JPH07219669A - Input circuit, clock generating circuit, and data processor - Google Patents

Abstract

PURPOSE:To reduce the temperature dependency and source voltage dependency of a clock skew. CONSTITUTION:The uninverted input terminal i11 and inverted input terminal i12 of a differential circuit 101 are connected to the inverted input terminal i22 and uninverted input terminal i11 of a differential circuit 102 equivalent to the differential circuit 101 respectively; and clocks Q1 and Q1' which are outputted from those differential circuits 101 and 102 corresponding to inputted clocks A and B are transmitted to a trailing-stage circuit. Then signal delay quantities of both the differential circuits 101 and 102 corresponding to temperature variation and source voltage variation are equalized to each other to reduce the temperature dependency and source voltage dependency of the clock skew.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing skew temperature dependency and power supply voltage dependency, and for example, clock generation for taking in an original clock signal generated by an oscillator to generate a multi-phase clock. The present invention relates to a technology effective when applied to a circuit and a computer system as an example of a data processing device.

[0002]

2. Description of the Related Art A multi-phase clock is used as an operating clock for each functional module constituting a computer system. Such a multi-phase clock is basically formed by appropriately dividing an original clock obtained by an original clock oscillator including a crystal oscillator or the like by a frequency dividing circuit. A clock input circuit is provided as a circuit for incorporating the original clock in such a frequency dividing circuit.

As shown in FIG. 7, for example, the clock input circuit includes a differential circuit 72 to which the output clock of the original clock oscillator 71 is input, and buffers 73 and 74 arranged at the subsequent stage thereof. Composed. The differential circuit 72 has a non-inverting input terminal (positive side input terminal) and an inverting input terminal (negative side input terminal), and a non-inverting output (positive side) according to clock input to these two terminals. Output) and inverted output (negative terminal). The non-inverted output and the inverted output are clock signals of complementary levels whose phases are shifted from each other by 180 degrees. The output clock of such complementary level is transmitted to the frequency dividing circuit in the subsequent stage via the buffers 73 and 74.

An example of a document describing a clock is Japanese Patent Laid-Open No. 64-2334.

[0005]

As described above, the phase shift (called "skew") of the clock signals output from the non-inverting output terminal and the inverting output terminal of the differential circuit 72 is often caused. This adversely affects the timing of the phase clocks and leads to a shortage of system operation margin. This becomes remarkable as the clock frequency becomes higher. Therefore, in the clock input circuit that takes in the original clock, as shown in FIG. 7, a load circuit 75 is provided at the inverting output terminal of the differential circuit 72 in addition to the buffers 73 and 74, and the differential circuit 72 By adjusting the load capacitance viewed from the inverting output terminal, in other words, adjusting the clock delay amount there, the complementary level of the complementary level transmitted from the differential circuit 72 to the subsequent circuit via the buffers 73 and 74 is adjusted. The skew of the clock signal is reduced.

However, the process variation of the elements of the semiconductor integrated circuit and the variation coefficient of the temperature characteristic and the power supply voltage characteristic are usually largely different depending on the circuit configuration, and even if the clock skew is small under a certain fixed condition, the temperature The present inventor has revealed that the clock skew undesirably increases due to the fluctuation of the power supply voltage. That is, even when the clock skew at the time of manufacturing the semiconductor integrated circuit is in accordance with the specifications, such a semiconductor integrated circuit is mounted in the computer system, and due to the temperature rise of the element due to a long-time energized state and the like, and the power supply voltage fluctuation, the buffer 73 , 74, the delay amount of the complementary level clocks varies, resulting in a large clock skew. This is a cause of causing an undesired phenomenon such as a defective operation margin in a system including such a clock input circuit.

An object of the present invention is to determine the temperature dependence of skew,
Another object of the present invention is to provide an input circuit with reduced power supply voltage dependency.

Another object of the present invention is to provide a clock generation circuit for generating a multi-phase clock with less skew temperature dependency and power supply voltage dependency.

Further, another object of the present invention is to provide a data processing device whose operation is stabilized by using a multi-phase clock whose skew has less temperature dependence and power supply voltage dependence. is there.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a first differential circuit having a non-inverting input terminal and an inverting input terminal, and a second differential circuit equivalent to the first differential circuit are provided, and the first differential circuit is provided. The non-inverting input terminal and the inverting input terminal of the circuit are respectively coupled to the inverting input terminal and the non-inverting input terminal of the second differential circuit, and the output terminal and the second difference of the first differential circuit are connected. The input circuit is configured to form a complementary level signal with the output terminal of the driving circuit. At this time, the signal can be used as a clock signal.

Further, a clock input circuit for taking in an output clock signal of an original clock oscillator for generating a clock signal of a predetermined frequency, and a multi-phase clock based on the clock signal taken in through this clock input circuit. When the clock generation circuit is configured to include a logic circuit for generation, the input circuit can be applied as the clock input circuit.

Further, a central processing unit for performing a predetermined arithmetic processing for data processing, a peripheral circuit thereof, and a multi-phase clock for generating a multi-phase clock for the operation of the central processing unit and the peripheral circuits. In the data processing device including the phase clock generation circuit, the clock generation circuit including the input circuit can be applied as the multi-phase clock generation circuit.

[0015]

According to the above means, the non-inverting input terminal and the inverting input terminal of the first differential circuit are coupled to the inverting input terminal and the non-inverting input terminal of the second differential circuit, respectively. That is, it operates so that complementary level signals are obtained from the output terminal of the first differential circuit and the output terminal of the second differential circuit in accordance with an input signal, and temperature fluctuation and power supply voltage The changes in the signal delay amount in both the differential circuits with respect to the change become equal to each other. so,
Aligning the signal delay amounts in the first differential circuit and the second differential circuit makes temperature dependence of skew in the input circuit,
And to reduce the dependency on the power supply voltage.

Further, in the clock input circuit arranged in the preceding stage of the logic circuit for generating the multi-phase clock, it is necessary to reduce the temperature dependence of the skew and the power supply voltage dependence in the output of the clock input circuit. The temperature dependence of the skew of the multi-phase clock generated based on it and the power supply voltage dependence are reduced.

Further, as described above, the output clock of the multi-phase clock generation circuit having less temperature dependency of skew and power source voltage dependency is supplied to the central processing unit and peripheral circuits.
Supplying them as the operation clocks ensures the securing of a predetermined operation margin in the central processing unit and the peripheral circuits, which achieves the stabilization of the operation of the data processing unit.

[0018]

FIG. 4 shows a computer system according to an embodiment of the present invention.

Computer system 40 shown in FIG.
Although 0 is not particularly limited, it functions as a server in the network system, and is configured as follows. That is, an original clock oscillator 502 for oscillating an original clock, and a main clock LSI (large size) for generating a multi-phase clock supplied to each unit of the computer system 400 of this embodiment based on the output clock of the oscillator 502. (Scale integrated circuit) 503, and a CPU 50 for performing arithmetic processing according to a preformed program
1, a memory 511 for holding various kinds of data, a memory controller 505 for controlling the operation of the memory 511, an operation of the CPU 501 and the memory controller 505 via the processor bus 509, the system bus 508 and the like. A CPU-memory control LSI 514 for controlling the serial I / O is further provided.
(Input / Output) I / O controller 506 for interface control and system bus 508
And an expansion bus adapter 507 for expansion of the. The original clock oscillator 502 is formed of a crystal oscillator or ECL (emitter coupled logic), although not particularly limited, and its output has a small amplitude level such as 0.8V.

The buffer main clock LSI 503 is
Although not particularly limited, a frequency of 60 MHz is obtained by including a clock input circuit 513 having an ECL configuration as will be described later, and dividing a clock signal input via the clock input circuit 513.
And various clocks of 30 MHz are generated. Although not particularly limited, a clock of frequency 60 MHz is
1, memory controller 505, CPU-memory control L
The clock having a frequency of 30 MHz, which is supplied to the SI 504, receives the I / O controller 506 and the expansion bus adapter 50.
7 is supplied. Also, the CPU-memory control LSI
504, the memory controller 505, the I / O controller 506, and the clock input unit of the expansion bus adapter 507 have phase adjustment circuits 514, 515, and 51 for adjusting the deviation of the clock phase in the clock transmission path.
6, 517 are provided respectively.

FIG. 3 shows the main clock LSI 50.
3 shows an example of the configuration of the main clock L. In FIG.
An example of a multi-phase clock generated by SI503 is shown.

As shown in FIG. 3, the main clock LS
I503 is not particularly limited, but the original clock oscillator 5
02 clock input circuit 513 for taking in the oscillation output
And a logic circuit 591 for generating a multi-phase clock supplied to each functional module shown in FIG. 4 based on the output clock of the clock input circuit 513,
It is formed on one semiconductor substrate such as a single crystal silicon substrate by using a known CMOS / LSI process.

In the present embodiment, since the output of the original clock oscillator 502 has a small amplitude level of the ECL level, the main clock LSI 503 uses the TTL (transistor Transistor logic) level multiphase clocks are output.

The output clocks of the clock input circuit 513 are Q1, Q1 ', Q2 and Q2'.
The clock Q1 and the clock Q2, and the clock Q1 'and the clock Q2' are in phase because the corresponding differential circuits are common. The original clocks A and B output from the original clock oscillator 502 are the clock input circuits 513.
Divided by 1/2 by such clocks Q1, Q
By inputting 1 ', Q2, Q2' to the logic circuit 591, a multiphase clock is formed.

The output clock Q2 of the clock input circuit 513 is divided by ½, ⅓, ¼ and ⅙ by frequency dividers 521, 522, 523 and 524, respectively. To be done. Selector 551 for selectively transmitting the frequency-divided outputs of frequency-dividing circuits 522-524 to the subsequent circuit
Is provided, and eight flip-flops 5 are provided in the subsequent stage.
41B is arranged. The output terminal of the flip-flop 541B is coupled to the selector 551 in the subsequent stage and the set terminal of the adjacent flip-flop. Further, four flip-flops 541A are provided in the subsequent stage of the frequency dividing circuit 521.
Is provided. The output terminal of the flip-flop 541A is coupled to the selector 551 in the subsequent stage and also to the set terminal of the adjacent flip-flop. further,
Output clocks Q2 and Q2 'of the clock input circuit 513
Are alternately input to the reset terminals of the plurality of flip-flops 541A and 541B. The selector 551 includes the plurality of flip-flops 541.
The output terminals of A and 541B are selectively transmitted to the set terminals of the plurality of flip-flops 561 in the subsequent stage. The reset terminals of the plurality of flip-flops 561 are connected to the output clocks Q1, Q1 ', Q of the clock input circuit 513.
Either 2, 2 or Q2 'is input.
That is, the plurality of flip-flops 561 are connected to the selector 55.
It is set in synchronization with the selected clock of 1 and reset by the output clock of the clock input circuit 513. The output clocks of the plurality of flip-flops 561 are transmitted to the plurality of buffers 581 via the 2-input NOR (NOR) circuit 571 in the subsequent stage. As described above, the logic circuit 591 is configured to generate clocks at different timings by combining the frequency dividing circuit and the flip-flop.
Then, the multi-phase clock is transmitted via the buffer 581 to the state shown in FIG.
Is supplied to each functional module as shown in FIG. Further, in order to balance the load seen from the output terminal of the clock input circuit 513, the equal load dummy circuit 562 is provided in the clock transmission path.

Further, a frequency dividing circuit 525 for frequency-dividing the output clock Q2 of the clock input circuit 513 is provided, and in synchronization with the output clock of the frequency dividing circuit 525, the control circuit 526 controls the selectors 531 and 551 to operate. The selection operation is controlled. It should be noted that when the reset signal RST is asserted, the control circuit 5
The control state of 26 is returned to the initial state.

FIG. 1 shows a configuration example of the clock input circuit 513.

As shown in FIG. 1, the clock input circuit 513 is not particularly limited, but two differential circuits 101 and 102 for buffering the output clock of the original clock oscillator 502, and the subsequent stages thereof are provided. The buffers 103, 104, 105 and 106 are arranged. The differential circuit 101 and the differential circuit 102 have non-inverting input terminals i11 and i21 and inverting input terminals i12 and i22, respectively.

In this embodiment, the non-inverting input terminal i11 of the differential circuit 101 and the inverting output terminal i22 of the differential circuit 102 are the same in order to reduce the temperature dependence of the clock skew and the power supply voltage dependence. Is input to the differential circuit 101 and the inverting input terminal i12 of the differential circuit 101 in the same manner.
The same clock is input to the inverted output terminal i21 of 02. Thereby, when the clock input terminal T11 is at a high level, a high level signal is obtained from the non-inverting output terminal 011 of the differential circuit 101 and a low level signal is obtained from the non-inverting output terminal of the differential circuit 102. To be On the other hand, when the clock input terminal T21 is at high level, the non-inverting output terminal O1 of the differential circuit 101 is
1 is set to low level, and the non-inverting output terminal O21 of the differential circuit 102 is set to high level. That is, the non-inverting input terminal i11 and the inverting input terminal i of one differential circuit 101
12 is the inverting input terminal i22 of the other differential circuit 102,
And non-inverting input terminal i21, respectively, and complementary level clocks can be obtained from the differential circuits 101 and 102 according to the original clocks input via the clock input terminals T11 and T21. However, this is one of the characteristic points of this embodiment. The output clock from the non-inverting output terminal O11 of the differential circuit 101 is
It is supplied to the logic circuit 591 shown in FIG. 3 via the buffers 103 and 105 in the latter stage, and the output clock from the non-inverting output terminal O11 of the differential circuit 102 is supplied to the buffers 104 and 106 in the latter stage. It is supplied to the logic circuit 591 shown in FIG. Although not particularly limited, the inverting output terminals of the differential circuits 101 and 102 are not used in this embodiment.

FIG. 2 shows a configuration example of the differential circuit 101 (102).

The differential circuits 101 and 102 have the same structure. Therefore, in the following description, only the differential circuit 101 will be described.

As shown in FIG. 2, this differential circuit 10
1 is, but not particularly limited to, the original clock having a small amplitude level amplitude of the ECL level from the original clock oscillator 502 is C
It includes a level shifter 201 for converting into a MOS level internal signal, a sense amplifier 202 for amplifying a differential output signal of the level shifter 201, and a buffer 203 for outputting an output signal of the sense amplifier 202. Become.

Although not particularly limited, the level shifter 201 is constructed as follows.

A p-channel MOS is used as a load for the differentially coupled n-channel MOS transistors N1 and N2.
Transistors P1 and P2 and P3 and P4 are provided. The p-channel type MOS transistors P1 and P3 are coupled to the high potential side power source Vdd. p-channel type MO
The S transistors P1, P2, P3 and P4 are fixed in the ON state by fixing their gate electrodes to the ground level. The source electrodes of the n-channel type MOS transistors N1 and N2 have n-channel type MO transistors.
A parallel connection circuit of S transistors N3 and N4 is coupled. This n-channel type MOS transistor N3, N
4 is connected to the ground via an n-channel MOS transistor N8. That is, when the externally applied enable signal EN2 is asserted to the high level, the n-channel type MOS transistor N8 is turned on, so that the level shifter 201 is turned on.
Is operated. n-channel MOS transistor N
The differential output of this level shifter is obtained from the drain electrodes of 1 and N2, and the differential output is transmitted to the sense amplifier 202 in the subsequent stage.

Although not particularly limited, the sense amplifier 202 is constructed as follows.

Differentially coupled n-channel type MOS transistors N5 and N6 are provided, and as a load thereof, a parallel connection circuit of p-channel type MOS transistors P5 and P6 and a p-channel type MOS transistor P7 are provided. An enable signal EN1 is input from the outside to the electrode of the p-channel type MOS transistor P5. An n-channel MOS transistor N7 is provided on the source electrodes of the n-channel MOS transistors N5 and N6, and the n-channel MOS transistor N7 is coupled to the ground via the n-channel MOS transistor N8. Since the gate electrode of the n-channel MOS transistor N7 is set to the high-potential-side power supply Vdd level, the enable signal EN
When 1 and EN2 are asserted to the high level, the sense amplifier 202 is operated. This sense amplifier 202
The signal output terminal of is the drain electrode of the n-channel MOS transistor N5, and is coupled to the buffer 203 described later so as to be able to transmit a signal.

The buffer 203 is a p-channel type MOS.
An inverter 211 including a transistor P8 and an n-channel MOS transistor N9 connected in series, a p-channel MOS transistor P9 and an n-channel MO.
An inverter 212 including an S-transistor N10 connected in series, an inverter 213 including a p-channel MOS transistor P10 and an n-channel MOS transistor N11 connected in series, a p-channel MOS transistor P11 and an n-channel MOS transistor N12. Includes an inverter 214 formed by connecting in series, and further includes a p-channel type MOS transistor P1.
2, P13 and n-channel MOS transistor N1
An inverter 215 formed by connecting N3 and N14 in series,
And an inverter 216 in which a p-channel type MOS transistor P14 and an n-channel type MOS transistor N15 are connected in series. The sense amplifier 20
The two output clocks are output via the inverters 211 to 214 and the inverters 211, 215 and 216, respectively. The output terminal of the inverter 214 is the non-inverting output terminal O11 of the differential circuit 101, and the output terminal of the inverter 216 is the inverting output terminal O12 of the differential circuit 101.

FIG. 5 shows an input signal waveform to the clock input circuit 513 constructed as described above and an output signal waveform in that case.

As shown in FIG. 5, original clocks A and B
Is a sine wave, the output clocks Q1, Q1 ', Q of the clock input circuit 513 that takes in such an original clock.
2, Q2 'are rectangular pulses of complementary levels. When the frequencies of the original clocks A and B input to the clock input circuit 513 are 120 MHz (one cycle is approximately 8.3 ns), for example, a 4-phase clock of 60 MHz is output, so that a clock phase difference of 240 MHz in the LSI. Need to occur. In the present embodiment, as shown in FIG. 1, the non-inverting input terminal i11 and the inverting input terminal i12 of the differential circuit 101 are connected to the inverting input terminal i22 and the non-inverting input terminal i21 of the other differential circuit 102. By respectively coupling and taking in the original clocks A and B, a clock equivalent to 240 MHz (half cycle is approximately 4.2 ns) is obtained from the differential circuits 101 and 102. In that case, if a temperature change or a power supply voltage change occurs, the output clocks Q1, Q1 are correspondingly changed.
Variations occur in the frequencies of ', Q2, Q2'. However, since the direction and amount of the variation are substantially the same in the differential circuits 101 and 102 formed on the same chip, at least the skew of the output clocks Q1, Q1 ′, Q2, Q2 ′ is extremely affected. Few. That is, although the high-level period and the low-level period of the output clocks Q1, Q1 ', Q2, Q2' fluctuate due to temperature changes and power supply voltage fluctuations, the fluctuation widths are almost equal, so the clock skew itself is almost the same. It doesn't change.

According to the above embodiment, the following operational effects can be obtained.

(1) In the clock input circuit, the non-inverting input terminal i11 and the inverting input terminal i of the differential circuit 101
12 is coupled to the inverting input terminal i22 and the non-inverting input terminal i21 of the differential circuit 102 which is equivalent to the differential circuit 101, respectively, according to the clocks A and B input via the clock input terminals T11 and T21. Lever differential circuit 10
Clocks Q1, Q1 ', Q output from 1, 102
2, Q2 'are configured to be transmitted to the logic circuit 591 in the subsequent stage, so that the signal delay amounts in the differential circuits 101 and 102 with respect to temperature fluctuations and power supply voltage fluctuations can be made equal to each other. Therefore, the fluctuation widths of the output clocks Q1, Q1 ′, Q2, Q2 ′ in the high level period and the low level period become substantially equal. As a result, even if the temperature fluctuation and the power supply voltage fluctuation fluctuate, the influence on the clock skew is small, so that the temperature dependence and the power supply voltage dependence of the clock skew in the clock input circuit 513 are reduced.

(2) Further, the clock input circuit 513 for taking in the output clock signal of the original clock oscillator 502.
And a logic circuit 591 for generating a multi-phase clock based on the clock signals A and B fetched via the clock input circuit, and the main clock LSI 503 as a clock generation circuit outputs the clock signal. The temperature dependence of the skew of the multiphase clock and the power supply voltage dependence can be reduced.

(3) Further, the computer system 400 is configured to include such a main clock LSI 503, and the output clock having less skew temperature dependency and power supply voltage dependency is the CPU 501 and its peripheral circuits. By supplying the data to the memory controller 505, the I / O controller 506, the expansion bus adapter 507, etc., in the CPU 501 and its peripheral circuits, at least the operation margin shortage and the operation abnormality due to the clock skew are eliminated. The operation of the computer system 400 as a processing device can be stabilized. Then, as described above, in the case where a margin can be provided in the operation margin by using the output clock having the low temperature dependency of the skew and the low power source voltage dependency,
The operating frequency of the computer system can be increased even higher.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the differential circuit 101,
I tried to use only the non-inverting output terminal of 102,
You may make it use an inverting output terminal.

Further, although the one including the two differential circuits 101 and 102 has been described, a large number of differential circuit pairs can be provided.

Further, although the clock skew is reduced in the above embodiment, the temperature dependence of the skew and the
Reducing the power supply voltage dependency may be important for various signals other than the clock, and in such a case, the temperature dependency of the skew and the power supply voltage dependency may be satisfied as in the case of the above embodiment. Can be reduced.

In the above description, the case where the invention made by the present inventor is mainly applied to a computer system functioning as a server in a network system, which is a field of application as the background, has been described, but the present invention is not limited thereto. However, it can be applied to, for example, a general-purpose computer or a single-chip microcomputer.

The present invention can be applied on the condition that at least a digital signal is handled.

[0050]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the non-inverting input terminal and the inverting input terminal of the first differential circuit are respectively coupled to the inverting input terminal and the non-inverting input terminal of the second differential circuit, so that the temperature fluctuation, Also, since the signal delay amounts in the differential circuits can be made equal to each other with respect to the power supply voltage fluctuation, the temperature dependence of the skew in the input circuit and the power supply voltage dependence can be reduced.

Further, in the clock input circuit arranged in the preceding stage of the logic circuit for generating the multi-phase clock, the temperature dependence of the skew and the power supply voltage dependence are reduced so that the output based on the clock input circuit is used. It is possible to reduce the temperature dependence and the power supply voltage dependence of the skew of the multi-phase clock generated as a result.

Furthermore, by supplying the output clocks of the multi-phase clock generation circuit, which has less skew temperature dependence and power supply voltage dependence to the central processing unit and the peripheral circuits as their operation clocks, Since it is possible to secure a predetermined operation margin in the central processing unit and the peripheral circuits, it is possible to stabilize the operation of the data processing device.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a configuration example of a clock input circuit included in a computer system that is an embodiment of the present invention.

FIG. 2 is a detailed configuration example circuit diagram of a differential circuit applied to the clock input circuit.

FIG. 3 is a block diagram of an overall configuration example of a main clock LSI included in the computer system.

FIG. 4 is a block diagram of an overall configuration example of a computer system that is an embodiment of the present invention.

FIG. 5 is an input / output waveform diagram of the clock input circuit.

FIG. 6 is an example timing chart of a multi-phase clock generated by the main clock LSI.

FIG. 7 is a circuit diagram of a conventional example to be compared with the clock input circuit.

[Explanation of symbols]

 101 differential circuit 102 differential circuit 103 buffer 104 buffer 105 buffer 106 buffer 201 level shift circuit 202 sense amplifier 203 buffer 400 computer system 501 CPU 502 original clock oscillator 503 main clock LSI 504 CPU-memory control LSI 505 memory controller 506 I / O controller 507 Expansion bus adapter 513 Clock input circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Noboru Masuda 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Inside Hitachi Central Research Laboratory

Claims (4)

[Claims] 1. An input circuit including a plurality of differential circuits each having a non-inverting input terminal and an inverting input terminal, wherein the non-inverting input terminal and the inverting input terminal of the first differential circuit are:
An inverting input terminal and a non-inverting input terminal of a second differential circuit, which are equivalent to the first differential circuit, are coupled to the output terminal of the first differential circuit and the second input terminal of the second differential circuit, respectively. An input circuit characterized by being capable of forming a signal of a complementary level with an output terminal of a differential circuit. 2. An input circuit including a plurality of differential circuits each having a non-inverting input terminal and an inverting input terminal, wherein the non-inverting input terminal and the inverting input terminal of the first differential circuit are:
The first differential circuit is coupled to the inverting input terminal and the non-inverting input terminal of the second differential circuit which is equivalent to the first differential circuit, and the first differential circuit is responsive to the clock input through the clock input terminal. An input circuit, characterized in that a complementary level clock can be formed between an output terminal of the circuit and an output terminal of the second differential circuit. 3. A clock input circuit for taking in an output clock signal of an original clock oscillator for generating a clock signal of a predetermined frequency, and a multi-phase clock based on the clock signal taken in through this clock input circuit. A clock generation circuit including a logic circuit for generation, wherein the input circuit according to claim 2 is applied as the clock input circuit. 4. A central processing unit for performing predetermined arithmetic processing for data processing, a peripheral circuit coupled thereto, and a multi-phase clock for operating the central processing unit and the peripheral circuit. 4. A data processing device including the multi-phase clock generation circuit according to claim 3, wherein the clock generation circuit according to claim 3 is applied as the multi-phase clock generation circuit.