JPH0721957B2 - Selective associative memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an associative memory device that stores and retrieves a symbol code as search data, and more particularly, an address translation system, a computer monitor and a debugger, and further stores knowledge information. The present invention relates to a selective associative memory device and its control method useful for an expert system for diagnosing with a computer.

[Prior Art] In general, an associative memory device stores some symbol codes and enables retrieval. That is, when the symbol code as the search data is input, if the symbol code is already registered, the registered address is output together with the match signal.
Even if a part of the symbol code is masked and input, the match signal can be output.

However, in the LSI associative symbol device, as the number of registered addresses increases, it becomes difficult to realize a priority encoder that can handle multi-match, and the processing time there becomes longer. The priority encoder has a range of 5 to 7 bits that is easy to make, and if it is made more than that, the circuit will be complicated rapidly as the number of bits increases.

On the other hand, the size of the symbol code is limited by the number of input terminals.
It is difficult to make it 64 bits or more, and in reality there are only 32 bits. Although a memory cell dedicated to associative memory is generally smaller than the case of using two cells for random access memory (RAM), an associative memory cell assuming a large symbol code does not become so small.

Therefore, considering the number of registered addresses and the size of the input symbol code, it becomes difficult to realize an associative memory LSI having a storage capacity of 128 × 64 bits or more. Of course, there are many applications in which such a capacity is sufficient.

However, the symbol data required for knowledge information processing and the like is configured by collecting a plurality of mutually related symbol codes, and even though each symbol code is short, the collected symbol data is considerably long. In terms of the number of short symbol codes that can be registered, the number of symbol codes to be registered in the associative storage device exceeds several thousand, which cannot be said to be sufficient with the conventional associative memory LSI.

[Problems to be Solved by the Invention] As described above, in the conventional associative memory device, when the memory capacity is increased to apply it to the knowledge information processing system, the number of symbol codes that can be registered is increased without decreasing the search speed. There is a problem of going to Japan. If the number of symbol data input terminals is fixed on the hardware side, it is required that large-sized symbol data can be accepted, but when registering a large number of small-sized symbol codes there, a large data size is required. Inefficient usage such as registering together and masking the part without data will occur. Furthermore, not only the part of the symbol data is associated with another part by registering the related symbol code group according to the structure of the semantic memory network, but also the part of the symbol data and the related predicate code are used to identify the other part of the symbol data. There is also a problem that the conventional associative memory device is difficult to use when performing a complicated search such as associating with.

An object of the present invention is to solve these problems.

[Means for Solving Problems] A selective associative memory device of the present invention includes a plurality of storage units for storing registration bit signals at intersections of word lines and bit lines selected by a part of a symbol code and a registration position code. A RAM matrix, a common writing means for the registered bit signal connected to a write circuit for each bit line of the RAM matrix, a registered address decoding means connected to a plurality of the common writing means corresponding to a plurality of bit lines, A wired-and-reading means for the registered bit signal read from the bit-line reading circuit, the encoding means connected to the plurality of wired-and-reading means corresponding to the plurality of bit lines, and each RAM matrix Data decoding means for selecting a word line and the read times of all bit lines for each RAM matrix. Masking means that always forces the output of the road to a match state,
Mode switch means for connecting the input terminals of the plurality of data decoding means to the symbol code input terminal and the area selection code input terminal are provided, and the symbol data consisting of the symbol code and its attribute code is provided to the symbol code input terminal and the area. It is characterized in that it is given to the selection code input terminal.

Further, in the selective associative memory device of the present invention, the number of RAM matrices is N and the number of input terminals of each data decoding means is K.
In the associative memory device with (> 2), before registering and retrieving symbol data, the mode switch means sets the number of area selection code terminals to B bits and the number of valid symbol code input terminals to (KB). ) The connection is switched so that it is set to N bits, the symbol code in the symbol data is input to the (KB) N-bit symbol code input terminal, and part or all of the attribute code is input to the area selection code input terminal. It is characterized by controlling to give.

Further, the selective associative memory device of the present invention inputs a plurality of concept codes included in the symbol data used for registration or retrieval and a relational predicate code indicating a semantic relation to the symbol code input terminal and the area selection code terminal, A part or all of the relational predicate code is assigned to the area selection code terminal, and the connection mode of the mode switch means is controlled so that the number of bits of the plurality of concept codes matches the number of valid symbol code input terminals. .

Further, the selective associative memory device of the present invention is used when the number of bits of the relational predicate code or the attribute code assigned to the area selection code input terminal in the symbol data used for registration or retrieval is masked for retrieval. The area selection code provided to the mode switch means is scanned.

[Operation] The search function for associative memory is executed by simply inputting the symbol data to the wort line selection decoder of the RAM memory matrix used for normal data storage and writing the registered bit signal "1" to the bit line. However, as the width of the symbol data increases, the utilization efficiency of the memory cell decreases. Conventionally, many small and subdivided RAM memory matrices have been combined to enable registration and retrieval of large symbol data. On the other hand, in the associative memory,
It has been considered that the encoding means and the registered position decoding means are commonly used in some associative memory matrices that store symbol data. This has led to the possibility of increasing the storage capacity and the storage density. However, in the associative memory device using the RAM matrix, when the associative memory matrix portion is selectively driven, there is a problem that the symbol data registered in some areas cannot be collated with the search data all at once.

Therefore, in the present invention, when registering the symbol data, the memory area is selected with a part of the symbol data.
Especially when the size of the symbol data is smaller than the number of input terminals of the symbol code, reduce the number of valid symbol code input terminals,
Instead, the number of area selection code input terminals is increased and all or part of the attribute code of the symbol code is assigned to the area selection code input terminal. As a result, the associative storage device capable of registering and collating large-sized symbol data has high storage efficiency when storing a large number of small-sized symbol data.

To explain a little more quantitatively, the number of RAM matrices is N
If the number of input terminals of the data decoding means of each RAM matrix is K, the area selection code is B bits, and the number of bit lines is M, conventionally there are only M symbol codes having a width of W = K × N bits. Although it could not be registered, in the present invention, when the symbol code width can be reduced to (KB) N bits, the area selection code is input to the input code of the attribute code of the symbol code and the relational predicate code between elements of the symbol code. The number of symbols that can be registered by entering the symbol code can be increased 2 ^B times.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, the selective associative memory device 100 includes a plurality of RAM matrices 110 for storing a registration bit signal in a memory cell 115 at an intersection of a word line 114 and a bit line 112 selected by a part of a symbol code and a registration position code. A common write means 120 for the registered bit signal connected to the write circuit 116 for each bit line 112 of the RAM matrix, and a plurality of bit lines 1
Registered address decoding means 125 connected to the plurality of common writing means 120 corresponding to 12 and each bit line 1
Wired-and-reading means 130 for the registration bit signal read from the twelve reading circuits 118.
An encoding unit 135 connected to the plurality of wired-and-reading units 130; and the RAM matrix 110.
Masking means 145 for constantly forcing the output of the read circuit 118 of all bit lines 112 to a match state, and each RAM matrix
Data decoding means for selecting 110 word lines 114
140, and mode switch means 150 for connecting the input terminals of the plurality of data decoding means 140 to the symbol code input terminals 101, 102, 103 and the area selection code input terminals 105 and 106.
It has and. The mode switch means 150 is a kind of multiplexer, and the switches 151 and 152 included therein are included.
By the control signal provided from the control signal input terminal 107, the input terminals 101, 102, 103 of the data decoding means 140,
Switch connection between 105 and 106.

The RAM matrix 110 is commonly used in most semiconductor memory LSIs, and it is a dynamic (D) RA.
Memory cells 115 such as M cells, static (S) RAM cells, and electrically rewritable e-read only memory (EAPROM) are arranged at the intersections of bit (horizontal) lines 112 and word (vertical) lines 114.

The number of memory cells 115 intersecting the bit lines 112 is equal to the number of word lines 114 selectively driven by the data decoding means 140, and 2 ³ = 8 when the input of the data decoding means 140 is 3 bits. The symbol code is registered depending on which of the eight memory cells 115 along the designated bit line 112 the registration bit signal "1" is written to. At the time of search, the search symbol code and the registered symbol code are collated depending on whether the signal read from the memory cell 115 selected by the symbol code input to the data decoding means 140 is the registered bit signal of "1". Done. To be more precise, the registration and search of the symbol code is performed as follows.

First, when registering a symbol code, each data decoding means 14 is provided in each part of the symbol code given from the input terminal 101.
Select the word line 114 via 0 and match it to the input terminal 108
An address code designating a registration position is given to the common writing means 125 of the row selected thereby, and a registration bit signal of "1" is given. Thereby the common writing means
The write operation of the registration bit signal of "1" starts from all the write circuits 116 connected to 125. Prior to this, the area selection code input terminals 105 and 106 are provided with an attribute code indicating the type of symbol code. Only in the area selected in each RAM matrix 110, the data decoding means 140
In the memory cells where the word line 114 selected by and the bit line 112 selected by the address decoder intersect, the registered bit signals of "1" are written all at once.

Next, when a symbol code is given to the input terminal 101 as search data, whether or not the symbol code matches the symbol code registered in the RAM matrix 110 is determined by "1" from all the read circuits 118 in each row. It depends on whether or not the registration bit signal is output. When the output from all the read circuits is "1", the wired and read circuit 130 is "1".
The match signal of is output. The encoding unit 135 detects which row of the read circuit 130 has output the match signal of “1”, and outputs the registered position address of the matched symbol code from the output terminal 109.

In addition, erasing the data registered in the RAM matrix 110
In many semiconductor LSI memories, this is achieved by a clear operation at every RAM matrix unit, but to erase only the symbol code registered in a specific area of a specific row, “0” is set in the common write circuit 120 of the specific row. The erase bit signal of is set and the input terminals of the data decoding means 140 connected to the input terminal 101 are sequentially input (scanned) from “0” to “1”, and all RAM matrices 110 are connected in parallel. When the write operation is performed twice to "0", the erase operation is completed. Rewriting of the registered symbol code is achieved by registering the new symbol code after erasing.

If the area selection code is 1 bit instead of 2 bits, the two input terminals 101, 1 of each data decoding means 140
The symbol code is entered in 02. In that case, the two input terminals of each data decoding means 140 are scanned from "00" to "11", and the "0" write operation is performed in parallel in all RAM matrices 110 four times to erase the data. The operation ends.

The mode switch means 150 is a part for selecting an input signal applied to the three input terminals of each data decoding means, one of them is always connected to the input terminal 101, and the other two are respectively input. Can it be connected to terminals 102 and 103?
Alternatively, it can be connected to the input terminals 105 and 106. Which one is connected is determined by the mode control signal given from the input terminal 107. The mode control signal controls two sets of switches 151 and 152 in the mode switch means 150.

When switches 151 and 152 are respectively connected up and down, the input terminals 105 and 106 are disabled. At that time, input terminals 101 and 1
02 and 103 are used, and it is possible to input a symbol code having a width three times the number N of the data decoding means 140. On the other hand, when the two sets of switches 151 and 152 are obliquely connected, the input terminals 102 and 103 are disabled, and instead the input terminals 105 and 106 are replaced.
Becomes effective. Since this input terminal selects only 1/4 of the memory areas in each RAM matrix 110, it is called an area selection code input terminal. Since the input terminals 102 and 103 cannot be used, the code width of the symbol code is N. At this time, since there is a 2-bit area selection code, the code width N
You can register 4 symbol codes of.

When the switch 151 is vertically connected and the switch 152 is obliquely connected, the input terminals 101 and 102 and the input terminal 106 are enabled and the input terminals 103 and 105 are disabled. At this time, the code width of the symbol code becomes 2N, and since there is a 1-bit area selection code, two symbol codes having a code width of 2N can be registered.
In this way, the mode switch means 150 serves to adjust the code width of the symbol code.

Here, when a mask signal is applied to the masking means 145 from the input terminal 104, the reading circuit 1 connected to the masking means 145
18 outputs are always set to "1". This makes it possible to collate symbol codes that are partially ignored. For example, if 11010101 is given as search data after registering 11000101, normally no match signal is output. However, if a mask signal is given to the 4th bit from the beginning, "1" of the 4th bit is ignored and a match signal is output.

2 (a), (b) and (c) are explanatory views of the control system by the mode switch means 150 in FIG. First
As shown in the figure, the number of RAM matrices 110 is N.
Then, it is assumed that the number K of input terminals of each data decoding means 140 is 3, and the data area that can be registered is 6 for 6 rows because of the size limitation of the drawings described. Therefore, if there is no mode switch, only 6 symbol codes with a code width of 3N can be registered. In the figure (a), the area selection code is 0.
In the case of bits, a symbol code having a code width of 3N is registered in the associative storage device 100 and searched. When N and K are large, the code width of the symbol code that can be registered or searched becomes large. However, when the code width of the symbol code is smaller than 3N, a mask signal may be given to the input terminal 104 of the masking means 145 of the RAM matrix connected to an unused input terminal to register or search, resulting in a large waste.

The second (b) is when the area selection code is 1 bit (mode (b)), the symbol code width of the input symbol code 200 is reduced to 2N, and instead, up to 12 symbol codes with a code width of 2N are registered. To be done. Since the mode switch 150 inputs the input symbol code into only one of the two memory areas, the matching between the input symbol code and the symbol code can be performed in only one of the two memory areas at the same time. That is, selective associative memory occurs.

FIG. 2 (c) shows a case where the area selection code is 2 bits (mode (c)), the code width of the input symbol code 200 is reduced to N, and instead, the number of memory areas that can be selectively accessed is increased to four. The number is increased, and up to 24 symbol codes with a code width of N can be registered.

Points to be noted here are: (a) In the mode (a) where the code width is 3N, part of the symbol data is masked in 3-bit units, and in the mode (b) where the code width is 2N, in 2-bit units. In addition, in the mode (c) where the symbol code width is N, it is in 1-bit units. (B) In the mode (a) where the symbol code width is 3N, there are 8 memory cells for a 3-bit symbol code. Using
In the mode (b) with a symbol code width of 2N, 4 memory cells are used for a 2-bit symbol code, and in the mode (c) with a symbol code width of N, 2 memory cells are used for a 1-bit symbol code. Using the memory cell of.

Considering the free seat with the mask bit width of (a) above and the memory cell utilization efficiency of (b), if the symbol code width is smaller than N, the number of valid symbol code input terminals is 3N and 6 symbols It is better to set the number of valid symbol code input terminals to 2N so that 12 symbol codes can be registered than to register the code. Furthermore, if the number of valid symbol code input terminals is N, 24 It is better to be able to register the symbol code. If you want to be able to register a 128-bit symbol code, set K to 4 and N to 32 and use it in mode (a). If the symbol code width is 32 bits, which is much shorter than 128, Is advantageously used in mode (c). Here is the existence value of the selective associative memory device that can increase or decrease the number of registrations according to the symbol code width.

The selective associative memory circuit of the mode (c) has a problem that the input symbol code is not simultaneously compared with all the symbol codes, instead of increasing the number of symbol codes. However, the problem can be avoided by devising the usage method. The usage method will be described below.

FIG. 3 shows an example of data of symbol codes registered in the selective associative memory of mode (c). At the beginning of the four data, a 2-bit attribute code 301 indicating the attribute of the symbol code 302 is added before the symbol code 302. When this attribute code is given from the input terminals 105 and 106, since the attribute codes are not the same, four data are registered in different areas. At the time of search, the area is selected by the 2-bit attribute code 301 at the beginning of the search data, and the remaining symbol code 302 is collated with the registered symbol data in the selected area. The registration position code of the comprehensive result is given from the encoding means 135 and the input terminals 105 and 106.

In this case, it is impossible to search by masking the 2 bits of the head 301. However, it is rare that a mask occurs at all bit positions in a 16 to 64-bit symbol code, and only a few bits in it do not change. If you assign that part to the input terminals 105 and 106, there will be no practical problems.
For example, in the case where the classification of regular employees or not, the gender, the name, the place of origin, the affiliation, and the age are coded into a symbol code, the attribute codes such as the category and the gender may not be masked. There may be an inquiry that I want to know the name, affiliation, and age of a full-time male in Tokyo from the birthplace, but conversely, given the name, affiliation, and age, the person's gender or regular employee This is because it is considered that there will be no inquiry about the classification of whether or not.

If it is necessary to perform the search by masking the leading 2 bits, naturally, it is necessary to scan the leading 2 bits sequentially. That is, it is necessary to access four times.
Assuming that the cycle time Tc for search is 100 nsec each time and the leading bit is masked at a frequency of 1%, the average cycle time Ta is approximately Ta = 100 + (1/100) × 400 = 104 nsec, It doesn't grow that much.

In FIG. 1, the area selection code is up to 2 bits,
If the number of bits is increased to 3 bits or 4 bits, the number of memory cells 115 that the read circuit 118 and the write circuit 116 at both ends of each bit line 112 handle is increased, and the storage density when viewed as an associative memory cell is increased. The fact that one of the two cells is always "0" is also effective in increasing the memory density. Further, when only the number of memory cells is increased without increasing the size or the number of the encoding means 135, the registered address decoding means 125, and the data decoding means 140, the increase in the chip size due to the increase in the storage capacity becomes small. Assuming that the area of the RAM matrix 110 occupies only 1/8 of the whole chip, the chip size can only be doubled even if the memory capacity of the RAM matrix 110 is increased by 8 times.

If the number of registered memory areas can be increased without increasing the chip size, the number of leading bits of the data in FIG. 3 will increase from 2 bits to 3 bits or 4 bits. Even in that case, there is data that can be assigned to it, and in many cases, attribute data such as the year and month of data creation, the affiliation of the creator, and the name of the data are useful as such data. In other words, he often makes inquiries about the data entered by Mr. A one year ago, but it seems unlikely that he will search for the creator or year of creation by giving some data. Of course, if a rare case occurs, the search time will increase slightly at that time.

Reconsidering the symbol data as the one to which the symbol code and the attribute code are added (that is, when the symbol code and the attribute data are paired and registered as one symbol data),
In mode (a), the attribute code cannot be assigned to the area selection code input terminal, but in mode (c), the attribute code can be assigned to the area selection code input terminal.
As a result, the registration capacity of the symbol data is substantially increased. That is, assuming that the number of bits of the area selection code is B, the number of RAM matrices is N, and the number of input terminals of the data decoding means is K, N × 2 ^K memory cells are used per bit line and the mode (a) In this case, symbol data having a data width of K × N can be registered or searched. In the mode (c), the width of the symbol data is from K × N to (K−
B) × (N + B), but instead the number of symbol data that can be registered increases 2 ^B times. Letting the product of the data width of the symbol data and the number of symbol data that can be registered per bit line be the registration capacity C, the registration capacity C is C = 2 ^B × (N + B) × (K
-B) increase. Here, assuming that the ratio of the registered capacity C to the number of memory cells per bit line (2 ^K × N) is the memory cell utilization efficiency, when K is 3, B = 0 in mode (a), C = 1 × 3N and the memory cell utilization efficiency is 3/8, but when B = 2 in mode (c), C = 4 × (N +
2), and the memory cell utilization efficiency is halved. This is due to the improvement of the memory cell utilization efficiency and the increase of the storage ratio of the attribute code. When N = 16, C was 48 in mode (a), but C = 72 in mode (c).
become.

FIG. 4 shows the registration capacity C of the symbol data that can be registered and the number N of the data decoding means 140, assuming K−B = 1.
Shows the relationship with. As a parameter, B in the number K = B + 1 of input terminals to each data decoding means is changed. The vertical axis 401 records the registered capacity C of the symbol data that can be registered, and the horizontal axis 402 records the value of N. The solid line shows the case where the mode switch means 150 is in the control mode (a), and the broken line shows the case where it is in the control mode (c). as mentioned above,
In the case of mode (a), C = (B + 1) · N, and in the case of mode (c), C = 2 ^B (N + B). When B becomes 2 or more, it is more advantageous to use in mode (c). In particular, B
It is shown that the number of registered data in the mode (c) is significantly large when 4 is 4, and the increasing effect is large even when N is small. For example, when B = 4 (K = 5) and N = 16, C = 80 in the mode (a), but C = 320 in the mode (c).

FIG. 5 shows an example of a relational predicate indicating a semantic relation between concepts. The left column shows the relational predicates, and the right column shows the outline of the meaning of each relational predicate. Relational predicate connecting concept codes A and B is-a
Means that A is B. The part-of connecting A and B means that A is part of B. A-kind connecting A and B
-of means that A is a kind of B. I connecting A and B
instance-of means that A is an example of B.

FIG. 6 is an example of description of knowledge information by a semantic network. In each table, each row shows a relational predicate indicating concepts and their meaning relations. The first column 610 shows the relational predicates, the second column shows the symbol code 620 of the antecedent part concept, and the third column shows the symbol code 630 of the consequent part concept in the form of words. The relational predicate code of each line and the symbol code of two concepts are registered in the associative memory as one symbol data, and by giving either the antecedent part or the consequent part of the relational predicate code and the symbol code of the concept, Associating the symbolic code of a concept, infer one concept of interest in the semantic network to another related concept. In order to make associations using relational predicates a base, when associating one concept with another using an associative memory device that stores symbolic data of semantic relations, a search is performed by masking the relational predicate code. There is no. Therefore, it is convenient to assign the relational predicate code to the area selection code input terminals 105 and 106. When the symbol code of each line is registered in the selective associative memory device of FIG. 1, the size of the symbol data in each column is usually small. 620 and the consequent part symbol data 630 are registered in the area 2. Therefore, a total of 12 symbol codes are registered in order to store the symbol data on the 4th row in FIG. A storage capacity (12N) for 12 pieces of N-bit data will be used. In that case, the search using the relational predicate part-of and the symbol code "meat" in the antecedent part is as follows.
First, Elijah 0 is selected and a search is performed using a part-of relational predicate. As a result, the second line matches. Next, when the area 1 is selected and the antecedent part symbol data is “meat”, the second line and the third line match. It was the second line that matched both Elijah. However, there is a more efficient registration method for storing symbol data consisting of concepts connected by relational predicates by making good use of the area selection code input terminal. That is, is-a is assigned to the first memory area, part-of is assigned to the second area, a-kind-of is assigned to the third area, and instance-of is assigned to the fourth memory area. After that, the concept code connected by each relational predicate code is registered in the area selected by the relational predicate code.

In the figure, when is-a and the first word (human) are given, a search is performed in the first memory area, and the registered address of the data is found. 2 using that address
The second word (animal) is revealed. Another word (flesh) can be derived from the second memory area using it and the following relational predicate (part-of). Using this and the following relational predicate (a-kind-of), the next word (food) can be derived from the third memory area. This word and the relational predicate (inst
By using the ance-of), it is possible to infer from the fourth memory area that "the human being can be (the meat) in some cases".

In the above description, the horizontal lines of the RAM matrix are called the bit lines and the vertical lines are called the word lines, but they can be named in reverse, and the above names limit the scope of the claims of the present invention. Not a thing.

[Effect of the Invention] As described above, according to the present invention, when the data width of the symbol code that can be accepted in the conventional associative memory device is increased, the registration and retrieval of the symbol code having a small data width are performed. It is possible to solve the structural problem that it is difficult to increase the registration capacity of the symbol code at the time of assigning by assigning the attribute code in the symbol data consisting of the symbol code and the attribute code to the area selection code input terminal. In addition, the relational predicate has a problem that the associative memory with the relational predicate code and a part of the conceptual code cannot be efficiently performed when storing the concept code connected by the relational predicate of the knowledge information expressed by the semantic network. There is an effect that it can be solved by assigning a code to the area selection code input terminal.

Further, the present invention can be applied not only to the storage of knowledge information, but also to address translation, computer monitors and debuggers, and can also be used for expert systems through the storage of knowledge information.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is an explanatory view of an operation mode of the embodiment shown in FIG. 3, FIG. 3 is an explanatory view showing an example of registration data, and FIG. 4 is a registration data bit number and N.
5 is an explanatory diagram of an example of relational predicates of the semantic network, and FIG. 6 is an example of description of knowledge information by the semantic network. 100 …… Selective associative memory device, 101-103 …… Input terminal for symbol code used for registration or search, 104 …… Input terminal for masking signal, 105,106 …… Input terminal for area selection code, 107 …… Control signal input terminal of mode switch means, 108 ... input terminal of symbol code registration position address, 109 ... output terminal of search result, 110 ... RAM matrix, 112 ... bit line, 114 ... word line, 115 ...... Memory cell, 116 …… Write circuit, 118 …… Read circuit, 120
...... Common writing means, 125 ...... Registered address / decoding means, 130 ...... Wired and reading means, 135 ...... Encoding means, 140 …… Data decoding means, 145 …… Masking means, 150 …… Mode switching means.

Claims (4)

[Claims] 1. A plurality of RAM matrices for storing registration bit signals at intersections of word lines and bit lines selected by a part of a symbol code and a registration position code, and a write circuit for each bit line of the RAM matrix. Connected to the common writing means of the connected registration bit signal, the registered address decoding means connected to the plurality of common writing means corresponding to a plurality of bit lines, and the read circuit of each bit line, and read from the read circuit. Registered bit signal wired-and-reading means, encoding means connected to the plurality of wired-and-reading means corresponding to the plurality of bit lines, data decoding means for selecting a word line of each RAM matrix, and the RAM matrix Separately, masking means for forcing the output of all bit line read circuits to always match , And a mode switch means for connecting the input terminals of a plurality of said data decoding means to the symbol code input terminal and Elijah select code input terminal,
A selective associative memory device, wherein symbol data composed of a symbol code and its attribute code is given to the symbol code input terminal and the area selection code input terminal. 2. The associative memory device according to claim 1, wherein the number of RAM matrices is N and the number of input terminals of each data decoding means is K (> 2). Before, the mode switch means switches the connection so that the number of area selection code terminals is set to B bits and the number of valid symbol code input terminals is set to (KB) N bits, and the (KB) N is set. The bit code code input terminal is controlled so that the code code in the code data and the area selection code input terminal are provided with a part or all of the attribute code. Selective associative memory. 3. A plurality of concept codes included in symbol data used for registration or retrieval and a relational predicate code indicating a semantic relation are input to a symbol code input terminal and an area selection code terminal, and a part of the relational predicate code or The connection mode of the mode switch means is controlled so that all of them are assigned to area selection code terminals and the number of bits of a plurality of concept codes matches the number of valid symbol code input terminals. A selective associative memory device as described. . 4. The mode switch means is provided when the number of bits of the relational predicate code or attribute code assigned to the area selection code input terminal in the symbol data used for registration or retrieval is masked and retrieved. The selective associative memory device according to claim 2 or 3, wherein the area selection code is scanned.