JPH0721779A - Semiconductor static memory integrated circuit - Google Patents

Abstract

PURPOSE:To prevent an operational margin and operational speed from being decreased by almost uniformizing and reducing amplitude of an input signal for a sense amplifier, even when the resistance of a bit line is increased. CONSTITUTION:One bit line BL1 (BL2) is provided with plural load transistors Q11, Q21, Q31 (Q12, Q22, Q32) at prescribed intervals. A load transistor nearest to memory cells (MC1-MCn) in a selecting state is turned on. Thereby, since the distance of a bit line between a connecting point of the load transistor and a connecting point of the memory cell in a selecting state is made short and voltage drop between them is made small, amplitude of an input signal for a sense amplifier is made small and uniformized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor static memory integrated circuit, and more particularly to a semiconductor static memory integrated circuit configured to read information by a voltage drop of a load element in which on / off currents of transistors of a memory cell flow through a bit line. Regarding

[0002]

2. Description of the Related Art At present, in a large-capacity semiconductor static memory integrated circuit, the bit line length is increased due to the increase in the number of memory cells connected to a pair of bit lines in accordance with the increase in the size, and on the other hand, Due to miniaturization, the line width of the bit line has been reduced. Due to these factors, the resistance of the bit line itself tends to increase, which causes deterioration of information read time and reduction of operation merge.

FIG. 2 shows a typical example of a conventional semiconductor static memory integrated circuit.

This semiconductor static memory integrated circuit has a pair of bit lines BL1 and BL2, a plurality of word lines WL1 to WLn insulated and intersecting with the bit lines BL1 and BL2, and a driving transistor Q1.
A flip-flop type memory unit MP having storage nodes N1 and N2, which includes Q2 and resistors R1 and R2, and a gate are connected to a corresponding word line (for example, WL1) and stored when the word line (WL1) is at a selected level. A plurality of memory cells MC1 to MCn respectively including switching transistors Q3 and Q4 for correspondingly connecting the nodes N1 and N2 and the bit lines BL1 and BL2, and the bit lines BL1 and BL2.
Bit lines BL1 and BL2 are connected between one end of each and a power supply potential point (power supply potential Vcc) and are turned on and off in response to turning on and off of transistors Q1 and Q2 for driving a memory cell corresponding to a word line of a selected level. Load transistors Q11 and Q12 for passing current through the bit lines BL1 and B
These bit lines BL1 and BL provided at the other end of L2
It has a configuration including a sense amplifier SA1 that amplifies the voltage between the two at a predetermined timing.

In this circuit, for example, the word line WL1
Becomes a high selection level, the switching transistors Q3 and Q4 of the memory cell MC1 are turned on, and the storage nodes N1 and NQ2 of the memory part MP and the bit line B are turned on.
L1 and BL2 are correspondingly connected. If, for example, the transistor Q1 is on and the storage node N1 is in the low level and N2 is in the high level information storage state, the power supply potential point (V
The current I ₁ flows from cc) to the transistor Q11 → bit line BL1 → transistor Q3 → transistor Q1. On the other hand, since the transistor Q2 is off, no current flows to the transistor Q12. As it is, the bit line BL1 becomes a potential (V ₁ ) lower than the power supply potential Vcc by the voltage drop due to the current I _1, and the difference potential V ₁ is supplied to the sense amplifier SA1 to store the stored information in the memory cell MC1. It is read.

Here, as described above, when the resistance rb of the bit lines BL1 and BL2 increases due to the large scale and miniaturization, the memory cell MC1 closest to the load transistors Q11 and Q12 is There is almost no voltage drop due to the resistance (rb) of the bit lines BL1 and BL2, but for the farthest memory cell MCn (closest to the sense amplifier SA1), the voltage drop due to the resistance (rb) of the bit lines BL1 and BL2. Becomes larger, the difference potential V1 supplied to the sense amplifier SA1 differs depending on the position of the memory cell, which causes a reduction in the operating margin of the sense amplifier SA1 and the like. Further, since the amplitude of the input signal (V ₁ ) of the sense amplifier SA1 increases, the operation speed also decreases accordingly.

[0007]

In this conventional semiconductor static memory integrated circuit, the load transistor Q is used.
11 and Q12 are provided at one end of the bit lines BL1 and BL2, and when reading stored information from the memory cells MC1 to MCn, the difference in voltage drop between the transistors Q11 and Q12 due to the current flowing through the bit lines BL1 and BL2 is determined. Sense amplifier S provided at the other end of BL1 and BL2
Since it is configured to perform amplification by A1, large scale,
As miniaturization progresses, the resistance (rb) of the bit lines BL1 and BL2 increases, and the sense amplifier SA1 depends on the connection position of the bit lines BL1 and BL2 of the memory cells MC1 to MCn.
Since the input signal amplitude to the
Further, there is a drawback that the operating speed is lowered due to the increase of the input signal amplitude.

It is an object of the present invention to reduce the operating margin by making the amplitude of the input signal to the sense amplifier substantially constant regardless of the bit line connection position of the memory cell even if the resistance of the bit line becomes high due to the increase in scale. Another object of the present invention is to provide a semiconductor static memory integrated circuit capable of avoiding a decrease in read operation speed.

[0009]

A semiconductor static memory integrated circuit of the present invention includes a bit line whose one end is connected to an input end of a sense amplifier, and a transistor for storing information, which is turned on / off depending on whether the transistor is turned on or off. A plurality of static type memory cells for storing a plurality of memory cells, a plurality of word lines which are provided corresponding to the plurality of memory cells and which connect the corresponding memory cells to the bit lines at the selection level, and one end of each of which is a power supply potential. Connected to a point and the other end to a predetermined position of the bit line at a predetermined interval and turned on in response to a selection level of a word line in a predetermined range. It has a plurality of load transistors that flow current according to on / off.

In addition, each of the plurality of load transistors is turned on in response to the selection level of a word line in a predetermined range corresponding to and adjacent to each of the transistors, and further, in a read standby state. At least 2 of the transistors for multiple loads when returning to
It has a configuration in which two are turned on at the same time.

[0011]

According to the present invention, the current of the transistor in the ON state of the memory cell flows through the load transistor closest to the memory cell in the selected state by the word line of the selected level. It can be shortened and made uniform. Therefore, even if the bit line resistance increases, the amplitude of the input signal to the sense amplifier can be made small and almost uniform regardless of the bit line connection position of the memory cell to prevent a decrease in operating margin. In addition, the operation speed can be prevented from lowering.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This embodiment differs from the conventional semiconductor static memory integrated circuit shown in FIG. 2 in that the load transistors (Q11, Q12 to Q31, Q32) are
Not only one end of the bit lines BL1 and BL2, but also provided at predetermined positions at predetermined positions of the bit lines BL1 and BL2 at a plurality of positions, these load transistors Q11 and Q12.
The point is that Q31 and Q32 are turned on in response to the selection level of a word line in a predetermined range corresponding to and close to each of these transistors.

For example, if n = 10 in FIG.
The word lines for turning on the transistors Q11, Q12 connected to the ends of the bit lines BL1, BL2 are WL1, WL
2. The word lines that turn on the transistors Q21 and Q22 are the bit lines BL1 and B of the transistors Q21 and Q22.
Memory cells MC3 connected to both sides of the connection point of L2
To MC6 (MCkhMC (k + 1) in FIG. 1) corresponding word lines WL3 to WL6 (WLk, WL (k + 1)),
Similarly, for the transistors Q31 and Q32, word lines WL7 to WL10 (WL (m-1), WLm to WL).
n).

In this way, one bit line BL1 (BL
2) Multiple load transistors Q11, Q21, Q
If 31 (Q12, Q22, Q32) is provided and the load transistor closest to the selected memory cell is turned on, the bit line for the current flowing through the load transistor and the selected memory cell transistor can be changed. Since the distance can be shortened and the voltage drop due to the bit line resistance is reduced, the input signal to the sense amplifier SA1 is irrespective of the connection position with the bit line of the memory cell even when the bit line resistance increases. The amplitude can be made substantially uniform and small, and therefore the sense amplifier SA1
It is possible to prevent a decrease in operation margin and a decrease in operation speed.

In addition, the bit line BL to the read standby state
When it is necessary to precharge and equalize 1 and BL2, load transistors Q11, Q12 to Q31, Q
By turning 32 on at two or more locations, high-speed precharging and equalization are possible.

[0018]

As described above, according to the present invention, one bit line is provided with a plurality of load transistors at predetermined intervals, and the load transistor closest to the selected memory cell is turned on. By doing so, it is possible to shorten the path of the current flowing from the load transistor in the bit line, so even if the bit line resistance increases due to a large scale, etc., the sense line is not affected regardless of the connection position with the bit line of the memory cell. The amplitude of the input signal to the amplifier can be made substantially uniform and small, so that there is an effect that the decrease of the operation margin and the operation speed can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional semiconductor static memory integrated circuit.

[Explanation of symbols]

BL1, BL2 bit lines MC1 to MCk, MC (k-1) to MC (m-1), M
Cm to MCn memory cell PM memory unit Q1 to Q4, Q11, Q12 to Q31, Q32 transistor R1, R2 resistance SA1 sense amplifier WL1 to WLk, WL (k-1) to WL (m-1), W
Lm to WLn word line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G11C 11/34 354 D

Claims (3)

[Claims] 1. A bit line having one end connected to an input end of a sense amplifier, a plurality of static type memory cells each including an information storage transistor for storing information according to ON / OFF of the transistor, and a plurality of these static type memory cells. A plurality of word lines which are respectively provided corresponding to the memory cells and connect the corresponding memory cells to the bit lines at the selection level, and one end of each word line is connected to a power supply potential point and the other end is a predetermined position of the bit line. A plurality of load transistors that are connected at a predetermined interval to turn on in response to a selection level of a word line in a predetermined range and flow current according to turning on / off of a transistor of a memory cell corresponding to the word line of this selection level. A semiconductor static memory integrated circuit comprising: 2. A semiconductor static memory integrated circuit according to claim 1, wherein each of the plurality of load transistors is turned on in response to a selection level of a word line in a predetermined range corresponding to and adjacent to each of the transistors. . 3. The semiconductor static memory integrated circuit according to claim 1, wherein at least two of the plurality of load transistors are turned on at the same time when returning to the read standby state.