JPH0721406A - Stereoscopic image processor - Google Patents

Abstract

PURPOSE:To provide a stereoscopic image processor capable of preventing the generation of moire, etc., even on a mapped polygon face and quickly executing antialiasing processing. CONSTITUTION:This stereoscopic image processor is provided with a memory 1 for storing the end point information of X and Y constituting a polygon and a distance from the visual point of each polygon, a geometric transformation device 3 for geometrically transforming the end point information read out from the memory 1, an external processor 7 for transforming the address information of a polygon outline into the information of a polygon outline part in each scanning line, an internal plotting processor 9 for detecting the position of a polygon edge based upon respective address information of two opposed sides calculated by the processor 7 and the distance from the visual point of each polygon, an antialiacing processor 11 for applying filter operation only to the picture information of polygon edges, and a CRT 12 for displaying the picture information obtained from the processor 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-dimensional image processing apparatus for displaying a high-quality image at high speed without aliasing in a three-dimensional image representing a three-dimensional image.

[0002]

2. Description of the Related Art Two-dimensional (plane) such as CRT display
There is known a method of displaying a three-dimensional solid figure on a display device by using a scan line algorithm when the three-dimensional figure is displayed by perspective conversion processing, perspective processing, and the like.

The scanline method is one of the most common hidden surface removal algorithms and is used in many stereoscopic image processing devices because it can generate a relatively high quality picture in a relatively short time. .

By the way, it is known that when a graphic is displayed on a raster display such as a CRT, jagged lines called "jaggies" are formed at diagonal line segments and polygon boundaries. These phenomena are one of the phenomena called aliasing.

In the generation of an image, sampling is often performed at a finite number of points in which figures and objects are arranged in a grid, but in this case aliasing occurs.

When this aliasing occurs, the following problems occur. (1) Jaggies occur. (2) Small or elongated objects may not be displayed. (3) A moire pattern occurs in an image that is periodically distributed, such as mapping. (4) Partial lack of highlights and patterns.

For high quality image generation, it is necessary to solve the problem of aliasing. As a method for removing this aliasing, anti-aliasing (an
ti-aliasing). The anti-aliasing method in the scan line method is performed by passing several scan lines in one pixel, obtaining the color ratio of each polygon in one pixel, and obtaining the color of the pixel.

However, since the anti-aliasing method based on the scan line method requires a plurality of scan line processes for one pixel, it requires a great deal of program complexity and execution time, and requires real-time processing. It is difficult to use for some systems.

On the other hand, as a method for performing high-speed anti-aliasing, there is a method of applying a digital filter using a 3 × 3 filter or the like to the screen.

[0010]

However, in the above digital filter processing, since the filter operation is performed on the mapped polygonal surface, there are problems such as more severe jaggies and moire. In order to eliminate these problems, it is possible to deal with the problem by increasing the number of pixels in the mapping data. However, increasing the number of pixels in the mapping data significantly increases the processing time and requires real-time processing. Difficult to use in systems with

The present invention has been made in order to solve the above-mentioned problems, and it is possible to perform high-speed anti-aliasing processing on a mapped polygonal surface without generating moire or the like. An object of the present invention is to provide an image processing device.

[0012]

A stereoscopic image processing apparatus according to the present invention comprises storage means for storing X and Y end point information forming a polygon and distances from the viewpoint of each polygon, and end point information from this storage means. A geometric transformation means for geometrically transforming
Between the outline processing means for converting the address information of the polygon outline into the information of the polygon outline portion for each scan line based on the end point information from the geometric conversion means, and between the two opposing sides calculated by the outline processing means. Means for detecting the position of the polygon edge based on each address information and the distance from the viewpoint of each polygon, anti-aliasing processing means for performing a filter operation only on the image information of the polygon edge, and image information from this anti-aliasing processing means. And display means for displaying.

Further, the anti-aliasing processing means is provided with means for changing the coefficient of the filter calculation according to the distance from the viewpoint of the polygon. Strongly anti-aliasing is applied to a distant polygon and a near polygon is applied. On the other hand, it is better to configure the anti-aliasing to be weak.

[0014]

According to the present invention, only the image information (dots) corresponding to the polygon edge is subjected to the filter calculation, and the filter calculation is not performed to the other parts, so that the jaggies and moire are eliminated and the anti-aliasing processing is performed at high speed. This makes it possible to display polygons on a display device such as a CRT in real time.

Furthermore, the coefficient of the filter calculation is changed according to the distance from the viewpoint of the polygon so that anti-aliasing is strongly performed on a distant polygon and weak anti-aliasing is performed on a near polygon. By doing so, a more realistic display can be performed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of a pseudo three-dimensional image processing apparatus using the present invention. This apparatus is an example suitable for use in a game machine such as a racing game or an airplane control simulation. It is shown. The overall configuration of the present invention will be described with reference to FIG.

In this embodiment, the simulation image under various conditions is used as a plurality of polygon information, and the end point information of each polygon is given to the polygon end point memory 1 as X, Y, Z coordinate values. Furthermore, this polygon end point memory 1
The end point information indicating the mapping pattern area of the basic pattern of the pattern to be given to the polygon surface is stored in.

The CPU represents all three-dimensional objects (objects) as an aggregate of a plurality of polygons, reads out end point information indicating each end point of this polygon, and operates an operation unit (not shown) constituted by handle access or the like. The situation data corresponding to this situation is calculated according to the electric signal converted based on the content, and the data is given to the geometric conversion device 3.

The geometric conversion device 3 reads the end point information data of each polygon from the polygon end point memory 1 while referring to various polygon data in accordance with a command from the CPU, and converts the value of the end point of the polygon in the visual line direction, the visual field conversion, The end point coordinates of each polygon are geometrically transformed by the perspective projection transformation, and the end point data indicating the X and Y two-dimensional screen data and the mapping pattern area to be given to the polygon surface are given to the screen memory 4. Further, a field-converted representative value of the center of the polygon, that is, a representative value (Z value) of the distance from the viewpoint of the polygon is determined, and the data is given to the screen memory 4.

The outer shape processing device 7 is an end point of each side forming the polygon from the screen memory 4, that is, an X start point address (XS), an end point address (XE), and a Y start point address (YS) and an end point address ( YE), and the start point address (MXS), X end point address (MXE), Y start point address (MYS), and Y end point address (MYE) of the mapping pattern that constitutes the basic pattern.

The contour processing device 7 calculates the contour edge information of each side while interpolating the address of the mapping pattern for polygon contour processing, and supplies the calculated data to the frame memory 8. Details of the outer shape processing device 7 will be described later.

Further, in the frame memory 8, each data given from the contour processing device 7, that is, the value of the left side X and the right side X of the polygon and the mapping memory address of the left side of the polygon for each horizontal line (scan line), and the right side are stored. The mapping memory addresses and are stored respectively.

Each data stored in the frame memory 8 is given to the internal drawing processing device 9, and the internal drawing processing device 9 interpolates each data inside the polygon. Details of the internal drawing processing device 9 will be described later.

Each data inside the polygon interpolated by the internal drawing processing unit 9 is processed by the anti-aliasing processing unit 11.
Given to. This anti-aliasing processing device 11
Are given address data from the mapping pattern memory 10 in which the lookup table address of the mapping pattern is stored and data from the internal drawing processing device 9.

This anti-aliasing processing device 11
Performs an anti-aliasing process by performing nxn filter calculation on the number of turns of the polygon edge only at the polygon edge of each polygon, and sends the data to the CRT 12. If it is not a polygon edge, the data is CR without antialiasing processing.
Send to T12.

Furthermore, the anti-aliasing processing device 11 of this embodiment is configured so that the parameter for filter calculation is changed according to the distance from the viewpoint, that is, the Z value of the polygon. Anti-aliasing is strongly performed on an object, and anti-aliasing is weakly performed on a near object so that a more realistic display is performed. Details of the anti-aliasing processing device 11 will be described later.

From the anti-aliasing processing device 11, the filter data is applied only to the dot portion corresponding to the polygon edge, and the image data not subjected to the filter operation processing is applied to the other portion to the CRT 12, and the CRT 12 is supplied.
Real images with no jaggies or moire are displayed in real time.

Next, the outline processing device 7 and the internal drawing processing device 9 of the present invention will be described with reference to FIGS. 4 and 5.

In this embodiment, the polygon has the screen end point coordinates (X, Y) and the basic pattern, that is, the end point coordinates (MX, MY) of the mapping pattern, so that the basic pattern is transformed and mapped on the polygon surface. To do.

First, the polygon contour processing unit 7 performs polygon contour processing.

For this outer shape processing, the CPU determines in which direction the vector of each side forming the polygon is shown in FIG. 13 based on the start point and the end point of the XY address of each side read from the screen memory 4. Whether it belongs or not is determined, and the right side or the left side is determined according to the direction of the vector.

The screen memory 10 stores the screen end point coordinates (X, Y), the end point coordinates (MX, MY) of the mapping pattern, and the Z value of the polygon.

Then, in the polygon outline processing circuit 61,
The distance (DY) in the Y direction is calculated from the start point (YS) and end point address (YE) of the Y address of each side read from the screen memory 10. That is, the subtractor 62 calculates DY = YE-YS. Then, using this DY,
X end point (XE) of each side to obtain the polygon outline
To the X start point (XS) are obtained by digital differential analysis (DDA), and the data is stored in the frame memory 8
To store.

That is, the fine difference value is calculated as shown in the equation (1) of the following equation 1, and the interpolation calculation is performed as shown in the following equation (2) to calculate the X end point to the X start point of each side. Calculate the address.

[0036]

## EQU1 ## DDX = (XE-XS) / DY (1) X = X + DDX (2)

This operation is performed by the DDA operation circuit 63, and the subtracter 64 of the DDA operation circuit 63 causes XE-XS.
Is calculated and the calculation result is given to the divider 65. The DY value is given to one input of the divider 65 from the subtractor 62, the above formula (1) is calculated, and the calculation result is given to the interpolation circuit 66 which performs interpolation calculation.

The adder 67 of the interpolation calculation circuit 66 and the register 68 perform the interpolation calculation of the above equation (2) to obtain the outline data of the polygon from the start point (XS) to the X end point (XE) of X on each side. It is calculated and stored in the frame memory 8.

Further, the mapping pattern contour processing circuit 71 carries out contour processing of the basic pattern information. This processing changes the end point address (MX, MY) of the basic pattern stored in the screen memory 4.

Starting point addresses (MXS, MYS), (MX) of the basic pattern read from the screen memory 4
The data corresponding to the polygon from the address data of (E, MYE) is calculated by the digital differential analysis (DDA) based on the formulas (3) and (4) of the following mathematical formula 2 and the DDA arithmetic circuit 72
And calculated by the interpolation calculation circuit 75 and stored in the frame memory 8. That is, the end point data (MXE, MYE) of each side
From the start point data (MXS, MYS) to digital differential analysis (DDA) by the subtractor 73 and the divider 74.
Then, the data is obtained by the interpolating operation in the adder 76 and the register 77, and the data is stored in the frame memory 8.

First, as shown in equations (3) and (4), the fine difference value is calculated, and as shown in equations (5) and (6), interpolation calculation is performed to determine the end point to the start point of each side. Calculate the data. The initial value of MX in equation (5) is the starting point data (MYS), and the initial value of MY in equation (6) is the starting point data (MYS). The operations of the expressions (5) and (6) are repeated from 0 to DY.

[0042]

## EQU00002 ## DMX = (MXE-MXS) / DY ... (3) DMY = (MYE-MYS) / DY ... (4) MX = MX + DMX ... (5) MY = MY + DMY ... (5) 6)

In this embodiment, in synchronization with the horizontal scanning line, the contour address of the polygon and the contour address information of the basic pattern modified based on the contour are stored in the frame memory 8 for each Y address indicating the vertical position. It

The operation of the contour processing apparatus 7 will be described based on the operation flow of FIGS. 8 to 9 according to the circuit example of FIG.

First, the controller reads the number of polygons (P) from the polygon end point memory 1, then reads the number of polygon angles to be processed, and stores the number in the internal processing memory (steps S1 and S2).

Then, the start point (X
S, YS, MXS, MYS) are read (step S3), the address of the screen memory 4 is incremented (step S4), and then the end points (XE, YE, MXE, MYE) are read from the screen memory 4 (step S3). Step S5). A direction vector is calculated from the read start point (XS, YS) and end point (XE, YE) of the end point, and this side vector is set to the left side or the right side (step S6).

Then, the data of YE and YS from the screen memory 4 are given to the subtracter 62 which constitutes the difference circuit of the polygon outer shape processing circuit 61 of the outer shape processing device 7, and the distance DY between them is calculated (step). S7). This DY
Are supplied to the fine difference calculation circuit 63 and the fine difference calculation circuit 72 of the mapping pattern outer shape processing circuit 71, respectively.

The start point (XS) and end point (XE) data is given from the screen memory 4 to the subtracter 64 in the fine difference calculation circuit 63, and the subtraction result XE- from this subtractor 64.
XS is supplied to the divider 65.

In this divider 65, (XE-XS) / D
Division of Y is performed (step S8), and this value (DDX)
Is given to the adder 67 of the interpolation calculation circuit 66. The adder 67 performs an operation of X + DDX, writes this value in the register 68, and writes it from the register 68 to the frame memory 28 as the X address (step S9).

Further, one input of the adder 67 is a register 6
Since the output from 8 is given, this interpolation calculation circuit 66
At, an interpolation calculation is performed.

Then, in step S10, the mapping pattern outer shape processing circuit 71 inputs the end point addresses (MXS, MYS) and (MXE, MYE) of the read basic pattern from the screen memory 4.
This subtractor 73 allows MXE-MXS and MYE-M
The subtractor 83 performs the operation of YS, and the subtractor 83 performs the operation of TPE-TPS, and the operation result is given to the divider 74 and the divider 84.

DY from the subtracter 62 of the difference circuit is given to the dividers 74 and 84, and DY is divided with the above calculation result to calculate a fine difference value.

In this fine difference calculation circuit 72, DMX =
(MXE-MXS) / DY, DMY = (MYE-MY
S) / DY is calculated, and the calculation result is supplied to the adder 76 of the interpolation calculation circuit 75.

In the interpolation calculation circuit 75, the adder 76 performs addition between the outputs from the fine difference calculation circuits 72 and 82 and the previous data set in the registers 77 and 87,
MX = MX + DMX, MY = MY + DMY, TP = TP
Calculation of + DTP is performed (steps S11 and 12).

This value is given to the register 77, and the value of this register 77 is written in the frame memory 8 as the address data of the mapping pattern.

Since the outputs from the registers 77 and 87 are given to one input of the adder 76, this circuit 7
At 5, interpolation calculation is performed.

The frame memory 8 stores the left side X address of the polygon side, the right side X address, the left side X address of the mapping pattern, the right side X address, the left side Y address of the mapping pattern, the right side Y address, and the Z value for each Y address. Is performed (step S13).

Then, in step S14, it is judged whether or not the DY times operation of the scan line has been repeated. If not repeated DY times, the process returns to step S9 to repeat the above-mentioned operations. After repeating DY times, the process proceeds to step S15, where the end point data is moved to the start point data and the number of end points is incremented by 1 (step S15).
16) and proceeds to step S17.

In step S17, it is judged whether or not all the sides of the polygon are finished. If not,
Returning to step S4, the above-mentioned operation is repeated.

When all the sides of the polygon are completed, the process proceeds to step S8, and in step S8, the screen memory 4
After incrementing the address in step S9, the polygon count is incremented in step S9, and step S1
Go to 0.

In step S10, it is determined whether or not all polygon processing has been completed. If all polygon processing has not been completed, the process returns to step S2 and the above-described operation is repeated. Then, when it is determined that the processing of all the polygons is completed, the contour processing operation is completed.

Next, a specific embodiment of the internal drawing processing device 9 used in the present invention will be further described with reference to FIG. On the basis of the polygon outline and mapping pattern information calculated by the outline processing unit 8 described above, the internal drawing processing unit 9 obtains the mapping pattern information data of the polygon from the start point to the end point for each Y address.

Each time the start point and end point addresses (XS, XE) of the polygon figure are read from the frame memory 8, the third counter 503 is incremented, and the unit section 504,
The parameters read from the frame memory 8 are set in the parameter calculation unit 530, respectively.

Each unit number of the unit section 504 corresponds to the order of the Z value of the polygon, and each unit has the start and end addresses (XS, XS) of the polygon figure of the polygon having the order of the Z value corresponding to the unit number. The horizontal dot address of the CRT 12 is received from the second counter 502, and the start point (XS) and end point (X) of the polygon address are received.
E) transfers to the priority encoder 650 whether or not it is included in the address.

Each unit of the unit section 504 is constructed as shown in FIG. 4, for example. From the second counter 502, the horizontal dot address of the CRT 12 is compared with the comparators 504d, 5
04e, 504g, 504f. In addition, the start point (XS) of the address from the frame memory 8,
The end point (XE) is given to the registers 504b and 504c, respectively. Then, the start point and end point (XS, XE) values are given as the other inputs of the comparators 504d, 504e, 504g, 504f, and the comparators 504d, 504 are supplied.
At e, the horizontal dot address and start point (X
S) is compared with the end point (XE) address, and the comparison result is output to the AND circuit 504h. That is, it is compared whether or not the start point (XS) is smaller than the horizontal dot address and the end point (XE) is larger than the horizontal dot address, and the end point is output to the AND circuit 504h. Then, the AND circuit 504h determines the result of whether or not the polygon is a displayed polygon by the priority encoder 6
Inform 50

On the other hand, the comparators 504d and 504e compare the horizontal dot address with the start point (XS) and end point (XE) address and output the result to the OR circuit 504i as to whether the two addresses match. . And OR circuit 5
The output (OUT2) from 04i informs the priority encoder 650 whether the horizontal dot address is equal to the start point (XS) or the end point (XE).

Further, the Z value number and the unit number are given to the comparator 504a, and the comparison result of the two is calculated by the AND circuit 50.
Output to 4h.

In this way, each unit is given the start and end addresses (XS, XS) of the polygon figure of the polygon having the order of the Z value corresponding to the unit number, and the horizontal dot of the CRT 12 from the second counter 502 is given. Receives an address and starts (XS) and ends (XE) the address
Is included in the address, that is,
Whether or not the polygon is displayed is transferred from the AND circuit 504f to the priority encoder 650. Further, the OR circuit 504i transfers information indicating whether the edge is a polygon edge to the priority encoder 650.

The priority encoder 650 transfers the address of the unit having the highest priority among the signals transferred from each unit to the parameter memory 600. Further, the priority encoder 650 transfers information indicating whether the edge is a polygon edge to the anti-aliasing processing device 11. This priority encoder 650 is configured as shown in FIG.

This priority encoder 650 is
Inverter group 651, AND circuit groups 652, 653, 6
54, an OR circuit 655, and an encoder 656. An output obtained by inverting the output (OUT1) from the AND circuit 504h from the unit 504 by the inverter group 651 is given to one input of the AND circuit group 652, and the other input has the preceding AND circuit group 652. The output of is given. The output of each stage of the AND circuit group 652 is connected to one input of the AND circuit group 653, and the relief circuit group 652 is connected to the other input.
Inverted output of each is given. The output (OUT2) from the OR circuit 504i of the unit 504 is supplied to one input of the AND circuit group 654, and one input of the AND circuit group 653 is supplied to the other input.

Further, the output from the AND circuit group 653 is given to the encoder 656. And AND circuit group 6
The output from 54 is provided to the OR circuit 655. From the encoder 656, the address of the unit having the highest priority among the signals transferred from each unit is transferred to the parameter memory 600. Also, the OR circuit 655
Sends information indicating whether or not the unit is an edge of a polygon to the anti-aliasing processing device 11.

The parameter calculation unit 530 receives from the frame memory 8 the start and end addresses (XS, X) of the polygon graphic.
E), receiving the start point and end point addresses (MXS, MXE) (MYS, MYS) of the mapping pattern memory 10,
The address interpolation processing unit 800 recreates the necessary parameters and transfers them to the parameter memory 600.

The parameter calculator 530 is constructed as shown in FIG. 5, for example. In this parameter calculation unit 530, digital differential analysis (D
DA) calculates a fine difference value for calculating the internal address of the mapping pattern. That is, the fine difference value is calculated according to (9), (10), and (11) of the equation 3.

[0074]

## EQU00003 ## DXY = XE (Y) -XS (Y) ... (9) DDMX = (MXE (Y) -MXS (Y)) / DXY ... (10) DDMY = (MY (Y)- MYS (Y))) / DXY (11)

The parameter calculation section 530 reads from the frame memory 8 the X address between two opposite sides and the address of the mapping pattern (XS, XE, MXS, MXE) for each Y address. That is, in this embodiment, Y as the vertical position is synchronized with the horizontal scanning signal.
Two X start points (XS) and X end points (XE) indicating the outline of the polygon corresponding to the address, and a mapping address (MXS, MYS) (MX
(E, MYE) is read from the frame memory 8. Then, XS is written in the register 531, XE is written in the register 532, MXS is written in the register 533, MXE is written in the register 534, MYS is written in the register 535, and MYE is written in the register 536.

Then, the subtracter 537 stores the registers 531 and
The data XS and XE are given from the register 532, and the distance DXY between them is calculated. This DXY is supplied to the dividers 540 and 541.

The subtracter 538 has a register 53.
3, MXS and MXE are given from the register 534, respectively, and the calculation result MYE-MYS from the subtractor 539 is given.
Are supplied to the divider 541.

In the dividers 540 and 541, (MXE
(Y) -MXS (Y)) / DXY, (MYE (Y) -M
The division of YS (Y)) / DXY is performed respectively, and this value (D
DMX), (DDMY) and MXS, MYS and XS are written in the parameter memory 600. The parameter memory 600 is the X calculated by the parameter calculation unit 550.
The values of S, DDMX, DDMY, and MXS, MYS are set to Z.
Store in order of increasing value.

As described above, the first counter 501 is
By receiving the signal of the parameter set, the counter is incremented by 1 to select the unit to set the parameter and generate the address of the parameter memory 600.

The second counter 502 generates the horizontal dot address of the CRT 12 and transfers it to all the unit sections 504 and the address interpolation processing section 800.

The address of the frame memory 8 is the third address.
It is generated by the counter 503 and is accessed based on the counter value.

This address interpolation processing section 800 uses each parameter calculated by the parameter calculation section 530 to
Interpolation calculation is performed from the start point to the end point of the Y-axis according to the following formula 4.

[0083]

## EQU00004 ## MX = MXS (Y) + DDMX * X ... (12) MY = MYS (Y) + DDMY * X ... (13)

Further, the values up to X in the equations (12) and (13) change from 0 to DXY.

The address interpolation processing unit 800 reads XS, DDMX, DDMY, MX from the parameter memory 600.
The S (Y), MYS (Y) data and the X address value of the current processing point are fetched from the second counter 502. The subtracter 801 subtracts XS from the X address value of the current processing point, and this value is given to the multipliers 802 and 803. This multiplier 80
From one of the parameter memories 600 to DD
MX is given, the multiplier 802 calculates DDMX * (X address value of current processing point−XS), and the calculation result is supplied to the adder 805. Then, MXS (Y) is given to the adder 805 from the parameter memory 600, the start point data is added to the calculation result of the multiplier 802, and the interpolation calculation is performed. The interpolated data is sent to the mapping address synthesizer 90.

Further, DDMY is given from the parameter memory 600 to one input of the multiplier 803, and this multiplier 803 calculates DDMY * (X address value of current processing point-XS, and The calculation result is supplied to the adder 804. Then, MYS (Y) is given to the adder 804 from the parameter memory 600, and the multiplier 80
The start point data is added to the calculation result of No. 3, and interpolation calculation is performed. The interpolated data is sent to the mapping address synthesizer 90.

The address of each segment from the parameter memory 600 is given to the segment address register 89. The segment address stored in the segment address register 89 is given to the mapping address synthesizer 90.

This mapping address synthesizer 90
Interpolated MXS given from the interpolation calculation circuit 800
The (Y), MYS (Y) data and the segment address data are combined, and this combined data is given to the anti-aliasing processing device 11.

As described above, the anti-aliasing processing device 11 is provided with polygon edge information (flag) indicating whether or not it is a polygon edge from the priority encoder 650.

This anti-aliasing processing device 11
If the polygon edge flag given from the priority encoder 650 is set, the anti-aliasing processing is performed by performing nxn filter calculation on the number of rounded dots of this polygon edge, and the data is sent to the CRT1.
Send to 2. If the polygon edge flag is not set, the data is sent to the CRT 12 without performing the anti-aliasing process.

As a result, high speed anti-aliasing is performed only on the polygon edge. Then, at the time of the CRT display, only when the dot corresponds to the polygon edge, n × n, 2 × 3 in the present embodiment, the filter calculation is performed on the number of rounded dots of the dot, and high-speed anti-aliasing becomes possible.

Furthermore, the anti-aliasing processing device 11 of this embodiment is configured so that the parameter for the filter calculation is changed according to the distance from the viewpoint, that is, the Z value, so that a far object can be obtained. On the other hand, the anti-aliasing is strongly performed, and the anti-aliasing is weakly performed on the object in the vicinity so that the display with more reality is performed. Details of the anti-aliasing processing device 11 will be described later.

The X address SX of the screen address to be displayed on the CRT 12 is calculated by XS + X.

Each of these circuits is entirely controlled by a controller 50, which is shown in FIG.
The whole is controlled according to the flowchart of 0 and 11.

Next, the operation of the internal drawing processing apparatus 9 of this embodiment will be further described with reference to FIGS. Figure 1
0 is a flowchart showing the parameter setting operation, FIG.
1 is a flow chart showing the operation of the address interpolation calculation unit.

In this embodiment, the frame memory 8
In, 512 polygons are stored in ascending order of Z value. When the operation of the internal drawing processing device 9 is started, first,
Third counter 5 for generating address of frame memory 8
03 and the first counter 501 for generating addresses of the parameter memory 600 (step S20), and after the first counter 501 is counted up (step S21), the value of the first counter 501 is set to the parameter memory 600. It is determined whether the number of polygons is less than or equal to the number of polygons stored in, or 255 in this embodiment. If the number of polygons is less than or equal to the number of stored polygons, the process proceeds to step S23. It ends (step S22).

Then, in step S23, the X start point address (XS) and the X end point address (XE) are read from the frame memory 8 and the unit section registers 504b,
Store in 504c respectively.

Then, in step S24, the X start point address (XS) and the X end point address (XE) from the frame memory 8, the start point address (MXS, MYS) and the end point address (MXE, MY) of the mapping pattern memory.
E), DDMX, and DDMY are read out and transferred to the parameter calculator 530, and then the process proceeds to step S25.

In step S25, the parameter calculation unit 530 calculates each parameter and stores each calculated parameter in the parameter memory 600 according to the address value indicated by the first counter 501.

Then, the third counter 503 is counted up (step S26), and it is judged whether or not the value of the third counter 503 is the number of polygons stored in the frame memory 8, that is, within 512 in this embodiment. ,
If it is within 512, the process returns to step S21 and the above-described operation is repeated. When the third counter 503 exceeds 512, the parameter setting operation ends.

Then, address interpolation calculation is performed. As shown in the flowchart of FIG. 11, first, the counter value of the second counter 502 is initialized (step S3).
0), the second counter 502 is counted up (step S31), and the value of the second counter 502 is transferred to each unit of the unit section 504 (step S32).

In each unit of the unit section 504,
The X start point address (XS) and the X end point address (XE) stored in the registers 504b and 504c, the Z value, and the output based on the second counter 502 are output to the priority encoder 650 (step S33).

Then, the priority encoder 650
Transfers the highest priority address to the parameter memory 600 and transfers the polygon edge flag to the anti-aliasing processor 11 (step S).
34). The parameter memory 600 outputs the data of the address indicated by the priority encoder 650 to the address interpolation calculation processing section 800 (step 35).

In step S36, the address interpolation calculation processing section 800 causes the parameter memory 600 to read XS,
DDMX, DDMY and MXS, MYS data, and the X address value of the current processing point are fetched from the second counter 502. Then, DDMX * (X address value of current processing point (second counter value) −XS) + MXS operation, DDMY
* (X address value of current processing point-XS) + MYS is calculated, and the interpolated data is given to the mapping address synthesizer 90. Further, the mapping pattern memory addresses interpolated with the values in the mapping pattern memories 10 on the left and right sides are also given to the mapping address composition device 90. Then, the mapping address synthesizing device 90 sends the address synthesized with the segment address to the anti-aliasing processing device 11, and proceeds to step S37.

In step S37, the second counter 502
Is equal to the horizontal dot address of the CRT 12 or 320 in this embodiment, and if 320 is not reached, the process returns to step S31 to repeat the above operation. And when it reaches 320,
This operation ends.

Next, a specific embodiment of the anti-aliasing processing apparatus of the present invention will be described with reference to FIGS. 7 and 12.

This anti-aliasing processing device 11
Determines whether to output the data subjected to the anti-aliasing processing to the CRT 12 according to the polygon edge flag from the priority encoder 650. That is, if the polygon edge flag is set, the data obtained by performing the n × n filter calculation on the number of turns of the polygon edge is output to the CRT 12, and if the polygon edge flag is not set, the filter calculation is performed. The data that has not been output is output to the CRT 12.

The mapping pattern memory address (MX, MY) transferred from the mapping address synthesizing unit 90 of the internal drawing processor 9 is temporarily stored in the register 112, and the mapping pattern memory address (MX, MY) is It is provided to the mapping pattern memory 10.

Mapping memory data is read from the mapping pattern memory 10 according to the address, and the data is given to the multiplexer 113. In addition, the register 111 indicates whether or not the polygon is a mapping polygon and a polygon attribute flag of the multiplexer 113.
And controls the multiplexer 113. When the polygon attribute flag indicates a mapping polygon, the multiplexer 113 uses the mapping pattern memory 10
To the look-up table (LUT) memory 114, and when it is other than the mapping polygon, it is stored in the register 112 and the mapping pattern memory address is given to the LUT memory 114.

Data such as R, G, and B is stored in the LUT memory 114, and color information corresponding to the mapping memory data or the mapping pattern memory address is read out and given to the register 115 and the multiplier 122. .

The Z value of the polygon is temporarily stored in the register 116, and the Z value is given to the filter coefficient generator 119 from this register 116. The filter coefficient generator 119 changes the filter calculation parameter according to the given Z value and gives the filter coefficient to each of the multipliers 122 to 127. This filter coefficient is changed to strongly anti-aliase a distant object and weakly anti-aliase a near object.

The color information from the LUT memory 114 stored in the register 115 is transferred to the register 121, the scan line memory 120 and the multiplier 123. The scan line memory 120 stores the output from the register 115 for one line, and the color information from the scan line memory 120 is given to the multipliers 125, 126, 127.

Then, the multipliers 122 to 127 receive the filter coefficient from the filter coefficient generator 119,
The color information of each dot is multiplied by a coefficient, and the adder 1
By adding all the multiplication results by 28, the filter operation is performed and the operation result is given to the multiplexer 129.

Register 1 is provided in the multiplexer 129.
The color information stored in 15, that is, the color information that has not been subjected to the filter calculation processing is given. This multiplexer 1
The output 29 is controlled by a polygon edge flag. That is, the polygon edge flag from the priority encoder 650 is the flip-flops 117 and 118.
Are temporarily stored in the memory and are given to the multiplexer 129.
Then, if the polygon edge flag is set, the value subjected to the anti-aliasing processing from the adder 128 is output from the multiplexer 129. When the polygon edge flag is not set, the output from the register 115, that is, the color information for which anti-aliasing processing is not performed is output.

The filter used in the anti-aliasing processor 11 is arranged as shown in FIG. 14, and X, Y = n, m, that is, in order to obtain the dot color of the portion k5 in FIG. The calculation shown in Equation 5 is performed.

[0116]

## EQU00005 ## k1 * (n-1, m-1) + k2 * (n, m-1) + k3 * (n + 1, m + 1) + k4 * (n-1, m) + k5 * (n, m) + k6 * ( n + 1, m)

The result of the above calculation is output to the CRT 12.

What is the detection point of the polygon edge? In the example shown in FIG. 15, the polygon edge flag is set at 6 points of 5, 8, 12, 14, 18, and 21, and the flag is given to the flip-flop 117. Then, the antialiasing processing is performed at these 6 points, and the value is output from the multiplexer 129 to the CRT.
Output to 12.

Next, the operation of the anti-aliasing processing device 11 of the present invention will be described with reference to the flowchart of FIG.

When the operation of the anti-aliasing processor 11 is started, it is judged whether or not it is a mapping polygon by its polygon attribute flag. If it is a mapping polygon, the process proceeds to step S42, and if it is not a mapping polygon, the process proceeds to step S41 (step S40). ).
In step S42, the mapping memory data from the mapping pattern memory 10 is given to the LUT memory 114, the R, G, B color matching information is read from the LUT memory 114, and the process proceeds to step S43.

In step S41, the mapping pattern memory address is given to the LUT memory 114, the R, G, B color matching information is read from the LUT memory 114, and the process proceeds to step S43.

In step S43, whether or not the polygon edge flag is 0, that is, the priority encoder 650 is used.
It is determined whether or not the polygon edge flag from is set, and if the polygon edge flag is set, step S4
If not standing, the process proceeds to step S46 to output color information for which anti-aliasing processing has not been performed.

In step S44, the filter coefficient is changed according to the Z value of the polygon so that the far object is strongly anti-aliased and the near object is weakly anti-aliased.
Proceed to.

Then, in step S45, the color information of each dot is multiplied by each filter coefficient, and all the multiplication results are added to carry out the filter operation, and the process proceeds to step S46.

In step S46, in the case of a polygon edge, the anti-aliasing processed value is set to CRT12.
To the CRT 12 if not a polygon edge.

[0126]

As described above, according to the present invention, only the image information (dots) corresponding to the polygon edge is subjected to the filter operation and the other parts are not subjected to the filter operation, so that the occurrence of jaggies and moire is eliminated. The anti-aliasing process can be performed at high speed, and polygons can be displayed on a display device such as a CRT in real time.

Furthermore, the coefficient of the filter calculation is changed according to the distance from the viewpoint of the polygon so that the anti-aliasing is strongly performed on the distant polygon and the anti-aliasing is weakly performed on the near polygon. By doing so, a more realistic display can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a stereoscopic image display device of the present invention.

FIG. 2 is a block diagram showing a configuration of an outer shape processing device used in the present invention.

FIG. 3 is a block diagram showing a configuration of an internal drawing processing device used in the present invention.

FIG. 4 is a block diagram showing a configuration example of a unit portion of the internal drawing processing apparatus used in the present invention.

FIG. 5 is a block diagram showing a configuration example of a parameter calculation unit of the internal drawing processing apparatus used in the present invention.

FIG. 6 is a block diagram showing a configuration example of a priority encoder of the internal drawing processing device used in the present invention.

FIG. 7 is a block diagram showing a configuration of an anti-aliasing processing device used in the present invention.

FIG. 8 is a flowchart showing the operation of the contour processing apparatus of the present invention.

FIG. 9 is a flowchart showing the operation of the contour processing apparatus of the present invention.

FIG. 10 is a flowchart showing the operation of the internal drawing processing device of the present invention.

FIG. 11 is a flowchart showing the operation of the internal drawing processing device of the present invention.

FIG. 12 is a flowchart showing the operation of the anti-aliasing processing device of the present invention.

FIG. 13 is a diagram showing a relationship of polygon side vector directions.

FIG. 14 is a schematic diagram showing filter coefficients used in the anti-aliasing processing device of the present invention.

FIG. 15 is a schematic diagram showing a relationship between a plurality of polygons and polygon edges.

[Explanation of symbols]

 1 polygon end point memory 3 geometric conversion device 4 screen memory 7 outline processing device 8 frame memory 9 internal drawing processing device 10 mapping pattern memory 11 anti-aliasing processing device 12 CRT

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Tatsuya Nakajima 1-3-3 Nakamagome, Ota-ku, Tokyo Stock company Ricoh Co., Ltd. (72) Inventor Yasuhiro Izawa 1-3-6 Nakamagome, Ota-ku, Tokyo Shares Company Ricoh

Claims (3)

[Claims] 1. Storage means for storing information on X and Y endpoints forming a polygon and the distance of each polygon from the viewpoint.
Geometric conversion means for geometrically converting the end point information from the storage means, and outer shape processing means for converting the address information of the polygon outer shape into information of the polygon outer shape portion for each scan line based on the end point information from the geometric conversion means. , Means for detecting the position of the polygon edge based on the address information between the two opposite sides calculated by the outer shape processing means and the distance from the viewpoint of each polygon, and only the image information of the polygon edge is filtered. A stereoscopic image processing apparatus comprising anti-aliasing processing means and display means for displaying image information from the anti-aliasing processing means. 2. Storage means for storing X and Y end point information forming a polygon, distances from the viewpoint of each polygon, and internal pattern end point information indicating a basic pattern area of a pattern to be given to a polygon surface, and this storage. Geometric conversion means for geometrically converting each end point information from the means, and based on each end point information from this geometric conversion means, polygon outline address information and internal pattern end point information are converted into polygon outline part information for each scan line. The contour processing means, the means for detecting the position of the polygon edge based on the address information between the two opposing sides calculated by the contour processing means and the distance from the viewpoint of each polygon, and the contour processing means. Internal drawing processing means for calculating internal pattern information inside the polygon on the basis of the address information between the two opposite sides calculated as above; The internal pattern memory forming the lookup table of the basic pattern and the internal pattern memory are accessed based on the information given from the internal drawing processing means, and only the image information of the polygon edge among the image information obtained from this memory is filtered. A stereoscopic image processing apparatus comprising: anti-aliasing processing means for performing the above; and display means for displaying image information from the anti-aliasing processing means. 3. The anti-aliasing processing means comprises:
It is equipped with a means to change the coefficient of the filter calculation according to the distance from the viewpoint of the polygon, and strongly anti-aliasing the distant polygons and weakly anti-aliasing the near polygons. The stereoscopic image processing device according to claim 1 or 2.