JPH07212667A - Display controller - Google Patents

Abstract

PURPOSE:To attain display more abundant in the expression than that of a conventional controller with simple configuration by using dot character data with respect to the display controller displaying characters on a TV screen or the like. CONSTITUTION:A graphic data generating circuit 24 handles dot character data D0-D8 not subject to coloring processing outputted from a font ROM 3 as color ata in the unit of 3-bits and generates graphic data DR,DG,DB displayed in which dots corresponding to three-bits processed as one unit are displayed for a same color, and a selection circuit 26 is used to select colored dot character data RGB outputted from a coloring circuit 4 or the graphic data DR, DG, DB outputted from the graphic data generating circuit 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a TV (television).
The present invention relates to a display control device for displaying characters (including figures; the same applies hereinafter) on a screen or the like.

[0002]

2. Description of the Related Art Conventionally, as a display control device, a device whose main part is shown in FIG. 11 is known.

In the figure, 1 is a display memory (VRAM: vi) for storing a character code, a character color, a character background color, and a character attribute.
Deo random access memory) 2 is a memory sequencer for controlling the operation of the display memory 1.

Further, 3 is a character pattern data composed of dots, that is, a font ROM (font read only memory) for storing so-called dot character data, and 4 is a dot character data which is output from the font ROM 3 and is not subjected to coloring processing. Is a coloring circuit that performs coloring processing on the basis of color data.

Here, the memory sequencer 2 is shown in FIG.
As shown in, the horizontal synchronization signal HS and the dot clock signal ACL which is the basic clock signal of the memory timing system.
The digit addresses VC0 to VC4 are generated based on K, and the row addresses VR0 to VR3 are generated based on the vertical synchronizing signal VS and the horizontal synchronizing signal HS, as shown in FIG. 13, and these digit addresses VC0 to VC4 and row are generated. Address V
It is configured to supply R0 to VR3 to the display memory 1.

As shown in FIG. 14, the display memory 1 has a horizontal 32 digit (1F) × vertical 16 row (F) configuration and is stored at an address designated by the memory sequencer 2. The character codes C0 to C3 and the color data RGB are output.

The font ROM 3 stores dot character data in which one character has horizontal 9 dots × vertical 8 dots, and the character codes C0 to C supplied from the display memory 1 are stored.
The dot character data corresponding to No. 3 are sequentially output in parallel from the first line and are supplied to the coloring circuit 4.

The coloring circuit 4 is constructed as shown in FIG. In the figure, 5 is a parallel / serial conversion circuit (P / S circuit) that converts 9-bit dot character data D0-D8 in units of lines supplied in parallel from the font ROM 3 into serial data, and 6-8 are changeover switch circuits. And 9 to 14 are AND circuits and 15 to 17 are OR circuits.

The changeover switch circuits 6 to 8 are controlled by the output of the parallel / serial conversion circuit 5 to switch between the character color data RGB and the background color data RGB for output.

That is, for example, when the output of the parallel / serial conversion circuit 5 is “1”, the character color data RGB is output as image data, and the parallel / serial conversion circuit 5 is output.
Output = “0”, the background color data RGB is output as image data.

Therefore, for example, when the dot ROM 3 outputs dot character data D0 to D8 as shown in FIG. 16A, the coloring circuit 4 displays a character as shown in FIG. Image data that can be displayed is output.

In FIG. 16B, 18 is a dot on the display surface, a dot with a dot pattern means that it is colored based on the character color data RGB, and a dot without a dot pattern is This means that coloring is performed based on the background color data RGB.

[0013]

As described above, when this display control device is used, the character unit (horizontal 9 dots ×
Characters and backgrounds can be colored in units of vertical 8 dots), but today it is desired to be able to perform richer display.

In view of the above point, the present invention provides a display control device which uses dot character data and has a simple structure and is capable of performing a more expressive display than ever. To aim.

[0015]

The display control device according to the present invention has a coloring circuit 20 as shown in FIG.
, Graphic data creation circuit 21, and selection circuit 22
And is configured.

In the present invention, the coloring circuit 20 is supplied with dot character data and color data which have not been colored, and the graphic data generating circuit 21 is supplied with only dot character data which has not been colored. Supplied.

Here, the coloring circuit 20 is for coloring the dot character data that has not been subjected to coloring processing based on the color data.

Further, the graphic data creating circuit 21
Is for processing uncolored dot character data as color data in units of a plurality of bits, and for dots corresponding to a plurality of bits handled as a unit, creates graphic data for displaying in the same color.

Further, the selection circuit 22 is for selecting and outputting the dot character data which has been subjected to the coloring processing and which is output from the coloring circuit 20 or the graphic data which is output from the graphic data creating circuit 21. The color-processed dot character data or graphic data output from the selection circuit 22 is supplied to a display device (not shown).

[0020]

According to the present invention, the coloring circuit 20 is provided for coloring the dot character data which is not colored, and the graphic data creating circuit 21 is provided for creating the graphic data from the dot character data which is not colored. Through the selection circuit 22, the dot character data or the graphic data which has been colored is output.

Therefore, without providing a graphic data storage circuit for storing graphic data, it is possible to perform display with richer expression than before by using dot character data with a simple structure.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described with reference to FIGS.
A display control device used for a display device having dots × vertical 8 dots will be described as an example.

FIG. 2 is a block diagram showing the main part of one embodiment of the present invention. The display control device of one embodiment of the present invention is the same as the conventional display control device shown in FIG. The graphic data creation control clock signal generation circuit 25 and the selection circuit 26 are added.

Here, the graphic data creation circuit 24
Is the graphic data DR, D for displaying the dot character data which is not colored processed output from the font ROM 3 as color data in units of 3 bits, and the dots corresponding to 3 bits handled as one unit are displayed in the same color.
G and DB are created.

The graphic data creation control clock signal generation circuit 25 controls the graphic data creation circuit 24 based on the dot clock signal ACLK which is the basic clock signal of the memory timing system. DS3
Is generated.

The selecting circuit 26 selects and outputs the colored dot character data RGB output from the coloring circuit 4 or the graphic data DR, DG, DB output from the graphic data creating circuit 24. It is a thing.

Here, the graphic data creation control clock signal generation circuit 25 is constructed as shown in FIG. In the figure, 27 to 35 are D flip-flops, 36,
37 is an inverter, 38 and 39 are Ex-OR circuits (exclusive OR circuit), and 40 is Ex-NOR circuit (non-exclusive OR circuit).

Here, D flip-flops 27 to 35 are provided.
Are connected in cascade, the positive phase output terminal Q of the D flip-flop 35 is connected to the data input terminal D of the D flip-flop 27 via the inverter 37, and the dot clock signal ACLK is inverted by the inverter 36. The inverted dot clock signal / ACLK is supplied to the clock signal input terminal CK.

As a result, with respect to the dot clock signal ACLK shown in FIG. 4A, the output of the D flip-flop 27 becomes as shown in FIG. 4B, the output of the D flip-flop 30 becomes as shown in FIG. 4C, and the D flip-flop becomes. 33
Output is as shown in FIG. 4D.

That is, the D flip-flops 27, 30, 3
The output of 3 is obtained by dividing the dot clock signal ACLK by 1/8, and the output of the D flip-flop 30 is delayed by 3 dot clocks from the output of the D flip-flop 27.
Is delayed from the output of the D flip-flop 30 by 3 dot clocks.

The Ex-OR circuit 38 inputs the positive phase outputs of the D flip-flops 27 and 30, the Ex-OR circuit 39 inputs the positive phase outputs of the D flip-flops 30 and 33, and the Ex-NOR circuit 40. Is a D flip-flop 27,
The positive phase output of 33 is input.

As a result, the graphic data creation control clock signal DS1 output from the Ex-OR circuit 38 becomes as shown in FIG. 4E, and the graphic data creation control clock signal DS2 output from the Ex-OR circuit 39.
Is as shown in FIG. 4F, and the graphic data creation control clock signal D output from the Ex-NOR circuit 40.
S3 becomes as shown in FIG. 4G.

That is, the graphic data creation control clock signals DS1, DS2, DS3 have an H level width of 3 dot clocks and a cycle of 9 dot clocks, and the graphic data creation control clock signal DS2 is the graphic data. Creation control clock signal DS
This is delayed by 3 dot clocks from 1, and the graphic data creation control clock signal DS3 is delayed by 3 dot clocks from the graphic data creation control clock signal DS2.

The graphic data creating circuit 24 is constructed as shown in FIG. In the figure, 41 to 43 are changeover switch circuits, 44 to 52 are AND circuits, 5
3 to 55 are OR circuits.

If the graphic data creation control clock signal DS1 = "1", the graphic data creation control clock signal DS2 = "0", and the graphic data creation control clock signal DS3 = "0", the dot character data D0, D1 , D2 are selected, and these dot character data D0, D1, D2 are graphic data DR, D
It is output as G and DB. In addition, DR is red data,
DG is green data and DB is blue data.

When the graphic data creation control clock signal DS1 = "0", the graphic data creation control clock signal DS2 = "1", and the graphic data creation control clock signal DS3 = "0", the dot character data D3, D4, D5 is selected, and these dot character data D3, D4, D5 are the graphic data DR, DG,
It is output as DB.

When the graphic data creation control clock signal DS1 = "0", the graphic data creation control clock signal DS2 = "0", and the graphic data creation control clock signal DS3 = "1", the dot character data D6, D7, D8 is selected, and these dot character data D6, D7, D8 are the graphic data DR, DG,
It is output as DB.

Here, in the present embodiment, the relationship between the dot character data D0 to D2, D3 to D5, D6 to D8, the graphic data DR, DG, DB, and the display color is as follows.
As shown in Table 1.

[0039]

[Table 1]

Therefore, for example, when the dot ROM D3 outputs the dot character data D0 to D8 as shown in FIG. 6A, the coloring circuit 4 displays the area for one character on the display surface as shown in FIG. 16B. The dot character data capable of displaying the character as shown is output.

On the other hand, in the graphic data creation circuit 24, the dot character data D0 to D8 shown in FIG.
6B are grouped in units of 3 bits as shown in FIG. 6B, and the graphic data creation circuit 24 displays graphic data DR, DG, which can display a graphic as shown in FIG. DB is output.

As described above, in this embodiment, the font RO
The coloring circuit 4 for coloring the uncolored dot character data D0 to D8 output from M3, and the graphic data DR, DG having the same three dots from the uncolored dot character data D0 to D8, A graphic data creation circuit 24 for creating a DB and a selection circuit 26 for selecting the dot character data RGB or the graphic data DR, DG, and DB that have been subjected to coloring processing are provided, and the dot character data RGB that has been subjected to coloring processing or The graphic data DR, DG, and DB are selected and output.

Therefore, according to this embodiment, the dot character data output from the font ROM 3 is used without providing the graphic data storage circuit for storing the graphic data, and the expression power is higher than that of the conventional art. The rich display of can be performed.

The display memory 1, the memory sequencer 2 and the coloring circuit 4 are realized by using a conventional on-screen display controller (OSDC) as shown in FIG. can do.

In this case, the graphic data creating circuit 2
4. The graphic data creation control clock signal generation circuit 25 and the selection circuit 26 can be configured by a circuit as shown in FIG.

In FIG. 7, 57 is an on-screen display.
The display controller main body 58 receives commands and data input by 8-bit serial transfer,
This is a serial interface unit that decodes commands by a command decoder and distributes data. / CS is a chip select terminal, SCLK is a shift clock input terminal, SIN is a serial data input terminal, and /
RESET is a reset terminal.

Reference numeral 59 is a dot clock generator for generating a dot clock signal which is a basic clock signal of the memory timing system, and EXD and XD are external circuit terminals of the display dot clock generator.

Reference numeral 60 denotes a color burst clock generating unit for generating a color burst clock signal (4FSC clock signal) which is a basic clock signal of the synchronizing signal system, and EXS and XS are external to the color burst clock generator. It is a circuit terminal.

Reference numeral 61 separates the input composite sync signal into a horizontal sync signal and a vertical sync signal, and
System or NTS for generating timing signal of PAL system
This is a C / PAL timing generator.

Note that / EXHSYN is an external horizontal sync signal input terminal, / EXVSYN is an external vertical sync signal input terminal, / VBLNK is a vertical blanking signal output terminal, /
HSYNC is a horizontal synchronizing signal output terminal, and / VSYNC is a vertical synchronizing signal output terminal.

Further, reference numeral 62 is a memory sequencer section for generating a timing signal for display operation and controlling the operation of each block. The memory sequencer 2 shown in FIG. 1 is included in this memory sequencer section 62.

Reference numeral 63 is a display memory for storing a character code, a character color, a character background color, and a character attribute.
The display memory 1 shown in (1) corresponds to this.

64 is an external font ROM
Address buffer that performs address output, read output, and address bus tristate control to / REA
D is a font ROM read control terminal, ADR0-18
Is a font ROM address output terminal, and / TSC is an address bus tristate control terminal.

Reference numeral 65 is a parallel / color processing for coloring the dot character data output from the font ROM.
The coloring circuit 4 shown in FIG. 1, which is a serial conversion / character modification unit, is included in the parallel / serial conversion / character modification unit 65.

DA0 to DA7 are data input terminals from the font ROM, RGBOUT is a colored dot character data output terminal, and VOBOUT is a character / character background period signal output terminal.

Reference numeral 66 denotes an analog video signal generator for synthesizing video signals by external input or internally generated, VIN is a composite video signal input terminal, YIN is a luminance signal input terminal, CIN is a saturation signal input terminal, VOUT is a composite video signal output terminal, YOUT is a luminance signal output terminal, and CO
UT is a saturation signal output terminal.

Further, / TEST is a test signal input terminal, V
CC is a power supply terminal, VSS is a ground terminal, AVCC is an analog power supply terminal, and AVSS is an analog ground terminal.

In FIG. 8, 67 to 74 are D flip-flop circuits, 75 and 76 are selectors, and 77 to 81.
Is an inverter, 82 and 83 are NAND circuits, and 84 is NO
It is an R circuit.

9 and 10 are waveform charts showing the operation of the circuit shown in FIG. 8. In the circuit shown in FIG. 8, the dot clock EXD shown in FIGS. 9A and 10A is
Via the inverters 77 and 78, the D flip-flop 6
It is supplied to the clock input terminals CK of 8 to 70 and 74.

Address A for the font ROM
Of the DR0 to ADR18, the address ADR17 is the D flip-flop 6 in synchronization with the read control signal READ.
7 and the output thereof is latched by the D flip-flop 73, and its output ADR17SL is supplied to the select control terminal SEL of the selector 75.

Address A for the font ROM
Of the DR0 to ADR18, the address ADR18 is the D flip-flop 6 in synchronization with the read control signal READ.
7 and the output thereof is latched by the D flip-flop 73, and its output ADR18SL is supplied to the select control terminal SEL of the selector 76.

The power supply voltage VCC is latched by the D flip-flop 67 in synchronization with the read control signal READ, and its output is supplied to the D flip-flop 68 and D
In the circuit including the flip-flop 68 and the NAND circuits 82 and 83, clock signals BCK, RCK, and GCK as shown in FIG. 9F (FIG. 10F), FIG. 9G (FIG. 10G), and FIG. 9H (FIG. 10H) are generated. .

Here, the clock signal BCK is supplied to the clock signal input terminal of the D flip-flop 71, the clock signal RCK is supplied to the clock signal input terminal of the D flip-flop 72, and the clock signal GCK is supplied to the clock of the D flip-flop 73. It is supplied to the signal input terminal.

In FIG. 8, VOB is a font R.
It is dot character data obtained by serializing dot character data output from the OM, and in FIGS. 9E and 10E, B1 to B8 are bits treated as blue data, R
1 to R8 are bits treated as red data, G1 to G
Reference numeral 8 indicates a bit treated as green data.

Here, of the dot character data VOB,
The bit treated as blue data is the clock signal BCK
Is latched by the D flip-flop 71 in synchronism with the clock signal GCK, and its output is latched by the D flip-flop 73 in synchronism with the clock signal GCK. The output BOT1 is supplied to the selector 76 as blue data of graphic data. 9I and 10I show this blue color data BOT1.

In the dot character data VOB, the bit treated as red data is latched by the D flip-flop 72 in synchronization with the clock signal RCK, and further,
The output is latched by the D flip-flop 73 in synchronization with the clock signal GCK, and the output ROT1 is supplied to the selector 76 as the red data of the graphic data. 9J and 10J show the red data RO
It shows T1.

In the dot character data VOB, the bit treated as green data is latched by the D flip-flop 73 in synchronization with the clock signal GCK, and its output GOT1 is supplied to the selector 76 as red data of graphic data. It 9K and 10K show green color data GOT1.

The blue data B of the graphic data
OT1, red data ROT1 and green data GOT1 are
It is supplied to the NOR circuit 84, and the output of the NOR circuit 84 is supplied to the selector 75 via the inverter 81.

The selector 75 is supplied with not only the output of the inverter 81 but also the horizontal blanking period signal / HBLNK as the selected signal. ADR17SL =
When it is "1", the horizontal blanking period signal / HBLNK
Is selected and blue data BOT1 = "0", red data ROT1 = "0", and green data GOT1 = "0", that is, graphic data BOT1, ROT1, G
When OT1 means to display black, black is displayed as it is.

On the other hand, when ADR17SL = "0", the output of the inverter 81 is selected and the blue data B
Even if OT1 = “0”, red data ROT1 = “0”, and green data GOT1 = “0”, that is, if the graphic data BOT1, ROT1, and GOT1 mean displaying black, the graphic data BO
T1, ROT1, and GOT1 are treated as displaying transparency.

Further, among the dot character data RGBOUT which has been subjected to the coloring process and is output from the on-screen display controller shown in FIG. 7, blue data BOUT and red data ROUT are supplied to the D flip-flop 69.

Further, of the dot character data RGBOUT, green data GOUT and the same on-screen data
The character / character background period signal VOBOUT output from the display controller is supplied to the D flip-flop 70.

Here, the blue data BOUT and the red data ROUT are delayed by 3 dot clocks in the D flip-flop 69 and supplied to the selector 76 as the blue data BOT76 and the red data ROT76.

The green data GOUT and the character / character background period signal VOBOUT are supplied to the D flip-flop 70.
In, at a delay of 3 dot clocks, the green data GOT 76 and the character / character background period signal VOB 76 are supplied to the selector 76.

These blue data BOUT and red data R
The delay process for OUT, the green data GOUT, and the character / character background period signal VOBOUT is to align the timing with the graphic data BOT1, ROT1, GOT1 and the signal VOB1 output from the selector 75.

Here, in the selector 74, the ADR
When 18SL = "1", the signal VOB1 and the graphic data BOT1 and ROT output from the selector 75 are output.
1, GOT1 is selected and these are the final output BITVO
It is output as B, BITB, BITR, BITG.

On the other hand, when ADR18SL = "0", the character / character background period signal VOB76 and the dot character data BOT76, ROT76, GOT76 are output as the final outputs BITVOB, BITB, BITR, BITG.

As described above, even when the on-screen display controller shown in FIG. 7 and the circuit shown in FIG. 8 are used, the dot character data output from the font ROM is used and a simple structure is obtained. It is possible to perform display with richer expression than before.

The circuit shown in FIG. 8 can be incorporated in the on-screen display controller. In such a case, the dot characters output from the font ROM can be produced without increasing the number of parts. The data can be used to provide a more expressive display than before.

[0080]

As described above, in the present invention, the coloring circuit (20) for coloring the dot character data that has not been colored and the plural dots from the dot character data that has not been colored have the same color. A graphic data creation circuit (21) for creating graphic data and a selection circuit (22) for selecting colored dot character data or graphic data are provided, and colored dot character data or graphic data is provided. Since it is configured to select and output, the dot character data can be used without providing a graphic data storage circuit, and a display with richer expressive power than conventional can be performed with a simple configuration.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a main part of an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a graphic data creation control clock signal generation circuit provided in an embodiment of the present invention.

FIG. 4 is a waveform diagram showing an operation of a graphic data creation control clock signal generation circuit provided in an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a graphic data creation circuit provided in an embodiment of the present invention.

FIG. 6 is a diagram for explaining the operation of the graphic data creation circuit provided in the embodiment of the present invention.

FIG. 7 is a display memory provided in one embodiment of the present invention,
FIG. 3 is a block diagram showing an on-screen display controller including a memory sequencer and a coloring circuit.

FIG. 8 is a circuit diagram showing another configuration example of a graphic data creation circuit and a graphic data creation control clock signal generation circuit and a configuration example of a selection circuit provided in an embodiment of the present invention.

9 is a waveform chart showing the operation of the circuit shown in FIG.

10 is a waveform chart showing the operation of the circuit shown in FIG.

FIG. 11 is a block diagram showing a main part of an example of a conventional display control device.

12 is a waveform chart showing an operation of a memory sequencer provided in the display control device shown in FIG.

13 is a waveform diagram showing an operation of a memory sequencer provided in the display control device shown in FIG.

14 is a diagram showing a configuration of a display memory provided in the display control device shown in FIG.

15 is a diagram showing a configuration of a coloring circuit provided in the display control device shown in FIG.

16 is a diagram for explaining the operation of the coloring circuit shown in FIG.

[Explanation of symbols]

 20 Coloring circuit 21 Graphic data creation circuit 22 Selection circuit

Claims (1)

[Claims] 1. A coloring circuit (20) for coloring non-colored dot character data based on color data, and handling the non-colored dot character data as color data in units of a plurality of bits. A dot corresponding to a plurality of bits treated as a graphic data creation circuit (21) for creating graphic data to be displayed in the same color, and dot character data or the graphic data output from the coloring circuit (20) and subjected to coloring processing. A display control device comprising: a selection circuit (22) for selecting and outputting graphic data output from a creation circuit (21).