JPH07211887A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to perform high-frequency operation by suppressing the increase in internal resistance, and effectively removing carriers. CONSTITUTION:An N<-> type high resistivity layer 3 is formed on a P<+> type substrate 1. An N<+> type cathode layer 5 is formed through a P<-> type channel layer 4 on the upper surface of the N type high resistivity layer 3. A P<+> type gate layer 6 is formed so as to hold the P<-> type channel layer 4. way, an N<+> type buffer layer 2, which is connected to the P type substrate 1, is formed in the N<-> type high resistivity layer 3. A trap region 15 is formed in the N<-> type high resistivity layer 3 by the implantion of hydrogen ions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device (electrostatic induction thyristor), and more particularly to a semiconductor device in which control of a storage carrier is optimized to drive at a low voltage and increase a frequency.

[0002]

2. Description of the Related Art In recent years, as electronic devices and systems have become more multifunctional and more compact, power sources used therein have also been required to be smaller and more efficient. In order to miniaturize the power source, it is possible to miniaturize the transformer, the capacitor, the coil, etc. by increasing the frequency. Therefore, a high-frequency PWM control system using a switching element realizes size reduction, weight reduction, and controllability improvement. However, high frequency PWM
Control methods include switching loss of switching elements, snubber loss, and increase in transient response stress due to increasing frequency.

Therefore, by driving the switching element by the resonance circuit method, the switching loss is small in principle, the snubber circuit is not required, and the transient response stress can be reduced.

FIG. 11 shows switching waveforms when a GTO thyristor is driven as a switching element using this resonance type circuit. When the GTO thyristor is turned on, a soft switching operation is performed in which the anode voltage VA drops and then the anode current IA1 rises in a sine wave. or,
When the GTO thyristor is off, the anode voltage VA rises after the anode current IA1 becomes 0, so the switching loss at the time of off is small. Further, in the case of the hard switching operation, as shown in FIG. 12, after the GTO thyristor is turned off and the anode voltage VA rises and the anode current IA falls, the current accumulated again in the GTO thyristor due to the influence of the carriers accumulated therein. There is a phenomenon that flows. If the current caused by this phenomenon is large, the tail loss of the GTO thyristor becomes large.

Therefore, it is necessary to suppress the tail loss by removing the carriers accumulated in the GTO thyristor.
As a countermeasure against this, the first method disclosed in JP-A-63-88863 is disclosed.
As shown in the figure, P or P
With a trapezoidal base layer, and Japanese Patent Laid-Open No. 62-
As shown in FIG. 3 of Japanese Patent Publication No. 76556, there is proposed an N ⁺ buffer layer implanted.

[0006]

However, due to this trap layer, accumulated carriers when the thyristor is turned off can be trapped in the trap layer and removed. Therefore, the tail loss of the thyristor can be reduced. However, the internal resistance of the thyristor increases due to the formation of the trap layer,
It becomes difficult to perform the turn-on operation at a low voltage.

That is, when the thyristor is turned on at a low voltage, the carriers remaining in the high resistance drift region at the time of turning off cannot be removed smoothly.
In particular, when applied to a switching element of a current resonance type circuit, an electric field is hardly generated inside the thyristor at the time of turn-off, and many carriers exist in the high resistance drift region. Therefore, even if the trap layer is used, carriers are not effectively removed. As a countermeasure for this, it is possible to increase the irradiation amount of protons and the like to effectively remove the carriers, but there is a problem that the resistance inside the thyristor increases and the on-voltage increases.

The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor device which suppresses an increase in internal resistance, effectively removes carriers, and enables high frequency operation. It is in.

[0009]

In order to solve the above problems, the invention according to claim 1 forms a low concentration base layer on the upper surface of an anode layer, and a cathode layer and a gate on the upper surface of the low concentration base layer. In the semiconductor device having the layer formed, the gist is that a trap region for carrier trap is formed in the low concentration base layer.

According to a second aspect of the present invention, in a semiconductor device in which a base layer is formed on an upper surface of a drain layer and a source layer and a gate layer are formed on an upper surface of the base layer, the low concentration base layer is for carrier trapping. The gist of this is that the trap region of No. 1 was formed.

The gist of the invention of claim 3 is that the trap region for carrier trap is formed by ion implantation of hydrogen. The gist of the invention according to claim 4 is that the semiconductor device is used as a switching means of a current resonance type circuit.

[0012]

According to the present invention, when a positive voltage is applied to the gate layer while a positive voltage is applied to the anode layer and a negative voltage is applied to the cathode layer, the semiconductor device is turned on.

If a negative voltage is applied to the gate layer without applying a voltage to the anode layer and the cathode layer, the semiconductor device is turned off. At this time, since no voltage is applied to the anode layer and the cathode layer, carriers remain in the low concentration base layer. This carrier is trapped and removed by the trap region formed in the low concentration base layer.

Therefore, since the carriers are smoothly removed, the current due to the influence of the carriers does not flow, and the tail loss can be reduced. According to the second aspect of the invention, when the positive voltage is applied to the gate layer while the positive voltage is applied to the drain layer and the negative voltage is applied to the source layer, the semiconductor device is turned on.

When a negative voltage is applied to the gate layer without applying a voltage to the drain layer and the source layer, the semiconductor device is turned off. At this time, since no voltage is applied to the drain layer and the source layer, carriers remain in the low concentration base layer. This carrier is trapped and removed by the trap region formed in the low concentration base layer.

Therefore, since the carriers are smoothly removed, no current flows due to the influence of the carriers, and the tail loss can be reduced. According to the third aspect of the present invention, by forming the trap region by ion implantation of hydrogen, the trap region can be accurately and easily formed at a position of an arbitrary depth of the low concentration base layer. .

According to the fourth aspect of the invention, when the semiconductor device is used as the switching means of the current resonance type circuit, almost no electric field is generated inside the semiconductor device when the semiconductor device is turned off. Therefore, a large amount of carriers remain in the low concentration base layer. This carrier is efficiently removed by the trap region.

Therefore, since the carriers are removed smoothly, no current flows due to the influence of the carriers, and the tail loss can be reduced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
This will be described with reference to FIG. FIG. 1 shows an electrostatic induction thyristor T.
It is a partial perspective view which shows the structure of hy. An N ⁻ -type high resistivity layer 3 as a low-concentration base layer is formed on the upper surface of a P ^{+ -type} substrate 1 serving as a rectangular parallelepiped anode layer. The N ^-
A buffer layer 2 connected to the P ^{+ -type} substrate 1 is formed below the high resistivity layer 3. Therefore, the N ⁻ -type high resistivity layer 3 can be thinned accordingly, and the thyristor Thy
It is possible to lower the on-voltage of. Also, the punch through voltage can be increased.

[0020] The N ^- on the upper surface of the type high resistivity layer 3 P by impurity diffusion in the longitudinal direction ^- form the channel layer 4 is formed. An N ^{+ -type} cathode layer 5 is formed on the upper surface of the P ⁻ -type channel layer 4 by thermal diffusion, and the N ^{+ -type} cathode layer 5 is surrounded by the P ⁻ -type channel layer 4. A P ^{+ -type} gate layer 6 is formed on the upper surface of the N ⁻ -type high resistivity layer 3 by thermal diffusion so as to sandwich the P ⁻ -type channel layer 4. The P ⁺ gate layer 6 is electrically connected to the rear side of the P ^{+ type} substrate 1 of FIG. With this configuration, the electrostatic induction thyristor Thy is in a normally-off state.

An oxide film 7 is formed on the upper surfaces of the P ^{− type} channel layer 4, the N ^{+ type} cathode layer 5 and the P ^{+ type} gate layer 6. On the rear side of the P ^{+ type} substrate 1, the oxide film 7 is formed.
The removal part 8 is formed in the. By this removing unit 8, P
A part of the ^{+ type} gate layer 6 is exposed on the upper surface.

A contact hole 9 corresponding to the N ^{+ type} cathode layer 5 is formed in the oxide film 7. The contact hole 9 exposes the N ^{+ -type} cathode layer 5 on the upper surface.

The above P⁺Oxide film on the rear side of the shaped substrate 1
A gate electrode 10 is formed on the upper surface of 7 and
The gate electrode 10 is connected to the P⁺Contact the gate layer 6
Has been continued. In addition, the acid should be separated from the gate electrode 10.
A cathode electrode 11 is formed on the upper surface of the chemical film 7. This
The cathode electrode 11 of the N through the contact hole 9 ⁺
Shaped cathode layer 5. Also, P⁺Shaped board 1
The anode electrode 12 is formed on the back surface.

When a positive voltage is applied to the anode electrode 12 and a negative voltage is applied to the cathode electrode 11 and a positive voltage is applied to the gate electrode 10, the electrostatic induction thyristor Thy is turned on.

Next, an evaluation circuit for evaluating the electrostatic induction thyristor Thy configured as described above will be described. As shown in FIG. 3, the electrostatic induction thyristor Thy for evaluation and the control thyristor Thy1 are connected in series to the power source 20. A diode 21 having a reverse bias is connected in parallel to the electrostatic induction thyristor Thy, and a diode 22 having a reverse bias is connected in parallel to the thyristor Thy. Furthermore, the coil 23 and the capacitor 24 connected in series are connected to the thyristor Thy1.
Are connected in parallel.

A drive circuit 25 is connected to the gates of the electrostatic induction thyristor Thy and thyristor Thy1,
The electrostatic induction thyristor Thy and the thyristor Thy1 are turned on and off at a predetermined timing.

Next, the evaluation circuit was operated based on the time chart shown in FIG. 5 to evaluate the electrostatic induction thyristor Thy. First, the drive circuit 25 applies a positive gate voltage VG1 to the gate of the electrostatic induction thyristor Thy at time t0. Then, the electrostatic induction thyristor T
A gate current IG1 flows through the gate of hy for a moment. Therefore, the electrostatic induction thyristor Thy turns on. As shown in FIG. 4A, the electrostatic induction thyristor T
When hy turns on, coil 23 and capacitor 24
A resonance current IA1 that becomes a sine wave based on the resonance of flows in the coil and the capacitor 24. Due to this resonance current IA1, a voltage higher than that of the power source 20 is accumulated in the capacitor 24.
The period of the sine wave can be changed by the constants of the coil 23 and the capacitor 24.

When the resonance current IA1 becomes 0 at time t1, the capacitor 24 is turned on as shown in FIG. 4 (b).
A negative feedback current -IA1 flows through the diode 21 due to the electric charge accumulated in the diode 21. The drive circuit 25 applies a negative gate voltage -VG1 to the gate of the electrostatic induction thyristor Thy at a time t2 when a predetermined time .DELTA.t has elapsed since the resonance current IA1 became zero. Then, a negative gate current -IG1 flows through the gate of the static induction thyristor Thy, and the static induction thyristor Thy is turned off.

Next, at time t3, as shown in FIG. 4 (c), the feedback current -IA1 flowing through the diode 21 is zero.
Then, the thyristors Thy and Thy1 and the diodes 21 and 22 are turned off, so that the coil 23 and the capacitor 24 are not connected to the power supply 20. Therefore, the voltage VAK between the anode and the cathode of the electrostatic induction thyristor Thy is half the voltage of the power supply 20.

Next, at time t4, the drive circuit 2
5 applies a positive gate voltage VG2 to the gate of the thyristor Thy1. Then, the gate current IG2 flows through the gate of the thyristor Thy1 for a moment, and the thyristor Thy1 is turned on. Therefore, the negative resonance current -IA2 flows through the coil 23 and the capacitor 24. Further, since the thyristor Thy1 is turned on, the voltage of the power supply 20 is applied to the voltage VAK between the anode and the cathode of the electrostatic induction thyristor Thy. Then, when the resonance current −IA2 becomes 0, the feedback current IA2 flows through the diodes 21 and 22 due to the charge accumulated in the capacitor 24.

The drive circuit 25 applies a negative gate voltage -VG2 to the gate of the thyristor Thy1 at a time t5 when a predetermined time Δt has elapsed after the resonance current -IA2 becomes zero. Then, a negative gate current -IG2 flows through the gate of the thyristor Thy1, and the thyristor Thy1 is turned off.

Here, if the driving frequency is high and the carrier remaining inside the electrostatic induction thyristor Thy cannot be removed at time t4, the thyristors Thy and Thy of each other are removed.
It will be short-circuited by y1.

Further, the time Δt from the time t1 when the current IA1 flowing through the anode of the electrostatic induction thyristor Thy becomes 0 to the time when the reverse bias is applied to the gate is adjusted. Then,
The relationship between the peak extraction amount IGP of the remaining carriers and the decay time τ of the reverse bias gate current −IG1 can be appropriately set, and the carriers can be removed. In this case, the reverse bias must be applied while the feedback current -IA1 is flowing in the diode 21, and the gate current -IG1 for extracting the carrier is 0 before the feedback current -IA1 flowing in the diode 21 becomes zero. Need to

Then, the time Δt is set to 0, 1, 2, 3, 4 μ
FIG. 6 shows the relationship between the peak withdrawal amount IGP and the decay end time τ when they are set to s. Time Δt is 0 μs
The peak extraction amount IGP is larger as it is closer to, but the decay end time (Δt + τ) is shorter. Conversely, when the time Δt increases, the peak extraction amount IGP decreases, but the attenuation end time (Δt + τ) increases.

Here, when the time Δt is brought close to 0 μs,
Since the peak extraction amount IGP is large, the extraction of the carrier can be speeded up, but the drive circuit 25
The load on the Further, if the time Δt is increased, the peak extraction amount IGP can be reduced, but the attenuation end time (Δt + τ) becomes long, and the feedback current −I
Even if A1 becomes 0, the gate current −IG1 does not become 0.

Therefore, in this embodiment, the driving frequency of the electrostatic induction thyristor Thy is 100 kHz, but the time Δt at this time is set to 2 μs.
Further, this time Δt can be arbitrarily changed according to the drive frequency used, and when the frequency is high, the time Δt is set to 0.
It is necessary to approach. On the contrary, when the frequency is low, the time Δt can be increased.

As a result, it is possible to smoothly pull out the remaining carrier by the gate-assisted carrier extraction. Here, if the drive frequency is increased, it is necessary to reduce the time Δt, but there is a limit to the time setting. Therefore, as shown in FIGS. 1 and 2, a predetermined distance L from the upper surface of the P ^{+ -type} gate layer 6, the P ^{− -type} channel layer 4, and the N ⁺ cathode layer 5 on which the oxide film 7 is formed.
A trap region 15 for trapping the remaining carriers is formed in the N ⁺ high resistivity layer 3 which becomes 1.

The trap region 15 is formed by completing the production of the electrostatic induction thyristor Thy shown in FIG. 1 and forming a protective film, and then implanting hydrogen ions from directly above the protective film.

The dose amount of the trap region 15 is actually set.
In the example, 0.6 × 10¹²cm ^-2, 1.0 x 10¹²
cm^-2, 1.5 x 10¹²cm^-2And three different types of static
An electric induction thyristor Thy was manufactured.

In addition to this, the position where the trap region 15 is formed is changed. That is, a predetermined distance L from the upper surface of the P ^{+ -type} gate layer 6, the P ^{− -type} channel layer 4, and the N ⁺ cathode layer 5.
A trap region 15 was formed in the N ^{+ type} buffer layer 2 to be 2. Then, three types of electrostatic induction thyristors Thy in which the dose amount of the trap region 15 is changed in the same manner as described above.
Was manufactured.

Further, a trap region 15 was formed in the P ^{+ type} substrate 1 at a predetermined distance L3 from the upper surfaces of the P ^{+ type} gate layer 6, the P ^{− type} channel layer 4 and the N ⁺ cathode layer 5. Then, three types of static induction thyristors Thy having different dose amounts were manufactured in the same manner as above. Further, each of these electrostatic induction thyristors Thy was evaluated by the same evaluation circuit as above. The time Δt was fixed at 2 μs.

FIG. 7 is a characteristic showing changes in the peak extraction amount IGP due to changes in the dose amount. FIG. 8 shows the characteristic of the decay end time τ due to the change of the dose amount. As can be seen from this characteristic, the peak extraction amount IGP and the attenuation end time τ are improved as the dose amount is increased. It is also found that the characteristics are best when the trap region 15 is formed in the N ^{− type} high resistivity layer 3. That is, normally, when the thyristor is turned off by hard switching, a reverse bias is applied between the anode and the cathode to generate an electric field. Due to this electric field, the depletion layer spreads from the cathode side of the N ^{− type} high resistivity layer 3, and the carriers are pushed out to the P ^{+ type} anode layer side through the N ^{+ type} buffer layer.

Therefore, even if the trap region 15 is formed in the N ^{− type} high resistivity layer 3, it becomes difficult to trap carriers. However, in the evaluation circuit of this embodiment, when the electrostatic induction thyristor Thy is turned off,
Since the feedback current −IA1 is flowing in the diode 21, the diode 21 becomes conductive. Therefore, the power source 20 is provided between the anode and the cathode of the electrostatic induction thyristor Thy.
Since no voltage is applied, no electric field is generated between the anode and the cathode.

[0044] Therefore, residual carriers N ^- so present in the high resistivity layer 3, N ^- carrier is trapped by the trap region 15 formed on the high resistivity layer 3. Therefore, although the trap region 15 is formed in any one of the N ^{− type} high resistivity layer 3, the N ^{+ type} buffer layer 2 and the P ^{+ type} substrate 1,
It is preferable to provide the trap region 15 in the N ⁻ -type high resistivity layer 3 so that carriers can be trapped most efficiently.

FIG. 9 is a characteristic diagram showing the relationship between the decay end time τ and the ON voltage VON of the electrostatic induction thyristor Thy. As can be seen from this characteristic, as the dose amount increases, the decay end time τ becomes shorter, but the ON voltage VON becomes higher. Therefore, the two are in a trade-off relationship.
Further, it can be seen from this characteristic that it also changes depending on the position where the trap region 15 is formed. As a result, by forming the trap region 15 in the N ⁻ -type high specific resistance layer 3,
The ON voltage VON and the decay end time τ can be most improved.

Therefore, it is possible to provide the electrostatic induction thyristor Thy which is driven at a low voltage and has a low loss even if the driving frequency of the electrostatic induction thyristor Thy is increased. Moreover, since the driving frequency can be increased, the transformer and the capacitor of the power supply device can be downsized.

Further, in this embodiment, since the trap region 15 is formed by hydrogen ion implantation, the trap region 15 can be easily formed at an accurate arbitrary position (distance L1 to L3). In this embodiment, the trap region 15 is formed by ion implantation of hydrogen, but in addition to this, the trap region 1 is formed by ion implantation of argon or the like.
It is also possible to form 5.

In the evaluation circuit, the thyristor Thy is used.
Although 1 is used, it can be changed to a switching element such as a transistor. FIG. 10 is an electric circuit diagram showing a usage example of the electrostatic induction thyristor Thy of the present invention. The power source 30 includes an electrostatic induction thyristor Thy and a coil 3.
1, the capacitor 32, and the primary side of the transformer Tr forming the forward converter circuit 33 are connected in series.
Then, a diode 29 which is a reverse bias is connected to the electrostatic induction thyristor Thy. Also, transformer Tr
A diode 34, a coil 35, and a resistor 36, which are forward biased, are connected in series on the secondary side of the. The cathode of the diode 37 is connected between the diode 34 and the coil, and the anode of the diode 37 is connected to the secondary side of the transformer Tr. A capacitor 38 is connected in parallel with the resistor 36. The gate of the electrostatic induction thyristor Thy is controlled by the drive circuit 39.

A positive voltage is applied to the gate by the drive circuit 39 to turn on the electrostatic induction thyristor Thy. Therefore, a sinusoidal resonance current I10 due to the coil 31 and the capacitor 32 flows. An output current I11 based on the resonance current I10 is output to the secondary side of the transformer Tr.

Then, when the resonance current I10 becomes 0, the feedback current −I10 flows through the diode 29 due to the charges accumulated in the capacitor 32. 2 μs after the resonance current I10 becomes 0, the drive circuit 39 applies a negative voltage to the gate. At this time, the peak extraction amount IGP is suppressed to a low level, and the attenuation end time τ can be set before the feedback current −I10 becomes zero. Therefore, the carrier can be pulled out to some extent. On the contrary, before the feedback current −I10 becomes 0, a negative voltage is applied to the gate, so that the voltage of the power source 20 is not applied between the anode and the cathode. Therefore, the carriers existing in the N ⁻ -type high resistivity layer 3 are efficiently trapped by the trap region 15, and the remaining carriers are smoothly removed.

Then, the drive circuit 39 again applies a positive voltage to the gate to turn on the electrostatic induction thyristor Thy, and thereafter, this operation is repeated in the same manner as above.
Note that almost no current is output to the secondary side of the transformer Tr due to the feedback current −I10. This is because the forward converter circuit 33 serving as a load is provided. Therefore, only the positive side sine wave based on the turn-on of the electrostatic induction thyristor Thy is output to the secondary side of the transformer Tr of the forward converter circuit 33.

In this embodiment, the N ^--type high resistivity layer 3 is used.
Although the trap region 15 is provided in the above, it is also possible to form the trap region 15 in the N ⁺ buffer layer 2 or both as necessary.

In this embodiment, the N ⁺ buffer layer 2 is formed on the N ⁻ -type high resistivity layer 3. However, the electrostatic induction thyristor T having the structure in which the N ⁺ buffer layer 2 is eliminated as necessary.
It may be hy. In addition, reverse conduction type, that is, N ⁺ anode layer, P ⁻ base layer, N ⁻ channel layer, P ⁺ cathode layer,
An electrostatic induction thyristor composed of a P ⁺ buffer layer may be used.

The present invention is not limited to the above embodiments, but can be embodied in the following modes, for example. (1) Any current resonance type that performs soft switching may be used. For example, the electrostatic induction thyristor Thy as the semiconductor device according to claim 1 or 2 and the coil 31 and the capacitor 32 are connected in series to the power supply 30. , The diode 37 which is reverse biased to the electrostatic induction thyristor Thy
Are connected in parallel. When the electrostatic induction thyristor Thy is turned on, the resonance current I10 of the coil 31 and the capacitor 32 flows, and after the resonance current I1 becomes 0, the current −I10 due to the charge accumulated in the capacitor 32 flows to the diode 37. The electrostatic induction thyristor Thy is sometimes turned off.

When the electrostatic induction thyristor Thy is turned on, the resonance current I10 flows through the coil 31 and the capacitor 32, and a voltage higher than that of the power source 30 is accumulated in the capacitor 32. Then, when the resonance current I10 becomes 0, the current −I10 due to the charge accumulated in the capacitor 32 flows through the diode 37. At this time, since the diode 37 is in the conductive state, the voltage is applied only between the anode and the cathode of the electrostatic induction thyristor Thy by about the voltage drop of the diode 37.

Therefore, since no electric field is generated between the anode and the cathode, the carriers remaining inside the electrostatic induction thyristor Thy are present in the N ^{− type} high resistivity layer 3. The carriers are trapped and removed by the trap region 15 formed in the N ⁻ -type high resistivity layer 3.

As a result, the remaining carriers can be removed efficiently, so that the tail loss of the electrostatic induction thyristor Thy can be reduced and the frequency can be increased. (2) The present invention is applicable to general thyristors, GTO thyristors, and IGBTs (Insulated) in addition to the electrostatic induction thyristor.
Gate Bipolar Transistor),
The same effects as the above are achieved.

[0058]

As described in detail above, according to the first and second aspects of the present invention, carriers are trapped and removed in the trap region formed in the low-concentration base layer. Therefore, when the semiconductor device is turned off. There is an excellent effect that the tail loss can be reduced.

According to the invention of claim 3, claim 1
In addition to the effect of No. 2, there is an excellent effect that the trap region can be accurately and easily formed at an arbitrary depth position of the low concentration base layer by hydrogen ion implantation.

According to the invention described in claim 4, when the semiconductor device according to any one of claims 1 to 3 is used for the switching means of the current resonance type circuit, an electric field is not generated in the semiconductor device at the time of off, The carriers existing in the low-concentration base layer can be efficiently trapped by the trap region, and there is an excellent effect that the tail loss of the semiconductor device can be reduced.

[Brief description of drawings]

FIG. 1 is a partial perspective view showing the configuration of an electrostatic induction thyristor according to the present invention.

FIG. 2 is a front view showing the configuration of an electrostatic induction thyristor.

FIG. 3 is an evaluation circuit for evaluating an electrostatic induction thyristor.

FIG. 4A to FIG. 4D are operation explanatory views for explaining the operation of the evaluation circuit.

FIG. 5 is a timing chart diagram for operating an evaluation circuit.

FIG. 6 is a peak extraction amount with respect to time Δt, time Δt
It is a characteristic view which shows the decay end time with respect to.

FIG. 7 is a characteristic diagram showing a characteristic of a peak extraction amount with respect to a change in dose amount.

FIG. 8 is a characteristic diagram showing a characteristic of an attenuation end time with respect to a change in dose amount.

FIG. 9 is a characteristic diagram showing the characteristics of the on-voltage with respect to the decay end time.

FIG. 10 is an electric circuit diagram showing a usage example of the electrostatic induction thyristor.

FIG. 11 is a switching waveform diagram of the GTO thyristor.

FIG. 12 is a switching waveform diagram of a GTO thyristor.

[Explanation of symbols]

1 ... P ⁺ form substrate as an anode layer, 3 ... low concentration N as the base layer ^- type high resistivity layer, 5 ... (N ⁺⁾ cathode layer, 6 ... (P ⁺⁾ gate layer, 15 ... trap region

Claims (4)

[Claims] 1. A semiconductor device in which a low-concentration base layer is formed on an upper surface of an anode layer, and a cathode layer and a gate layer are formed on an upper surface of the low-concentration base layer, wherein the low-concentration base layer has a trap for carrier trapping. A semiconductor device in which a region is formed. 2. A base layer is formed on the upper surface of the drain layer,
A semiconductor device in which a source layer and a gate layer are formed on an upper surface of the base layer, wherein a trap region for carrier trap is formed in the low concentration base layer. 3. The semiconductor device according to claim 1, wherein the trap region for carrier trap is formed by ion implantation of hydrogen. 4. A semiconductor device using the semiconductor device according to claim 1 as a switching means of a current resonance type circuit.