JPH07211082A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize the high speed data amplification by a semiconductor memory device regardless of the variation at the time of manufacture. CONSTITUTION:The potential of a common data line part 8 and 9 is set at a reference voltage Vref by the voltage negative feedback of differential amplifiers 10 and 11 and the signal amplitude of the common data line pair 8 and 9 is reduced. A current DELTAI from a memory cell 1 is converted into a voltage by transistors 41 and 42 in a negative feedback loop. As a result, even if a variation or an offset voltage exists in the differential amplifiers, the signal amplitude of the common data line pair 8 and 9 can be reduced and the high speed data amplification with a low power consumption can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device capable of reducing the signal amplitude of a data line and reading data in a memory cell at high speed.

[0002]

2. Description of the Related Art As a conventional semiconductor memory device for reading data stored in a memory cell at high speed, 1992 iE International Solid
State Circuit Conference, Digest
Of Technical Papers, pp. 208-209 (1
992 IEEE International Solid State Circuit Confere
nce, Digest of Technical Papers, pp.208-209).

[0003]

In order to speed up the data read time of a semiconductor memory device having two data lines, that is, a pair of data lines, it is generally effective to reduce the signal amplitude of the data line pair. . The signal amplitude of the data line pair is ΔV,
When the parasitic capacitance of the data line is C and the current of the transistor that drives the data line is I, the time t until the potential of the data line is changed is given by the following equation. t = CΔV / I Therefore, by reducing the signal amplitude ΔV, the time t
Becomes smaller and high speed operation becomes possible. In the above conventional technique, a so-called current sense type sense amplifier is used in which the current of the memory cell is introduced into the sense amplifier in order to reduce the signal amplitude of the data line and the current is converted into a voltage in the sense amplifier. .

It can be said that the above-mentioned conventional example is effective in realizing the high-speed operation of the semiconductor memory device to some extent. But,
As a result of a detailed study, it was found that the above-mentioned conventional example has a limitation in further speeding up for the following reason. That is, in the sense amplifier of the above conventional example, the delay time increases when the characteristics of the MOSFETs forming the sense amplifier vary and the offset voltage of the sense amplifier increases. For example, if the pair of P-channel MOSFETs forming the sense amplifier have different threshold voltages, the amplification delay time increases significantly. For example, with a difference in threshold voltage of 20 mV, the delay time is about 2n.
s, and the threshold voltage difference of 50 mV or more also causes no operation. Usually, the threshold voltages of the two MOSFETs do not completely match, and a difference of about 20 mV occurs on average. Therefore, it is difficult for the conventional sense amplifier to avoid an increase in delay time due to a difference in threshold voltage. That is, the conventional sense amplifier can realize high-speed amplification by reducing the amplitude of the data line when there is no ideal threshold voltage difference, but the delay time is rather increased when the offset voltage is large. was there.

The object of the present invention is to solve the above problems of the conventional example, eliminate the influence of the threshold voltage and offset voltage of the MOSFET of the sense amplifier, and reduce the signal amplitude of the data line so that the data is stored in the memory cell. It is possible to amplify existing information at high speed.

[0006]

To achieve the above object, according to one embodiment of the present invention (see FIG. 2), the data line pair (2, 3) of the memory cell (1) is a selector switch.
Connected to the common data line pair (8, 9) through (6, 7),
The pair of common data lines (8, 9) are two sense MOSFs.
The gate electrodes of the two sensing MOSFETs (41, 42) are connected to the drains of the ETs (41, 42), and the differential amplifiers for setting the potentials of the common data line pair (8, 9) ( 10 and 11), the reference voltage (Vref) is input to the inverting input terminals (-) of the two differential amplifiers (10, 11), and the two differential amplifiers (1
0, 11) non-inverting input terminal (+) has a common data line pair
(8, 9) are connected. Further, according to the present embodiment, the reference voltage (Vref) input to the non-inverting input terminal (+) of the differential amplifier (10, 11) is based on the power supply voltage (Vcc) and the sense MOSFET (41). , 42) is subtracted from the threshold voltage (Vth). That is, the condition of Vcc-Vth <Vref is satisfied, and as a result, the sensing MOSFET (4
1, 42) is characterized in that it operates in the saturation region. That is, in the region where the drain conductance does not fluctuate due to the fluctuation of the drain voltage, the sense MOSF
ET (41, 42) is operated, the differential amplifier
Memory cell independent of (10,11) offset voltage
It becomes possible to convert the current (ΔI) of (1) into a voltage.
The above conditions are obtained by subtracting the threshold voltage (Vth) from the maximum value of the gate voltage of the sensing MOSFETs (41, 42) (that is, the maximum output value Vcc of the differential amplifier (10, 11) (Vcc).
-Vth) is larger than the drain-source voltage V _DS (Vref) of the sensing MOSFETs (41, 42), and as a result,
This is derived from the condition that the sensing MOSFETs (41, 42) operate in the saturation region, that is, the pentode region.

[0007]

In the typical embodiment of the present invention (FIG. 2), the differential amplifiers (10, 11) and the sensing MOSFETs (41, 4) are used.
2) forms a feedback circuit, and the gate voltage of the MOSFETs (41, 42) for sensing is fixed so that the potential of (8, 9) of the common data line pair is fixed to the same value as the reference voltage (Vref). Is controlled. Therefore, common data line pairs
Both the potentials (8, 9) are maintained close to the reference voltage (Vref), and the potential difference can be made extremely small, which is effective in reducing the delay time.

Next, the operation of converting the voltage into a voltage in proportion to the current (ΔI) of the memory cell (1) without depending on the offset voltage of the differential amplifier (10, 11) will be described. In FIG. 2, the current flowing through the data line pair (2, 3), the common data line pair (8, 9) and the sense MOSFET (41, 42) in the state where the current (ΔI) does not flow in the memory cell (1). Is Io.
The word line (32) is selected and the current is ΔI in the memory cell (1).
Flows, the current flowing through the data line (2), the common data line (8) and the sensing MOSFET (41) changes to Io-ΔI. The conductances of the MOSFETs (41, 42) are β ₄₁ , β ₄₂ , and the gate voltages are V1 (V _GS41 ), V2 (V
_GS42 ), threshold voltage Vth ₄₁ , Vth ₄₂ , differential amplifier (1
If the offset voltage of 0, 11) is Voff ₁₀ and Voff ₂₀ , the potential of the common data line pair (8, 9), that is, MOSF
The drain-source voltages of ET (41, 42) are Vref + Voff ₁₀ and Vref + Voff ₂₀ , respectively. At this time, since the MOSFETs (41, 42) operate in the saturation region, that is, the pentode region, as described above, the drain currents of the MOSFETs (41, 42) are respectively drain-source voltages Vref + Voff ₁₀ and Vref +.
It is given by the following equation without depending on Voff ₂₀ .

[0009]

[Equation 1]

[0010]

[Equation 2]

Therefore, the gate voltages V1 (= V _GS41 ) and V2 (= V _GS42 ) of the MOSFETs (41, 42) are respectively given by the following equations.

[0012]

[Equation 3]

[0013]

[Equation 4]

MOSFETs (41, 42) so that the channel length L and the channel width W of the MOSFET 41 match the channel length L and the channel width W of the MOSFET 42 with high accuracy.
, The conductances β ₄₁ and β ₄₂ of the MOSFETs (41, 42) can be matched with each other with high accuracy, and M
Threshold voltage difference of OSFET (41, 42) Vth ₄₂ -V
than the value of th ₄₁ , M due to the current (ΔI) of the memory cell (1)
Change in gate-source voltage of OSFET 41 √ (2Δ
MOSFET (41, 42) to increase I / β)
If the conductances β ₄₁ and β ₄₂ = β are set to sufficiently small values, the following equation is obtained.

[0015]

[Equation 5]

Thus, the current (ΔI) of the memory cell (1) is
As a result, a difference voltage V2-V1 between the gate-source voltages of the MOSFETs 41 and 42 is generated. Furthermore, this difference voltage V
2-V1 can be amplified by the differential amplifier (45) of the next stage. Accordingly, representative embodiments of the present invention
According to FIG. 2, the influence of the threshold voltage and the offset voltage of the MOSFET of the sense amplifier can be eliminated, the signal amplitude of the common data line pair can be reduced, and the information stored in the memory cell can be amplified at high speed. It will be possible. Other objects and features of the present invention will be apparent from the following examples.

[0017]

FIG. 1 is a circuit diagram for explaining the principle of the effect of reducing the signal amplitude of a common data line pair by the differential amplifier of the present invention. In FIG. 1, 1 is a memory cell, 31 is a power supply terminal, 32 is a word line, 2 and 3 are data line pairs, and 4 and 5 are P-channel MOS which are loads of the data line pairs 2 and 3.
FETs, 6 and 7 are P-channel MOSFETs that are selector switches, and 8 and 9 are common data line pairs, 10 and 1.
1 is a differential amplifier for setting the potentials of the common data line pairs 8 and 9 to reduce the signal amplitude thereof, 23 and 24 are load elements of the memory cell 1, 25 and 26 are transfer MOSFETs, 2
7 and 28 are drive MOSFETs, and 29 and 30 are storage nodes of the memory cell. In the present example of FIG. 1, the data line pair (2, 3) is connected to the common data line pair (8, 9) through the selector (6, 7), and the common data line pair (8, 9) is a differential amplifier. It is connected to the output terminal of (10, 11), and this output terminal is the inverting input terminal of the differential amplifier (10, 11).
The feedback circuit is formed by being connected to (-) and applying the reference voltage (Vref) to the non-inverting input terminal (+) of the differential amplifier (10, 11). That is, since the common data line pair (8, 9) is an output terminal of a so-called voltage follower circuit using the differential amplifier (10, 11), the potential of the common data line pair (8, 9) is changed to the differential amplifier. (1
It can be fixed to the same value as the reference voltage (Vref) applied to the non-inverting input terminal (+) of 0, 11). Therefore, the signal amplitude of the common data line pair (8, 9) and the data line (2, 3) can be extremely increased. On the other hand, in the present example of FIG. 1, the reference voltage (Vref) applied to the non-inverting input terminal (+) of the differential amplifier (10, 11) is the word line (3) of the memory cell (1).
From the voltage (Vw) in the selected state of 2), transfer MOSFET (2
5, 26) is set to a value larger than the value obtained by subtracting the threshold voltage (Vth). That is, the following inequality is satisfied. Vw−Vth <Vref As a result, the reference voltage (Vref) applied to the non-inverting input terminal (+) of the differential amplifier (10, 11) is set to a value larger than Vw−Vth, so that the data line pair (2, 3)
Can be set to a value larger than Vw-Vth. For example, if the storage node (30) in the memory cell (1) is "H
When information is accumulated at the voltage of "(high level)", the word line (32) which is the gate electrode of the transfer MOSFET (26)
There even when the value of the selected Vw, the voltage between the gate and source when the potential of the data line becomes the source electrode (3) is maintained at the same conditions as the reference voltage (Vref> V _W -Vth) is It becomes below the threshold voltage. Therefore, transfer MOSFET (26)
Does not become conductive. In this case, transfer MOSFET
Through (26), the H level storage node in the memory cell
The signal voltage stored in (30) does not flow to the data line. Therefore, the storage node (3
It is characterized in that the signal voltage stored in (0) does not drop and the operating margin is impaired, and the soft error due to alpha rays does not weaken. However, in this example of FIG. 1, a voltage proportional to the current from the memory cell (1) cannot be taken out, so this point will be described in the following embodiments.

FIG. 2 shows a first embodiment of the present invention, in which the present invention is a semiconductor memory device having a static type memory cell 1 (see FIG. 1) (for example, a static random access memory).
It is a circuit diagram applied to. Since the basic configuration and operation of FIG. 2 have already been described, only points that have not been described above will be described below to avoid redundant description. In FIG. 2, P-channel MOSFETs 4 and 5 as data line loads are connected between the power supply voltage terminal 31 and the data line pairs 2 and 3, and the data line pairs 2 and 3 are connected to common data via selector switches 6 and 7. It is connected to line pairs 8 and 9. Although not shown, a plurality of data line pairs are similarly connected to the common data line pairs 8 and 9 via a plurality of selector switches. As in the example of FIG. 1, in the embodiment of FIG. 2, the reference voltage (Vref) applied to the inverting input terminal (−) of the differential amplifier (10, 11) is the word line of the memory cell (1). 32) Transfer MOSFET of the memory cell (1) from the selected voltage (Vw)
It is set to a value larger than the value obtained by subtracting the threshold voltage (Vth) of (25, 26). As a result, the signal voltage stored in the high-level storage node (30) in the memory cell (1) does not drop to impair the operating margin, and it is not vulnerable to a soft error due to alpha rays. The two differential amplifiers 10 and 11 are composed of a plurality of MOSFETs, and the channel length L and the channel width W of the N-channel MOSFETs 41 and 42 for sensing which operate in the saturation region are set equal to each other by setting the reference voltage (Vref). , Its conductance β is set to be extremely small. As a result, the current from the memory cell (1) is expressed by the above-mentioned equation 5 of the N-channel MOSFETs 41 and 42 for sensing.
A voltage proportional to (ΔI) can be taken out. That is, as shown in the above equation 5, the drain voltages V _DS41 , V of the N-channel _MOSFETs 41, ₄₂ for sensing are
_{The DS42} is fixed to the reference voltage (Vref) by the feedback circuit composed of the differential amplifiers 10 and 11, and has different drain currents Io-ΔI (I _DS41 ) and Io (I).
_DS42 ) flows. Therefore, the N-channel MOSFET 4
The gate voltages V1 (V _GS41 ) and V2 (V _GS42 ) of _{Nos. 1 and 42} generate a potential difference according to their conductance and the drain current difference (ΔI). Here, when the conductance β of the N-channel _{MOSFETs 41} and _{42 is} set to be extremely small, as is apparent from the above equation, the gate voltage V1 (V1 The change amount (ΔV) of _GS41 ) and V2 (V _GS42 ) becomes large. Therefore, the N-channel MOSFETs 41, 42
Although the gain of itself decreases, the gain of the differential amplifier (or
The potential difference that can be taken out as the output becomes large.

Further, generally, when the gate length of the MOSFET is increased, the threshold voltage due to process variations or the like is caused.
The fluctuation of (V _th ) can be suppressed small. Therefore,
As described above, the N-channel MOSFETs 41 and 42, which may have a small conductance, can have a large gate length, and the threshold voltage (V
It is possible to reduce the fluctuation of _th ). On the contrary, the differential amplifiers 10 and 11 are N-channel MOSFE.
A relatively large conductance is required to drive the T41 and T42, and the MOSF that constitutes the differential amplifiers 10 and 11 is required.
Although the gate length of ET is also made relatively small, the influence of its threshold voltage and offset voltage can be eliminated by adopting the configuration of the present invention, so that the conductance can be made sufficiently large.

The signal converted into a voltage by the two differential amplifiers 10 and 11 and the two N-channel MOSFETs 41 and 42 for sensing is further amplified by the differential amplifier 45 and output to a data bus or a data output buffer. Then, the final data signal can be obtained.

FIG. 3 is a diagram showing a simulation result comparing the effect of the first embodiment of FIG. 2 of the present invention with the conventional method. The simulation conditions are a power supply voltage of 2.5V,
The current consumption of the sense amplifier was 1.1 mA. FIG. 3 shows changes in the threshold voltage of one of the P-channel MOSFET used in the differential amplifiers 10 and 11 of the first embodiment of FIG. 2 of the present invention and the P-channel MOSFET of the conventional sense amplifier. It shows a change in delay time when the delay time is changed. In the conventional method, the change in threshold voltage ΔVth
Becomes larger, the delay time increases, and when the change in the threshold voltage becomes larger than 40 mV, it finally stops operating. On the other hand, in the system of the first embodiment of the present invention, there is almost no increase in the delay time even if the threshold voltage changes, and it operates without problems even if the threshold voltage changes by at least 50 mV. . In addition, since the signal amplitude of the common data line can be made extremely small, it is shown that it can operate at high speed with the same power consumption as compared with the conventional method.

FIG. 4 is a more specific embodiment of the first embodiment of FIG. 2 of the present invention, which illustrates in detail the internal configuration of the differential amplifiers 10 and 11, and the embodiment of FIG. Differences from the above will be described below. In FIG. 4, 70 is an equalizing P-channel MOSFET for reducing the potential difference between the data line pairs 2 and 3, and 51 and 52 are P-channel MOSFETs that are the loads of the common data line pairs 8 and 9. P-channel MOSFETs 53 and 54 and N-channel MOSFET 5
Reference numerals 5 and 56 are current mirror type differential amplifiers.
The differential amplifier 10 of the P-channel MOSFET 5
8, 59 and N-channel MOSFETs 60, 61 are current mirror type differential amplifiers.
And the N-channel MOSFET 57 constitutes a constant current source common to the two differential amplifiers 10 and 11 in FIG.

The P-channel MOSFETs 65 and 66 and the N-channel MOSFET 67 form a reference voltage generating circuit and generate a reference voltage Vref. In addition, P channel MOS
The FETs 65 and 66 are depletion type, and their threshold voltage is negative. Differential pair N-channel MOSFET
62 and 63 and the N-channel MOSFET 64 of the constant current source constitute a current switch type differential amplifier to drive the data buses 68 and 69 which are the second common data line pair. In this embodiment of FIG. 4, the differential amplifiers 53, 54, 55,
The potential difference between the common data lines 8 and 9 can be made extremely small by the action of 56, 57, 58, 59, 60 and 61, but since the MOSFETs 6 and 7 of the selector act as a resistance, the potential difference between the data line pairs 2 and 3, that is, the signal amplitude is Common data lines 8, 9
The potential difference cannot be reduced as much. In such a case, the equalize MOSFET 70 of the data line pairs 2 and 3 of the present embodiment.
Can be used to reduce the potential difference between the data line pairs 2 and 3. That is, during the data read period (while the write control signal (/ WE) is at the high level and its inverted signal (WE) is at the low level in this example), the data line equalize signal SE
By setting 1 to low level and turning on the P-channel MOSFET 70, the potential difference between the data line pairs 2 and 3 can be reduced. This data line equalize signal SE
1 is P-channel MOSFET 70 during the data reading period
Any signal can be used as long as it can control the ON state, and can be formed by inverting the write control signal (/ WE). Even in this case, the features of the present invention are not impaired. In addition, sense amplifiers 53, 54, 55, 56, 5
7, 58, 59, 60, 61 and MOSFETs 41, 42
The signal converted into the voltage by the
The data bus 68, 69 is converted to a current again by a current switch type differential amplifier composed of FETs 62, 63, 64.
May be output to.

Further, a MOS constituting the reference voltage generating circuit
The sense amplifier control signal SS for turning off the MOSFET is inputted to the FET 67, the MOSFET 57 which constitutes the constant current source of the current mirror type differential amplifier, and the MOSFET 64 which constitutes the constant current source of the current switch type differential amplifier. To be done. With such a configuration, the differential amplifier or the like used for amplifying read data can be turned off when writing to the memory,
It is possible to reduce the current consumption that flows during writing.
The sense amplifier control signal SS may be any signal as long as it can inactivate the sense amplifier during the data writing period, and for example, the chip selection signal (/ CS) and the write control signal (/ W
The signal formed from E) can be used.

FIG. 5 is a circuit diagram for explaining the principle of the effect of reducing the signal amplitude of the data buses 68 and 69 of FIG. In this example, the current switches 62, 63, 64 are the same as in FIG. 4, and the sense amplifiers 53, 54, 5 in FIG.
The signals D, / D amplified by 5, 56, 57, 58, 59, 60, 61 are converted into currents and output to the data buses 68, 69. In FIG. 5, the potentials of the data buses 68 and 69 are set using the differential amplifiers 70 and 71 that are negatively feedback-connected in the voltage follower format, and the data buses 68 and 6 are set.
The amplitude of 9 is reduced. This has the effect of reducing the delay time of the data buses 68 and 69 as in the example of FIG. However, in the present example of FIG. 5, a voltage proportional to the current from the memory cell cannot be taken out, so
This point will be described below.

FIG. 6 is a diagram showing a circuit diagram and operation waveforms capable of reducing the signal amplitude of the data buses 68 and 69 of FIG. 4 and taking out a voltage proportional to the current from the memory cell to the data buses 68 and 69. Finally, the signals of the data buses 68 and 69 can be finally output to the data output terminal 110 of the chip. In FIG. 6, reference numerals 80 and 81 denote equalizing MOSFETs for reducing the potential difference between the data buses 68 and 69, and P-channel MOSFETs 82 and 81.
83 and the N-channel MOSFETs 84, 85, 86 form a current mirror type differential amplifier, and the drain-gate connection of the N-channel MOSFET 84 causes the current mirror type differential amplifier to operate as a voltage follower. As a result, the data bus 69
Is a P-channel MOSFET 95, 96 and an N-channel M
The potential is set to be substantially equal to the reference voltage from the reference voltage generating circuit configured by the OSFET 97. The electric potential of the data bus 69 is minutely changed by the current switches 62, 63 and 64 of FIG. The N-channel MOSFET 92 of the push-pull buffer responds to this minute signal, while P-channel MOSFET 92
The channel MOSFET 92 outputs the amplified signal voltage V1 in response to the signals of the gates of the P-channel MOSFETs 82 and 83 of the current mirror in phase with this minute signal.

Similarly, P-channel MOSFETs 87, 8
8 and N-channel MOSFETs 89 and 90 form a current mirror type differential amplifier, and N-channel M
Due to the connection between the drain and the gate of the OSFET 90, this current mirror type differential amplifier operates as a voltage follower. As a result, the data bus 68 includes P-channel MOSFETs 95 and 96 and N-channel MOSFETs.
The reference voltage is set to a potential substantially equal to the reference voltage from the reference voltage generating circuit constituted by 97. The electric potential of the data bus 68 is minutely changed by the current switches 62, 63 and 64 shown in FIG. N-channel MOSF of push-pull buffer
The ET94 responds to this small signal while the P channel M
The OSFET 93 outputs the amplified signal voltage / V1 in response to the signals of the gates of the P-channel MOSFETs 87 and 88 of the current mirror in the same phase as this minute signal. For example, M connected to the data bus 68 of the current switch type differential amplifier
When the gate electrode of the OSFET 63 is set to the high level, from Vcc to the source / source of the P-channel MOSFET 88.
Current flows through the drain path to the data bus 68.
The data bus 68 has a reference voltage (VR
Although the potential is the same as that of (EF), the potential of the data bus 68 is slightly changed by the current switches 62, 63 and 64 of FIG. The gate voltage of the P-channel MOSFET 88 is the reference voltage (VREF) based on the potential of the data bus 68.
To lower to try to keep. Therefore, P channel MO
The gate voltage of the P-channel MOSFET 93 whose gate electrode is connected to the gate electrode of the SFET 88 also drops,
It outputs a high level amplified signal voltage / V1.

The amplified signal voltages V1 and / V1 are applied to load cross-coupled load P-channel MOSFETs 98 and 9.
9 and a differential pair N-channel MOSFETs 100 and 101 and a constant current source N-channel MOSFET 102. After being amplified by a differential amplifier, the P-channel MOS of the final output stage is passed through NOR circuits 105 and 106 and an inverter 107.
It is transmitted to the gates of the FET 108 and the N-channel MOSFET 109. Further, in this embodiment, in order to equalize the data buses 68 and 69 during the data reading period, the N-channel MOSFET 80 and the P-channel MOSFET are arranged.
And 81. These N-channel MOSFET8
The 0 and P-channel MOSFETs 81 are controlled by data bus equalize signals SE2 and / SE2 (/ SE2 is an inverted signal of SE2). Similarly, in this embodiment, the N-channel MOSFET 112 and the P-channel MOSF for equalizing the amplified signal voltages V1 and / V1 are used.
It has ET111. P-channel MOSFET 1
11 and N-channel MOSFET 112 are controlled by main amplifier equalize signals SE3 and / SE3, respectively. Similarly, in the present embodiment, the amplified signal voltages V2 and / V2 of the differential amplifier 111 whose loads are cross-coupled.
N-channel MOSFET 10 for equalizing and
4 and a P-channel MOSFET 103, which are controlled by main amplifier equalizing signals SE4 and / SE4, respectively.

As shown in the operation waveform diagram of FIG. 6, by equalizing the data buses 68, 69, etc., there is an effect that the speed can be further increased as compared with the case of inverting the data without equalizing.

Further, in this embodiment, the differential amplifiers 70, 7
N-channel MOSFET 8 which is a current source of 1 and 120
By controlling 6 and 102, the operation of the differential amplifiers 70, 71 and 120 is stopped during the data writing period to reduce unnecessary current consumption. N channel MO
The main amplifier control signal SM for controlling the SFETs 86, 102 is the differential amplifiers 70, 7 during the data writing period.
Any signal can be used as long as it can stop the operations of 1 and 120, and the data bus equalize signals SE2 and / SE2 can also be used.

Further, as shown by the operation waveform, the data bus 6
Since the MOSFETs 8 and 69 are equalized by the MOSFETs 80 and 81, there is an effect that a higher speed can be achieved as compared with the case where the data is inverted without the equalization.

FIG. 7 shows the effect of the embodiment of FIG. 6, in which the delay time with respect to the current consumption is obtained by simulation using the operating frequency as a parameter. As shown in FIG. 7, in the conventional method, the higher the operating frequency, the larger the current consumption. This is because the amplitude of the data bus is large and the AC current component is large. On the other hand, in this method, the consumption current hardly increases even if the operating frequency becomes high. Therefore, this method has an effect of increasing the operating frequency without increasing the current.

FIG. 8 shows an embodiment in which the sense amplifier and the main amplifier of the present invention are applied to a semiconductor memory device (in particular, a static random access memory).

Reference numeral 90 denotes a semiconductor memory device, which is formed on a single semiconductor substrate. MC is a memory cell that serves as a data storage unit, and is formed by a static memory circuit as shown in FIG. MM1 is a memory mat, and a plurality of memory cells MC are arranged in a matrix. The semiconductor memory device 9 is not particularly limited.
At 0, a plurality of memory mats (MM1 and MM2) are formed.

When reading the information stored in the memory cell MC, the X address Ax and the Y address Ay corresponding to the memory cell MC from which the information is to be read are input to the X address terminal 91 and the Y address terminal 92. It The input X address Ax is converted into complementary address signals ax, / ax by the X address buffer XADB and supplied to the X decoder XDEC. The X decoder XDEC decodes the input complementary address signals ax, / ax and selects a single word line WL corresponding to the input X address Ax. When the word line WL is selected, the plurality of memory cells MC connected to the word line WL are activated, and the data line pair DL, / to which each memory cell MC is connected is activated.
Output data to DL. Multiple data line pairs DL, / D
The data output to L is selectively connected to the common data line pair CDL, / CDL by the column selection circuit YSEL. The selection by the column selection circuit YSEL corresponds to the Y address Ay input to the Y address terminal 92, and is similar to the case of the X address Ax, in the Y address buffer YAD.
This is performed through the B and Y decoder YDEC.

The data signal output to the common data line pair CDL1, / CDL1 is transmitted to and amplified by the sense amplifier SA1 of the present invention. This sense amplifier SA1 is, for example, the differential amplifiers 10, 11, 45 shown in FIG.
It is composed of the FETs 41 and 42, and specifically is composed of the circuit shown in FIG. The data signal amplified by the sense amplifier SA1 is further transmitted to the data buses DB and / DB, and further amplified by the main amplifier MA of the present invention,
It is output from the output terminal 96 to the outside of the semiconductor memory device via the output buffer DOB. The main amplifier MA is composed of, for example, the differential amplifiers 70 and 71 shown in FIG. 5, specifically, the circuit shown in FIG. Although not particularly limited, the sense amplifiers (SA1, SA2) are arranged for each memory mat (MM1, MM2), and the memory mats are also the same.
Common data line pair (CD
L1, / CDL1, CDL2, / CDL2) are selectively amplified. The outputs of the sense amplifiers (SA1, SA2) are commonly connected to the data buses DB, / DB.

In this semiconductor memory device, since the sense amplifier and the main amplifier of the present invention are used, the signal amplitude of the common data line pair and the data bus can be suppressed, and high-speed reading of the data signal can be performed. it can.

As shown in FIG. 4, the data line equalize circuit DEQ connected to each data line pair is, for example, a transistor (7 in FIG. 4) which selectively short-circuits the data line pair.
0). The data bus equalize circuit DBEQ connected to the data bus is, for example, a transistor (80 in FIG. 6, 80, which selectively short-circuits the data bus shown in FIG. 6).
81). These data line equalize circuit DEQU and data bus equalize circuit DBEQ are
The data line equalize signals SE1, / SE1 and the data bus equalize signals SE2, / SE2 are controlled so as to equalize the data line pair DL, / DL and the data bus DB, / DB during the data writing period. , Data line pair DL, / DL when reading data
Also, the potential difference between the data buses DB and / DB can be eliminated, and the reading time of the data signal can be shortened.

A sense amplifier control signal SS is supplied to each of the sense amplifiers (SA1, SA2), and the sense amplifiers are controlled to be inactive during the data signal writing period as shown in FIG. . Similarly, the main amplifier M
The main amplifier control signal SM is supplied to A and is controlled to inactivate the main amplifier during the data signal writing period as shown in FIG.

The control circuit CONT is a semiconductor memory device 90.
Write control signal / WE, chip select signal / CS, output enable signal / O
E and the output signal of the address transition detection circuit ATD,
Internal control signals such as a data line equalize signal SE1 for controlling equalization of a data line pair, a data bus equalize signal SE2, a sense amplifier control signal SS for controlling sense amplifiers, and a main amplifier control signal SM are generated.
The data line equalize signal SE1 is not particularly limited.
Are formed on the basis of the write control signal / WE, and include the data bus equalize signal SE2 and the sense amplifier control signal SS.
And the main amplifier control signal SM is a write control signal / W
It is formed based on E and the output signal of the address change detection circuit ATD. Regarding the sense amplifier control signal SS, the write control signal / WE and the address transition detection circuit ATD
In addition to the output signal of, the mat selection signal obtained by decoding the Y address can be used. In addition, in the type of memory to which the reference clock is supplied from the outside,
A reference clock signal may be used instead of the ATD output signal.

Although the embodiment of the present invention has been described above, it is needless to say that the present invention is not limited to the above embodiment and various modifications can be made within the scope of the technical idea thereof. For example, as shown in FIG. 9, the two sensing transistors 41 and 42 may be bipolar transistors.
However, in this case, the base potential (base-emitter voltage V _{BE of the} transistors 41 and 42) is lower than the collector potential (V _ref ) so that the NPN bipolar transistors 41 and 42 operate in the non-saturation region. Therefore, it is necessary to set the reference voltage (V _ref ) according to the following equation. V _BE <V _ref Thus, NPN type bipolar transistors 41, 4
When 2 operates in the non-saturation region, the collector currents of the bipolar transistors 41 and 42 are given by the following equations.

[0042]

[Equation 6]

[0043]

[Equation 7]

Here, K is the Boltzmann constant, T is the absolute temperature, and Is is the saturation current.

Therefore, the bipolar transistors 41, 4
The differential voltage of the base of 2 is given by the following equation.

[0046]

[Equation 8]

[0047]

As described above, according to the present invention, the influence of the threshold voltage and the offset voltage of the MOSFET of the sense amplifier is small, and the signal amplitude of the data line is reduced so that the data is stored in the memory cell. Information can be amplified at high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining the principle of the effect of reducing the signal amplitude of a common data line pair by the differential amplifier of the present invention.

FIG. 2 is a circuit diagram of the first embodiment of the present invention in which the present invention is applied to a semiconductor memory device having static type memory cells.

FIG. 3 is a diagram showing a simulation result comparing the effect of the first embodiment of FIG. 2 of the present invention with a conventional method.

FIG. 4 is a diagram showing a more specific example of the first example of FIG.

5 is a circuit diagram for explaining the principle of the effect of reducing the signal amplitude of the data buses 68 and 69 of FIG.

FIG. 6 is a diagram showing a circuit diagram and an operation waveform capable of reducing a signal amplitude of the data bus of the embodiment of FIG. 4 and taking out a voltage proportional to a current from a memory cell to the data bus.

FIG. 7 is a diagram showing an effect of the embodiment of FIG.

FIG. 8 is a diagram showing an embodiment in which the present invention is applied to a semiconductor memory device.

FIG. 9 is a diagram showing a circuit according to a modified embodiment of the present invention.

[Explanation of symbols]

1 ... Memory cell, 2, 3 ... Data line pair, 8, 9 ... Common data line pair, 10, 11 ... Differential amplifier, 41, 42 ... MO
SFET, 68, 69 ... Data bus, 110 ... Output terminal.

Claims (4)

[Claims] 1. A plurality of memory cells, a plurality of data line pairs connected to the plurality of memory cells, a common data line pair connected to the plurality of data line pairs, and one of the common data line pairs. The non-inverting input terminal is connected to the line of No. 1, the first differential amplifier to which the reference voltage is applied to the inverting input terminal, and the non-inverting input terminal is connected to the other line of the common data line pair, A second differential amplifier having the reference voltage applied to its inverting input terminal and an input electrode thereof connected to the output of the first differential amplifier, the output electrode of which is connected to the one of the common data line pair. A first transistor connected to the line, and a second transistor having its input electrode connected to the output of the second differential amplifier and its output electrode connected to the other line of the common data line pair. And is equipped with Conductor memory device. 2. The first transistor and the second transistor are MOSFETs, and when the reference voltage is set to a predetermined value, each MOSFET operates in a saturation region. 1. The semiconductor memory device of 1. 3. The first transistor and the second transistor are bipolar transistors, and when the reference voltage is set to a predetermined value, each bipolar transistor operates in a non-saturation region. The semiconductor memory device according to claim 1. 4. The two input terminals of a third differential amplifier are connected to the input electrode of the first transistor and the input electrode of the second transistor. The semiconductor memory device according to any one of claims 1 to 3.