JPH07203457A - Motion vector detector - Google Patents

Abstract

PURPOSE:To attain high speed processing by executing difference absolute value accumulation processing in parallel, thereby reducing the capacity of a signal buffer for arithmetic operation. CONSTITUTION:An image block of interest is stored in a noted image memory 11, an image signal of a retrieval area is stored in a retrieval area memory 12 and extracted for each line and compared while being shifted. Thus, the accumulation value is obtained at once at plural positions by using difference absolute value accumulators 16-1-16-(2r+1) whose number is equal to number of reference image blocks taken in the line direction with respect to the retrieval area. The memory capacity used to store image signal for the image block of interest and the retrieval area is sufficiently reduced and a minimum number of the difference absolute value accumulators is prepared to execute the arithmetic operation processing for detecting a moving vector.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion vector detecting device used for signal compression coding of moving images.

[0002]

2. Description of the Related Art In multimedia systems and the like,
It is required to process moving image data together with various data such as character information. Therefore, in order to facilitate the storage and transfer of moving images, a highly efficient moving image compression coding method has been developed. In this method, for example, motion-compensated interframe predictive coding is performed to reduce redundancy in the time axis direction. In this method, a motion vector indicating how much in a certain direction an image block of a certain size has moved is obtained, and a pixel value at a position offset corresponding to the motion between image blocks is used as a prediction value, and the prediction value is The difference and the motion vector are encoded. Such a technique is described in the following documents.・ Yamada and Ueda, “4. Moving Image Coding Technology for Storage Media,” Journal of the Television Society, Vol.45, No.7, pp807-812 (19)
91) ・ Hiroshi Yasuda, "International Standards for Multimedia Coding", Chapter 6, pp126-129 (1991) Maruzen

FIG. 2 is a diagram for explaining the contents of the motion vector. As shown in the figure, for example, the current frame 1A is divided into a target image block 3A which is an appropriate processing unit. In addition,
It is assumed that the current frame 1A is displaying a moving image image 2 of, for example, a triangle as shown in the figure. Specifically, the current frame 1A has, for example, 240 pixels vertically and horizontally.
The image block 3A of interest is composed of x352 pixels.
Is selected to have a size of about 16 × 16 pixels.

Then, it is checked in which part of the previous frame 1B the target image block 3A is located. That is, the reference image block 3B having the most similar content to the attention image block 3A.
Is found in the vicinity of the same position as the target image block 3A of the previous frame 1B. For this, an image block of the same size is cut out around the same position as the target image block 3A of the previous frame 1B, and the difference between the image signals forming each block is calculated. The offset for the target image block 3A when this difference becomes the minimum is the motion vector 4.
The offset is position information of the reference image block based on the position of the target image block 3A.

FIG. 3 shows a block diagram of a general motion vector detection circuit. This circuit includes a buffer memory 6A for storing the target image block 3A and a buffer memory 6B for storing the search area 7. The outputs of both buffer memories 6A and 6B are input to the absolute value difference accumulator 8. Then, the accumulated result is input to the determiner 9.

Here, each image signal forming the image block 3A of interest is represented by the following equation (1). Pf (i + nx, j + ny) (1) (i + nx, j + ny) is the position coordinate of each image signal of the target image block 3A with reference to one point on the frame. In addition,
It is assumed that the image block of interest is composed of image signals arranged in a square having k sides. Therefore, the above nx, ny
Respectively take values 0 ≦ nx ≦ k−1 and 0 ≦ ny ≦ k−1.

The image signal in the search area is expressed by the following equation (2). Sf ((i + nx) + mx, (j + ny) + my) (2) Note that the size of the search area is the width of r image signals vertically and horizontally centering on the position of the image block of interest. Set to the range of. That is, mx and my are respectively -r≤mx≤
+ R, −r ≦ my ≦ + r.

The above-mentioned image block 3A of interest is compared with a certain reference image block 3B in the search area 7, and the difference between the respective signals is calculated and accumulated, and the result is shown in the following equation (3). Ms (i + mx, j + my) = Σ ^k-1 _{nx = 0} Σ ^k-1 _ny-0 ｜ Sf ((i + nx) + mx, (j + ny) + my) −Pf (i + nx , j + ny) | (3) In the search area 7, the reference image block 3B is shifted in the vertical and horizontal directions to obtain the cumulative absolute value of the differences, and the minimum value is obtained from these by the decision unit 9. When the minimum value is taken, the position of the reference image block 3B and the position of the target image block 3A are referred to, and the motion vector is obtained from the offsets of both.

Such a technique is described in the following documents, for example. Japanese Patent Application Laid-Open No. 3-110551 "Motion vector detection circuit" Japanese Patent Application Laid-Open No. 3-113571 "Vector correlation detection circuit" Japanese Patent Application Laid-Open No. 3-185575 "Motion vector detection device"

[0010]

The conventional motion vector detecting device as described above has the following problems to be solved. The attention image block as described above and a constant reference image block 3B in the search area 7 are set,
When accumulating the absolute values of these differences, for example, if the size of the image block of interest is k × k and the search region is larger by r in the front, rear, left, and right, the cumulative calculation of the absolute values of the differences is (2r + 1). ² × k ² times are required. The cumulative result of the absolute values obtained is (2r + 1) ² . It is necessary for the determining unit 9 to determine the minimum value of these.

However, such processing requires a very large amount of calculation, and the image signals required for the calculation are repeatedly read out, so that the number of times of access to each image signal becomes extremely large. Therefore, for example, the buffer memories 6A and 6B as shown in FIG.
It is preferable to provide a large number of circuits to increase the speed by parallelizing the circuits. However, for this purpose, the attention image block 3A
And a large number of buffer memories 6A and 6B for storing the image signals of the search area 7 are required. Therefore, it becomes necessary to provide a large number of difference absolute value accumulators 8 corresponding to these.

This requires a large-capacity memory for signal storage, and a large amount of hardware for accumulating the absolute value of the difference and the like. The present invention has been made with attention to the above points, and when signals are processed in parallel, without having duplicate data to be stored in the search area,
(EN) A motion vector detecting device that realizes high speed by performing parallel processing of absolute difference calculation by minimizing access to the same data in a reference area a plurality of times.

[0013]

According to the motion vector detecting apparatus of the present invention, a moving image at a time point when the image block having the smallest difference from the image block of interest forming a part of the moving image frame is different in the time axis direction. An image signal of the search area for detecting the position in the search area set in the frame to obtain a motion vector, and an image memory of the image area for storing the image signal of the image block of interest And a search area memory for storing the search area memory, and a difference absolute value accumulator for accumulating the absolute value of the difference between the input signals by the number equal to or less than the number of reference image blocks that can be taken in the line direction are arranged in parallel with respect to the search area. , The parallel-arranged absolute difference accumulators correspond to the respective reference image blocks continuous in the line direction of the search area, and receive the respective outputs of the difference absolute value accumulators. Image signal forming one line of the image block of interest, which has a minimum value determining unit that determines the minimum value and obtains a motion vector from the position information of the reference image block when the minimum value is indicated. One image signal is selected from among the image signals and is input to the difference absolute value accumulators all at once. From each reference image block of the search area corresponding to each difference absolute value accumulator, the same reference image block is selected. An image signal having a positional relationship is selected, input from each reference image block to the corresponding absolute value accumulator of the difference, the absolute value of the difference between the two is calculated, and then one line of the image block of interest is formed. From among the image signals to be selected, one image signal adjacent to the image signal selected immediately before is selected and input simultaneously, and the reference image blocks have the same positional relationship and are adjacent to the image signal selected immediately before. image Signal is input to the corresponding absolute value accumulator from each reference image block, the absolute value of the difference between the two is calculated, and the absolute value of the difference obtained immediately before is added, and the same processing is repeated. It is characterized in that a cumulative result of the absolute value of the difference is obtained.

[0014]

In this apparatus, the target image block is stored in the target image memory, the image signal of the search region is stored in the search region memory, and each line is extracted and shifted for comparison. As a result, an absolute value accumulator having a difference equal to or smaller than the number of reference image blocks that can be taken in the line direction with respect to the search area can obtain an accumulated value by comparison at a plurality of points at once. By repeating such processing, it is possible to sufficiently reduce the memory capacity for storing the image signals forming the image block of interest and the search area and execute the arithmetic processing for motion vector detection.

[0015]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of a motion vector detecting device of the present invention. This apparatus includes a target image memory 11 and a search area memory 12. The attention image memory 11 is a memory for storing the image signals forming the attention image block 3A already described with reference to FIG. 3, and the attention image block 3A is composed of a group of k × k square image signals. In this case, this memory capacity is also set to the extent that these image signals can be stored.

The search area memory 12 is a memory for storing the image signal of the search area 7 shown in FIG. 3, and its capacity is (k + 2) as in the case described with reference to FIG.
r) × (k + 2r). Also, a shift buffer 13 for storing an image signal for one line of the target image block read out from the target image memory 11
And a shift buffer 14 for storing the corresponding one-line image signal read from the search area memory 12. The shift buffer 14 for this search area
On the serial output side of the registers 15-1, 15-2, 15-3, ... 15- (2r + 1) in order from the farthest position.
Are connected in order. These registers are provided in the same number as the number of reference image blocks that can be taken in the line direction with respect to the search area, that is, 2r−1, which receive the image signals output from the shift buffer 14 and are adjacent to each other in order. It is configured to transfer the signals stored so far.

That is, the image signal for one line of the search area stored in the shift buffer 14 is stored in each of the registers 15-1 to 15-1.
When shifted in the 15- (2r + 1) direction, the leading image signal is input to the register 15- (2r + 1). Further, when the image signal for one line stored in the shift buffer 14 is shifted, the signal stored in the register 15- (2r + 1) is transferred to the register 15-2r,
Similarly, the signal can be sequentially transferred to the register 15-1. In addition, this device further includes a register 1
5-1 to 15- (2r + 1) are provided with absolute value accumulators 16-1 to 16- (2r + 1) having the same number of differences, and signals are respectively received from the corresponding registers 15-1 to 15- (2r + 1). Has become. Further, the absolute value accumulators 16-1 to 16- (2r + 1) of these differences collectively receive the image signal stored at the head from the shift buffer 13 storing one line of the image block of interest. Is configured.

Absolute difference value accumulators 16-1 to 16- (2r
The signal output by +1), that is, the accumulation result and the position information of each reference image block when the accumulation is performed are input to the minimum value determination unit 17. Minimum value determination unit 17
Are absolute value accumulators 16-1 to 16- (2r +
It is a circuit for receiving the input signal of 1), determining the minimum value of the cumulative result, and obtaining the position information of the reference image block corresponding to this.

4 and 5 are schematic operation explanatory diagrams of the apparatus of the present invention. The general operation of the device of the present invention will be described with reference to FIGS. First, all the image signals forming the attention image block for obtaining the motion vector are first stored in the attention image memory 11. At the same time, the search image memory 12 stores the image signal of the search area having the predetermined size, which includes the image signals around the target image block.

Then, first, the image signal for one line of the image block of interest is transferred to the shift buffer 13. Further, the image signal for one line corresponding to the search area is transferred to the shift buffer 14. Then, the image signals stored in the shift buffer 14 are sequentially transferred in the direction of the register 15-1 and the shift is repeated until the leading image signal is stored in the register 15-1. With the above-described preparation, the absolute difference value accumulators 16-1 to 16- (2r + 1) have the leading image signal stored in the shift buffer 13 and (2r + 1) from the beginning of the corresponding line in the search area. Each image signal is in a state of being input. In this state, the absolute value difference accumulators 16-1 to 16- (2r + 1) calculate the absolute value of the difference between the two types of input signals.

The process shown in step S1 of FIG. 4 shows this first process. For example, when r = 2 and k = 4,
The first image signal of the shift buffer 13 and the first to fifth image signals of the shift buffer 14 are compared with each other, and the absolute value of the difference is calculated. Next, the shift buffer 14 shifts the image signal further by one, whereby the first image signal stored in the register 15-1 disappears and the second image signal is stored in the register 15-1. It In addition, the image signal stored in the shift buffer 13 is also shifted by one, and the image signal stored secondly so far moves to the head of the shift buffer 13.

As a result, as shown in step S2 of FIG. 4, the second to sixth signals of the image signal initially stored in the shift buffer 14 and the image signal initially stored in the shift buffer 13 are stored. Is compared with the second signal, and the absolute value of the difference is calculated. Similarly, in step S3, the image signal stored in the shift buffer 14 is further shifted and input, and the shift buffer 1
The third image signal stored in No. 3 is input, and the absolute value of the difference is calculated. If one line of the image block of interest is composed of four image signals, step S in FIG.
When the last 4th image signal is compared with the 4th to 8th image signals stored in the shift buffer 14 and the absolute value of the difference is calculated by 4, the entire calculation on the line is completed. .

Thereafter, the image signal for the next one line adjacent to the image block of interest is stored in the shift buffer 13 from the image memory 11 of interest. In addition, the corresponding image signal for one line stored in the search area memory 12 is stored in the shift buffer 14. Then, the same processing as the first line is executed. In the case of the example shown in FIG. 4, the absolute value difference accumulators 16-1 to 16-5 accumulate the results each time the absolute value of the difference is obtained. If this process is repeated by the number of lines forming the image block of interest, that is, four times, five absolute value accumulation results of the differences are obtained from the outputs of the absolute value accumulators 16-1 to 16-5 of each difference.

When the size of the image block of interest is k × k and the search area is (k + 2r) × (k + 2r), the absolute value accumulators 16-1 to 16- (2r of the differences are subjected to the above processing.
+1) from the outputs 22-1 to 22-2 as shown in FIG.
The absolute value accumulation result of the difference at 22 (2r + 1) is obtained. For example, the leftmost state 22-1 shown in FIG. 5 shows the reference image block 21 obtained by the accumulation result of the absolute difference accumulator 16-1 shown in FIG. The reference image block 21 in this state exists at the upper left end of this search area. Then, the states 22-2, 22-3, ... 22- (2r + 1)
Sets a reference image block at the position where each image signal is shifted to the right by one and takes the difference.

Therefore, as a result of the above-described arithmetic processing, the differences from the k reference image blocks as shown in FIG. 5 can be obtained all at once. After that, by sequentially shifting one line of the image signal first extracted from the search area memory 12 shown in FIG. 1, reference image blocks are set in all parts of the search area, and a difference from the target image block is obtained. be able to. When the minimum value determination unit 17 determines the minimum value of the absolute value accumulation result of these differences, the offset between the corresponding reference image block and the target image block is determined as the motion vector.

FIG. 6 shows a connection diagram of a more specific embodiment of the device of the present invention. The device shown in FIG. 1 is specifically realized by the circuit configuration shown in this figure. That is, for example, each of the attention image memory 11 and the search area memory 12 is configured to be able to read four image signals at one time. Here, it is assumed that the image block of interest is composed of 16 × 16 image signals, and parallel processing is performed by arranging four sets of circuits as shown in the figure.

On the output side of the image memory 11 of interest, a shift buffer 13 having two shift registers 13A and 13B arranged in parallel is provided. This image signal 4
By alternately using the individual shift registers 13A and 13B, the reading of the image signal and the process of shifting and sending the image signal are simultaneously performed. The shift registers 13A and 13B that output the image signals while shifting them are selected by the selector 18, and one output of the shift registers 13A and 13B is the absolute value accumulator 1 of the four differences.
It is configured to input to 6-1 to 16-4.

On the other hand, the output of the search area memory 12 is also connected to the shift registers 14A and 14B which are connected in parallel to each other, and these constitute the shift buffer 14. Each of the shift registers 14A and 14B is for four image signals, and the image signals for one line in the search area are alternately stored in both, and while one stores the image signal, the other stores the image signal. It is configured to process transfer by shift.

When the image signals for one line are sequentially transferred, the selector 24-4 shifts the shift registers 14A, 1A.
4B is selected and the signal is sent out. The outputs of the search area memory 12 are connected in parallel so that they can be input to the registers 25-1 to 25-4, respectively, and during that time, signals input from adjacent registers and signals input from the search area memory 12 are connected. 24-1 to 24-2 for selecting any of
4-4 are arranged. The search area memory 12
And shift registers 14A and 14B and selector 24-1
To 24-4 are connected to the source data bus 19-1 to 19-4.
19-4.

Here, FIGS. 7 and 8 are explanatory views of the memory access method. FIG. 7 is a diagram showing the two-dimensional data of the target image block of the current frame, which is composed of the following 16 × 16 image signals. cb (0,0), cb (0,1), ..., cb (0,15), cb (1,0), cb (1,1), ..., cb (1,15), :: cb ( 15,0), cb (15,1), ..., cb (15,15)

On the other hand, FIG. 8 shows the search area 2 of the previous frame.
It is a figure showing dimension data, and is composed of the following 46 × 46 image signals. sb (0,0), sb (0,1), ..., sb (0,7), ..., sb (0,45), sb (1,0), sb (1,1), ..., sb ( 1,7), ..., sb (1,45), :: sb (7,0), sb (7,1), ..., sb (7,7), ..., sb (7,45), :: sb (45,0), sb (45,1), ..., sb (45,7), ..., sb (45,45)

In the diagram shown on the lower side of FIG. 7, four pixels arranged in the horizontal direction are read at a time while the image signal of the noted image block of the current frame is held in the buffer. In the diagram shown on the lower side of FIG. 8, four pixels arranged in the horizontal direction are similarly read at a time in the state where the pixel signals in the search area of the previous frame are held in the buffer. Here, one image signal is 8-bit data, and it is assumed that the memory is accessed in units of 32 bits / word including four data.

FIG. 9 shows a block diagram of the absolute value accumulator of the difference. Absolute value accumulators 16-1 to 16- shown in FIG.
(2r + 1) has, for example, a block configuration as shown in this figure. This circuit itself is known. That is, the difference absolute value accumulator shown in FIG.
Image signals to be compared are input to 1 and 32, position information of the reference image block in that case is obtained from the output terminal 33, and an absolute value accumulation result is obtained from the output terminal 34.

A subtractor 35, a sign inversion circuit 36, a selector 37, an adder 38, an absolute value accumulation register 39 and a position register 40 are provided here. Subtractor 3
Reference numeral 5 is a circuit for calculating the difference between two input signals, and the subtraction result is input to the selector 37 and the sign inverting circuit 36. The sign inversion circuit 36 inverts the sign of the subtraction result and inputs it to the selector 37. The subtracter 35 determines whether the result is positive or negative when the subtraction is performed, and sends the determination result to the selector 37. As a result, the well-known absolute value of the difference between the digital signals is selected and output from the selector 37. Then, in the adder 38, addition with the contents of the absolute value accumulation register 39 which has already been calculated and accumulated is performed. As a result, the cumulative value is stored in the absolute value cumulative register 39 for each calculation process. The position register 40 stores the position information of the reference image block in that case.

FIG. 10 shows a block diagram of the main part of the minimum value judgment unit. This circuit sequentially compares the absolute values of the four types of differences input to the input terminals 51 to 54, stores the smallest value in the minimum value register 73, and further obtains the position information of the corresponding reference image block. It is configured to be stored in the position register 74 and output from the output terminal 59. This circuit includes four subtractors 61-64 and eight comparators 6
5 to 72, the minimum value register 73 and the position register 74 described above are provided.

For example, the subtractor 62 has input terminals 51 and 52.
It is determined whether the result is positive or negative by subtracting the other from one of the absolute value accumulation results of the difference input from, and the determination result is output to the selectors 65 and 66. Selector 66
Two kinds of cumulative results which are the objects of comparison are input to the subtracter 62, and a smaller cumulative result is output by the subtractor 62.
Is output in the direction of. Further, the position information of each reference image block to be compared is input to the selector 65 from the input terminals 55 and 56, and the smaller accumulated result is output to the selector 69. The subtractor 61 and the two selectors 67 and 68 perform exactly the same processing, and the subtractor 63
And the two selectors 69 and 70 also perform the same processing.

With these, the input terminals 51, 52, 5
The smallest of the absolute value accumulation results of the differences input from 3 and 54 is input to the subtracter 64 and the selector 72. Further, these also perform the same processing and output the smallest one to the minimum value register 73 and the position register 74. Through such processing, the minimum value determination unit outputs necessary position information.

The above-structured apparatus shown in FIG. 6 specifically operates as follows. First, the search area memories 12 to 4
The two image signals sb (0,0), sb (0,1), sb (0,2), sb (0,3) are read out and are directly selected from the selectors 24-1 to 24-1 through the source data paths 19-1 to 19-4. Enter it in 24-4. These selectors select the data from the source data paths 19-1 to 19-4 and hold them in the registers 25-1 to 25-4. Then, the following four image signals sb (0,4), sb (0,5), sb (0,6), sb (0,7) are read from the search area memory 12 and the source data path 19- Input to the shift register 14A through 1 to 19-4.

On the other hand, four image signals cb (0,0), cb (0,1), cb (0,2), cb (0,3) are read from the image memory 11 of interest,
Input to the shift register 13A. In this state, the outputs of the registers 25-1 to 25-4 are set to the difference absolute value accumulator 16-
1 to 16-4 and at the same time the shift register 13
A is shifted, and the leading image signal cb (0,0) is passed through the selector 18 to the absolute value accumulators 16-1 to 16-4 of the respective differences.
To enter. Thus, the absolute value of the first difference is accumulated. The cumulative calculation of the absolute value of the difference performed in this state is as follows. In the absolute difference accumulator 16-1, | sb
(0,0) −cb (0,0) |
-2, | sb (0,1) -cb (0,0) | is accumulated, and in the accumulator 16-3 of the absolute value of the difference, | sb (0,2) -cb (0,0) | And the absolute value of the difference accumulator 16-4 is | sb (0,3) −.
cb (0,0) | is accumulated.

Next, the head signal of the shift register 14A is transferred to the register 25-4, the signal of the register 25-4 is transferred to the register 25-3, and the signal of the register 25-3 is transferred to the register 25-2. Then, the signal of the register 25-2 is transferred to the register 25-1 to shift by one image signal. As a result, the absolute difference accumulators 16-1 to 16-4 perform the following calculation. In the accumulator 16-1 of the absolute value of the difference, | sb (0,0) −cb (0,0) | +
| Sb (0,1) -cb (0,1) | is accumulated, and in the accumulator 16-2 of the absolute value of the difference, | sb (0,1) -cb (0,0) | + | sb ( 0,2) −
cb (0,1) | is accumulated, and in the absolute value accumulator 16-3, | sb (0,2) −cb (0,0) | + | sb (0,3) −cb (0 , 1) ｜
And the absolute value accumulator 16-4 of the difference is | sb (0,
3) -cb (0,0) | + | sb (0,4) -cb (0,1) | is accumulated.

Thereafter, similarly, the image signals are sequentially transferred by the shift register 14A and the registers 25-1 to 25-4, each one is shifted, and the difference absolute value accumulator 16 is provided.
Enter in -1 to 16-4. Further, in this case, the image signal of the shift register 13A is also shifted by one.

While the above processing is repeated and all the image signals are sequentially sent out from the shift register 14A, four pixels sb (0,8), sb (0,9), sb are searched from the search area memory 12.
(0,10), sb (0,11) are read and source data path 19-
Stored in the shift register 14B through 1 to 19-4. Further, while outputting all the data in the shift register 13A while sequentially shifting the data, the target image memories 11 to
The two pixels cb (0,4), cb (0,5), cb (0,6), cb (0,7) are read out and input to the shift register 13B. When all the data of the shift register 14A is output, the selector 24-4 selects the shift register 14B, and the shift register 13A
When all the data of (3) are output, the selector 18 selects the output of the shift register 13B.

When the output of all the image signals from the shift register 13A is completed, the absolute value difference accumulator 16-1 has the following formula: | sb (0,0) -cb (0,0) | + | sb (0,1 ) − Cb (0,1) ｜ + ｜ sb (0,2) − cb (0,2) ｜ + ｜ sb (0,3) − cb (0,3) ｜ + ｜ sb (0,4) − cb (0,4) | is accumulated, and in the absolute value accumulator 16-2, | sb (0,1) −cb (0,0) | + | sb (0,2) −cb (0 , 1) | + | sb (0,3) -cb (0,2) | + | sb (0,4) -cb (0,3) | + | sb (0,5) -cb (0,4) ) | And the accumulator 16-3 for the absolute value of the difference calculates | sb (0,2) − cb (0,0) | + | sb (0,3) − cb (0,1) | Accumulate | sb (0,4) − cb (0,2) ｜ + | sb (0,5) − cb (0,3) ｜ + | sb (0,6) − cb (0,4) | , Sb (0,3) −cb (0,0) | + | sb (0,4) −cb (0,1) | + | sb (0, 5) -cb (0,2) | + | sb (0,6) -cb (0,3) | + | sb (0,7) -cb (0,4) | are accumulated.

Subsequently, the calculation is advanced, and four pixels sb (0,16), sb (0,17), sb (0,18), sb (0,19) are searched from the search area memory 12.
Is read and input to the shift register 14B through the source data paths 19-1 to 19-4. In addition, four pixels cb (0,12), cb (0,13), cb (0,1) from the image memory 11 of interest.
4) and cb (0,15) are read and input to the shift register 13B. All of these data are accumulated in the absolute value of the difference 16-
1-16-4 are input and accumulated, the accumulated absolute value of the difference is obtained for the first line of the four portions corresponding to the target image block in the search area. The results are as follows. In the accumulator 16-1 of the absolute value of the difference, | sb (0,0) −cb (0,0) | + | sb (0,1) −cb (0,1) | + | sb (0,2 ) − Cb (0,2) ｜ ＋ ｜ sb (0,3) − cb (0,3) ｜ ＋ ｜ sb (0,4) − cb (0,4) ｜ ＋ ｜ sb (0,5) − cb (0,5) | + | sb (0,6) -cb (0,6) | + | sb (0,7) -cb (0,7) | + | sb (0,8) -cb ( 0,8) | + | sb (0,9) -cb (0,9) | + | sb (0,10) -cb (0,10) | + | sb (0,11) -cb (0, 11) | + | sb (0,12) -cb (0,12) | + | sb (0,13) -cb (0,13) | + | sb (0,14) -cb (0,14) |||| b (0,15) -cb (0,15) | is accumulated, and in the accumulator 16-2 of the absolute value of the difference, | sb (0,1) -cb (0,0) | + | sb (0,2) -cb (0,1) | + | sb (0,3) -cb (0,2) | + | sb (0,4) -cb (0,3) | + | sb ( 0,5) -cb (0,4) | + | sb (0,6) -cb (0,5) | + | sb (0,7) -cb (0,6) | + | sb (0, 8) -cb (0,7) | + | sb (0,9) -cb (0,8) | + | sb (0,10) -cb (0,9) | + | sb (0,11) -Cb (0,10) | + | sb (0,12) -cb (0,11) | + | sb (0,13) -cb (0,12) | + | sb (0,14) -cb (0,13) ｜ ＋ ｜ sb (0,15) −cb (0,1 4) | + | sb (0,16) -cb (0,15) | is accumulated, and in the accumulator 16-3 of the absolute value of the difference, | sb (0,2) -cb (0,0) | + | Sb (0,3) -cb (0,1) | + | sb (0,4) -cb (0,2) | + | sb (0,5) -cb (0,3) | + | sb (0,6) − cb (0,4) | + | sb (0,7) − cb (0,5) | + | sb (0,8) − cb (0,6) | + | sb ( 0,9) -cb (0,7) | + | sb (0,10)-cb (0,8) | + | sb (0,11)-cb (0,9) | + | sb (0, 12) -cb (0,10) | + | sb (0,13) -cb (0,11) | + | sb (0,14) -cb (0,12) | + | sb (0,15) -Cb (0,13) | + | sb (0,16) -cb (0,14) | + | sb (0,17) -cb (0,15) | is accumulated, and the absolute value of the difference is accumulated. In the instrument 16-4, | sb (0,3) −cb (0,0) | + | sb (0,4) −cb (0,1) | + | sb (0,5) −cb (0, 2) | + | sb (0,6) -cb (0,3) | + | sb (0,7) -cb (0,4) | + | sb (0,8) -cb (0,5) ｜ ＋ ｜ sb (0,9) − cb (0,6) ｜ ＋ ｜ sb (0,10) − cb (0,7) ｜ ＋ ｜ sb (0,11) − cb (0,8) ｜ ＋ ｜ sb (0,12) − cb (0,9) ｜ ＋ ｜ sb (0,13) −cb (0,10) ｜ ＋ ｜ sb (0,14) −cb (0,11) ｜ ＋ ｜ sb (0,15) −cb (0,12) ｜ Accumulate | sb (0,16) -cb (0,13) | + | sb (0,17) -cb (0,14) | + | sb (0,18) -cb (0,15) | ..

By processing the remaining 15 lines in the same manner, the accumulated absolute value of the differences for the four portions corresponding to the target image block in the search area can be obtained.
The result is input to the minimum value determination unit 17. The minimum value determination unit operates in the manner described above with reference to FIG. 10, and finally obtains the required motion vector.

The present invention is not limited to the above embodiments. In the device as described above, while performing the arithmetic processing on the current image block currently being processed, the current image block adjacent to the current image block is read into the new image memory of interest and corresponds to the newly read image block of interest. In the search area, the image data of the portion that does not currently exist in the search area memory is sequentially read into the search area memory, so that the calculation processing for the adjacent image block of interest can be started immediately after the current processing is completed.

In order to further speed up the above arithmetic processing, a group of absolute difference accumulators corresponding to a plurality of reference image blocks which can be taken in the line direction as shown in FIG. 4 is provided for a plurality of lines. May be. That is, the absolute value accumulator groups provided for a plurality of lines may be used to execute the calculations for a plurality of reference image blocks adjacent in the two-dimensional direction in parallel.

In the present embodiment, the maximum number of reference image blocks that can be taken in the line direction with respect to the search area is set as the maximum number of absolute value difference accumulators and registers for supplying signals to these. However, any number less than that may be selected. In the case of this embodiment, if the number of reference image blocks that can be taken in the line direction with respect to the search area is the same, parallelization can be most efficiently performed. As a matter of course, various well-known circuit configurations can be adopted for the circuit that accumulates the absolute value of the difference and the circuit that determines the minimum value of the accumulated value.

[0049]

The motion vector detecting apparatus of the present invention described above stores the image signal of the image block of interest in the image memory of interest, stores the image signal of the search area in the memory of the search area, and responds to each of these. An image signal for one line is obtained, and the image signals are input in parallel in a predetermined order to the absolute value difference accumulators whose number is equal to or less than the number of reference image blocks that can be taken in the line direction with respect to the search area. By doing so, a large number of cumulative results are obtained all at once, and the minimum value is determined.Therefore, the absolute value accumulation of differences can be executed in parallel without holding a large amount of image signals in the input image block search area in the device. , Storage capacity can be saved. Further, the number of times of accessing the image signal necessary to obtain a plurality of difference absolute value accumulation results can be minimized, and the processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a motion vector detecting device of the present invention.

FIG. 2 is an explanatory diagram of the contents of a motion vector.

FIG. 3 is a block diagram of a general motion vector detection circuit.

FIG. 4 is an operation explanatory diagram (1) of the apparatus of the present invention.

FIG. 5 is a schematic operation explanatory view (No. 2) of the device of the present invention.

FIG. 6 is a specific connection diagram of the device of the present invention.

FIG. 7 is an explanatory diagram of an access method of a search area memory.

FIG. 8 is an explanatory diagram of an access method of a target image memory.

FIG. 9 is a block diagram of a difference absolute value accumulator.

FIG. 10 is a block diagram of main parts of a minimum value determination unit.

[Explanation of symbols]

 11 Image of Interest Memory 12 Search Area Memory 13 and 14 Shift Buffer 15-1 to 15- (2r + 1) Register 16-1 to 16- (2r + 1) Absolute Value Accumulator of Difference 17 Minimum Value Determination Unit

Claims (1)

[Claims] 1. A position in a search area set in a moving image frame at a different time point in the time axis direction, where the image block having the smallest difference from the image block of interest forming a part of the moving image frame is located. A target image memory that stores an image signal of the target image block; a search area memory that stores an image signal of the search area; and a line of the search area. A number of reference image blocks equal to or less than the number of reference image blocks that can be taken in a direction, and a difference absolute value accumulator for accumulating the absolute value of the difference between the input signals; and an output of each of the difference absolute value accumulators. , A minimum value determination unit that determines the minimum value thereof and obtains a motion vector from the position information of the reference image block when the minimum value is indicated, and the absolute value accumulator of the difference is One image signal is selected from the image signals forming one line of the eye image block and is received all at once, and the same number of continuous image signals as the reference image block is received from the corresponding one line of the search area. Each of them is accepted, the absolute value of the difference between the two is calculated, and then one image signal adjacent to the image signal selected immediately before is selected from among the image signals forming one line of the image block of interest to perform simultaneous operation. In addition, the continuous image signals shifted by one line direction from the image signal received immediately before are respectively received from the corresponding one line of the search area, and the absolute value of the difference between them is calculated, and immediately before A motion vector detecting device characterized by adding to the obtained absolute value of the difference and repeating the same processing to obtain a cumulative result of the absolute value of the difference.