JPH07200815A - Image processor - Google Patents

Abstract

PURPOSE:To provide an image processor which can eliminate in reel time the block distortions of the compressed image data and never deteriorates the picture quality improvement effect despite its simplified constitution. CONSTITUTION:The reading operation of a data register 3 is controlled by the output timing of an adverse DCT converter 2. A subtractor 5 performs the subtrection between the output of the register 3 and that of the converter 2 to acquire the difference of data. A comparator 9 compares the output of the subtractor 5 with that of a register a which holds the threshold data that are used for control of the noise eliminating level received from a CPU 7. Then, it is decided whether the block noises should be eliminated or not based on the output of the comparator 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which is applied to a digital VTR, a digital camera or the like and which carries out compression / expansion processing on digital image data.

[0002]

2. Description of the Related Art Conventionally, in order to process digital image data in real time, many line memories (8 lines or more) have been required.

According to the image processing method disclosed in Japanese Patent Application Laid-Open No. 4-209073, the linearity of the difference data is determined by judging from the difference between the image data of one processed block and the adjacent blocks at the four corners. Block distortion is removed by interpolation to prevent image quality deterioration.

[0004]

However, in the case of the above-mentioned conventional method, it is necessary to obtain the difference between the image data from the upper, lower, left, and right blocks in order to obtain the difference between the blocks. Therefore, many line memories or frames are required. I needed memory. Therefore, there is a problem that the hardware configuration becomes large.

It is an object of the present invention to remove block distortion in real time from image compressed image data regardless of whether it is a still image or a moving image. An object of the present invention is to provide an image processing apparatus which has a merit in integrating circuits so that the effect of improving the image quality after simplifying the ware structure is not deteriorated.

[0006]

In order to achieve the above object, the present invention provides an image processing apparatus for compressing and expanding image data by using digital signal processing, in which an image of m × m (m is a positive integer) An image inverse conversion circuit that performs conversion processing using data as one block, a data register that stores only predetermined pixel data in the peripheral portion of the block of the block data output from the image inverse conversion circuit, and this data register A register control circuit for controlling reading and writing of
The size of the data between the subtracter that subtracts the output of the image inverse conversion circuit and the output of the data register and the register that holds the data for adjusting the noise removal level from the arithmetic processing circuit and the output of the subtractor , A coefficient multiplier for multiplying the output of the subtractor by a predetermined coefficient by an address in the block, a switching circuit for switching the output of the coefficient multiplier by the output of the comparator, and the coefficient multiplication Block adder for adding the output of the converter and the output of the image inverse conversion circuit, and a block raster conversion circuit for converting the block data output from the adder to raster data, and block noise generated by image compression / expansion Is removed.

Further, a line memory and a line memory control circuit are provided instead of the data register.

Further, a block memory and a block memory control circuit in the image inverse conversion circuit are provided instead of the data register.

Further, the coefficient of the multiplier is calculated by inputting the data calculated by the arithmetic processing circuit from the expansion parameter of the image inverse conversion circuit to the coefficient register and calculating the coefficient multiplier by the output of the coefficient register. It is characterized by changing the coefficient.

Further, a horizontal low-pass filter which operates every m pixels is arranged after the output of the block raster conversion circuit.

Further, a vertical low-pass filter which operates every m lines is arranged after the horizontal low-pass filter.

[0012]

In the image processing apparatus having the above-described configuration, the image data for noise removal is retained by using the image data of the block preceding the time block of the own block, so that the noise removal process is performed in real time (real time). ) Is processed. Moreover, since the required number of data is held in the data register, a large memory capacity is not required and the hardware can be achieved with a small configuration.

By sharing the data register required for block noise removal by using the 1H line memory required for camera signal processing, no data register is required and the hardware configuration is simplified.

By sharing the block memory in the inverse conversion circuit with the data register, the hardware configuration is simplified.

Further, since the coefficient of linear interpolation can be adaptively changed by the parameter of image compression, the effect of noise removal is enhanced without imposing a burden on the hardware.

Since the low-pass filter (LPF) is further applied after the block noise is removed, the effect of removing the noise is great. Particularly, in the case of the color difference signal, the output of the color difference signal is color-modulated as a composite video signal due to the influence of the block noise. When output, dot interference that adversely affects image quality can be suppressed.

Further, after removing the block noise,
Since the LPF is applied in the vertical direction, the effect of noise removal is great, and especially when the color difference signal output is color-modulated and output as a reproduced composite video signal due to the influence of block noise in the case of a color difference signal, the image quality is adversely affected. Occurrence of dot interference that gives a line is suppressed, and the line memory for camera signal processing is shared as the line memory for the LPF in the vertical direction, so that the load on the hardware is reduced.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, in which 1 is a Huffman decoding circuit and 2 is m × m.
An image inverse conversion circuit (inverse DCT converter) for performing conversion processing on the image data of (m is a positive integer) as one block, 3 is a peripheral part of the block of the block data output from the inverse DCT converter 2. A data register for storing only predetermined pixel data of 4, a register control circuit for controlling reading and writing of the data register 3, a subtracter 5 for subtracting an output of the inverse DCT converter 2 and an output of the data register 3, and a reference numeral 9 A comparator that compares the output of the subtracter 5 and the size of the data with the register 8 that holds the data for adjusting the noise removal level from the arithmetic processing circuit (CPU) 7, and 6 is the block of the output of the subtractor 5. Coefficient multiplier for multiplying a predetermined coefficient by an address in the switch, 10 is a switching circuit for switching the output of the coefficient multiplier 6 by the output of the comparator 9, 11 is the output of the coefficient multiplier 6 and the inverse DCT transform An adder for adding the output of the converter 2 and a block raster conversion circuit 12 for converting the block data output from the adder 11 into raster data.

In FIG. 1, the compressed image data is
In this case, it is processed by the Huffman decoding circuit 1 and the next 8 ×
Inverse D for processing 8 image data as one block
The output data of the CT converter 2 is stored in the data register 3 which stores only predetermined data of the block.
It is recorded under the control of the register control circuit 4 that controls the reading and writing of data.

Here, the reading of the data register 3 is controlled by the output timing of the inverse DCT converter 2, and the output of the data register 3 and the output of the inverse DCT converter 2 are subtracted by the subtractor 5.
Take the difference of the data. The output of the subtractor 5 and the register 8 holding the threshold data for adjusting the noise removal level from the CPU 7 are compared by a comparator 9 for comparing the size of each data, and this comparison is performed. Whether or not to remove block noise is determined by the output of the container 9.

Regarding the coefficient multiplier 6, in the case of this embodiment, the coefficient is 1/16 to 7/16, etc., and multiplication of the coefficient can be achieved by a bit shift and an adder instead of using a multiplier (multiplier). Therefore, there is an advantage that the hardware configuration can be simplified.

Here, the output of the coefficient multiplier 6 is used as the comparator 9
The switching circuit 10 that switches according to the determination result that is the output of outputs the noise removal or not. When performing noise removal, the output of the coefficient multiplier 6 and the output of the inverse DCT converter 2 are added by the adder 11. As a result of the block data from which block noise is removed, this adder
The output from the adder 11 is output from the adder 11 through a block raster conversion circuit 12 that converts block data into raster data, and reproduced image data is output as raster data.

Next, removal of block distortion will be described using specific numerical values as an example.

Here, the data actually recorded in the data register are as follows (Pnn is the coordinates in block units, and the coordinates in () are the coordinates). That is, paying attention to the image Pnn (0,0) on the upper left of the block, the pixel Pnn− above the pixel
The correction value in the block is obtained from the three pixels of 1 (0,7) and Pn-1n (7,0) on the left side.

The correction method is such that the difference data between the pixels at the right and upper corners is held in a register, and this difference data is linearly interpolated in the horizontal and vertical directions. In this case, the coefficient for the linear interpolation of the multiplier 6 is (8-n) / 16
(n: 1-8).

For example, when the image data of a certain block and its periphery are as shown in (Table 1),

[0028]

[Table 1]

128 {pixels Pn-1n (7,0)}-145 {pixels Pnn (0,0)} =
Difference data "-17" is obtained in the horizontal direction as -17 {difference data}.

156 {pixel Pnn-1 (0,7)}-145 {pixel Pnn (0,0)} =
As 11 {difference data}, for a pixel in a block of n rows and m columns, -17 (8
-N) / 16 times and 11 (8-m) / 16 times are two-dimensionally added to the pixel data of the block as linear interpolation data. This improves block distortion between blocks (here, 128 and 156 are stored in the data register 3).

Actually, there is a method of storing not only two pieces of data but also a maximum of five pieces of data as shown in FIG. 7 in the data register 3.

Further, as the image data for obtaining the difference,
In addition to the method described above, the pixel data of interest in the block can be converted into {pixel Pnn (0,0)}, {pixel Pnn (7,
0)} and {pixel Pnn (0,7)}.

As another method for the interpolation coefficient,
There are (8-n) / 8, n / 16, n / 8, etc., and the degree of noise removal can be adjusted.

FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention. In the case of a digital still video camera for compressing image data, a camera signal processing circuit 20 is provided in addition to the image compression / expansion circuit. In the second embodiment, the first
Inside this camera signal processing circuit 20 different from the embodiment, there is a line memory 21 for aperture correction of a luminance signal.

The line memory 21 includes an inverse DCT converter 2
It is used in place of the data register 3 for holding the output of, and reads and writes predetermined image data under the control of the memory control circuit 22 which controls the line memory 21.

FIG. 3 is a block diagram showing the configuration of the third embodiment of the present invention. Explaining only the difference from the first embodiment, the output of the inverse DCT converter 26 inside the inverse DCT converter 2 is directly output. The block memory 24 for outputting and outputting the block data in the internal processing holds the image data instead of the data register 3.

The block memory 24 is controlled by the block memory control circuit 25. At this time, the timing of the output data of the inverse DCT converter is different from that of the first and second embodiments, and the block raster conversion circuit 12 for converting the block data of this different timing into the raster data is the first and the second. Processing is performed in a sequence different from that of the second embodiment, and the sequence of raster data as a final reproduced image signal is combined.

FIG. 4 is a block diagram of the essential parts showing the configuration of the fourth embodiment of the present invention. Explaining only the difference from the first embodiment, the data set by the CPU 7 is the coefficient register.
Recorded in 31. The coefficient register 31 is composed of 64 pieces of data corresponding to the number of pixels in the block. The coefficient, the subtracter 5 and the output are multiplied by the coefficient multiplier 32, and the multiplication result data is passed through the switching circuit 10. Add to adder 11. Here, the coefficient multiplier 32 is composed of a multiplier for multiplying the coefficient from the CPU 7.

FIG. 5 is a block diagram showing the configuration of the fifth embodiment of the present invention. The difference from the first embodiment is that the reproduced image data converted into raster data by the block raster conversion circuit 12 is the horizontal LPF 41. It has a configuration in which it is output through the vertical LPF 42.

FIG. 6 is a block diagram showing an example of the vertical LPF. In this example, a vertical LPF is achieved by using two line memories 51 and 52 and an adder 53 inside the camera processing circuit. is doing. In the horizontal direction, the LPF can be configured by a delay circuit such as a latch circuit.
Whether or not to process this at block boundaries is controlled by a switching circuit 54 that controls every m pixels in the horizontal case and every m lines in the vertical case (every 8 lines in this example). It is a thing.

[0041]

As described above, according to the first aspect of the present invention, the image processing apparatus according to the first aspect of the invention retains the image data for noise removal in the block preceding the block in time. Since it is removed using the image data of, noise removal processing can be performed in real time (real time). Further, since the required number of data is held in the data register, it can be achieved with a configuration having a large memory capacity and a small hardware.

According to the second aspect of the invention, the data register required for block noise removal is shared by using the 1H line memory required for camera signal processing, so that the data register is not particularly required. , The hardware configuration becomes simple.

According to the third aspect of the invention, since the block memory in the inverse conversion circuit is shared with the data register, the hardware configuration is simplified.

According to the invention described in claim 4, since the coefficient of linear interpolation can be adaptively changed by the parameter of image compression, the effect of noise removal can be enhanced without imposing a burden on the hardware. .

According to the fifth aspect of the present invention, since the LPF is further applied after the block noise is removed, the effect of removing the noise is great. Particularly, in the case of the color difference signal, the output of the color difference signal is color-modulated by the influence of the block noise. Then, when output as a reproduced composite video signal, the occurrence of dot interference that adversely affects the image quality can be suppressed.

According to the sixth aspect of the present invention, since the LPF is further applied in the horizontal and vertical directions after the block noise is removed, the effect of removing the noise is large, and the color difference is particularly affected by the block noise in the case of the color difference signal. When the signal output is color-modulated and output as a reproduced composite video signal, dot interference that adversely affects the image quality can be suppressed. Further, by sharing the line memory for camera signal processing as the line memory for the LPF in the vertical direction, the load on the hardware is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an image processing apparatus of the present invention.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the image processing apparatus of the present invention.

FIG. 3 is a block diagram showing the configuration of a third embodiment of the image processing apparatus of the present invention.

FIG. 4 is a block diagram of a main part showing a configuration of a fourth embodiment of the image processing apparatus of the present invention.

FIG. 5 is a block diagram showing the configuration of a fifth embodiment of the image processing apparatus of the present invention.

FIG. 6 is a block diagram showing an example of a vertical LPF.

FIG. 7 is an explanatory diagram of pixels stored in a data register.

[Explanation of symbols]

1 ... Huffman decoding circuit, 2, 26 ... Image inverse conversion circuit
(Inverse DCT converter), 3 ... Data register, 4 ... Register control circuit, 5 ... Subtractor, 6,32 ... Coefficient multiplier,
7 ... CPU, 8 ... Register, 9 ... Comparator, 10 ...
Switching circuit, 11 ... Adder, 12 ... Block raster conversion circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 1/41 B 7/30 H04N 7/133 Z

Claims (6)

[Claims] 1. An image processing device for compressing and expanding image data using digital signal processing, and an image inverse conversion circuit for performing conversion processing on m × m (m is a positive integer) image data as one block. A data register for storing only predetermined pixel data in the peripheral portion of the block out of the block data output from the image inverse conversion circuit, and a register control circuit for controlling reading and writing of the data register,
The size of the data between the subtracter that subtracts the output of the image inverse conversion circuit and the output of the data register and the register that holds the data for adjusting the noise removal level from the arithmetic processing circuit and the output of the subtractor , A coefficient multiplier for multiplying the output of the subtractor by a predetermined coefficient by an address in the block, a switching circuit for switching the output of the coefficient multiplier by the output of the comparator, and the coefficient multiplication Block adder for adding the output of the converter and the output of the image inverse conversion circuit, and a block raster conversion circuit for converting the block data output from the adder to raster data, and block noise generated by image compression / expansion An image processing device characterized by removing the. 2. The image processing apparatus according to claim 1, further comprising a line memory and a line memory control circuit instead of the data register. 3. The image processing apparatus according to claim 1, further comprising a block memory in the image inverse conversion circuit and a block memory control circuit instead of the data register. 4. The coefficient of the multiplier is input to the coefficient register with the data calculated by the arithmetic processing circuit from the decompression parameter of the image inverse conversion circuit, and the coefficient multiplier outputs the coefficient by the output of the coefficient register. The image processing apparatus according to claim 1, wherein the operation coefficient is changed. 5. The image processing apparatus according to claim 1, further comprising a horizontal low-pass filter that operates every m pixels after the output of the block raster conversion circuit. 6. The image processing apparatus according to claim 5, further comprising a vertical low-pass filter that operates every m lines after the horizontal low-pass filter.