JPH07200808A - Image rotation processor - Google Patents

Abstract

PURPOSE:To shorten the processing time and also to reduce the cost of an image rotation processor by scanning obliquely e memory storing an original image to read out the pixel data and writing horizontally the read pixel date into into a result memory to obtain a rotated original image. CONSTITUTION:An image rotation processor reeds out obliquely an original image and sends it to e horizontal magnifying part. The pixels ere horizontally interpolated at the horizontal magnifying part. The pixel data outputted from the horizontal magnifying part are sent to e vertical magnifying part where the pixels are vertically interpolated. Then, the pixel data outputted from the vertical magnifying part are horizontally written into a result memory. The pixel A1, A2, A3... A7 are successively and obliquely read out of an original image memory. The reading pattern of the image data is Previously decided according to the image rotational. angle. The number of read Pixels obtained when the pixel data ere obliquely read is decreased in comparison with that obtained when the pixel date are horizontally read.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image rotation processing device for performing character recognition, shape inspection, etc. using an image captured by a video camera or the like.

[0002]

2. Description of the Related Art In character recognition, shape inspection, etc., a reference image serving as a reference is compared with an input image one pixel at a time, and if the proportion of matching pixels is equal to or more than a specified percentage, it is regarded as a pass. . Such character recognition, character recognition,
When a shape inspection or the like is performed, there is no problem if the rotation angles of the reference image and the input image are the same, but if the rotation angles of both images are different, the images will be rejected even if they have the same shape.
Therefore, when the rotation angles of both images are deviated, one of the images is rotated by performing a complicated calculation generally called affine transformation. The affine transformation is expressed by the following matrix.

[0003]

[Equation 1]

In the above formula 1, (x, y) is the original image input coordinate and (X, Y) is the output coordinate. e and f represent the movement of the coordinate origin. If b = c = 0, it simply means enlargement or reduction. Also, a = d = kcos θ, c = −b = k sin θ
Then represents rotation of θ and expansion of k times.

[0005]

If the image is rotated using such an affine transformation as it is, the amount of calculation becomes enormous and the processing time becomes slow. In addition, there is a problem that the circuit becomes complicated and expensive when trying to realize the affine transformation at high speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image rotation processing device which can shorten the processing time and can be manufactured at low cost.

[0007]

A first image rotation processing device according to the present invention comprises means for reading pixel data by obliquely scanning an original image memory storing original images, and means for reading the read pixel data. A means for writing in the result memory in the horizontal direction is provided.

A second image rotation processing apparatus according to the present invention is a means for scanning an original image memory storing an original image in an oblique direction to read out pixel data, a horizontal direction interpolation process for the read pixel data, and a vertical direction. It is characterized by comprising an interpolating means for adding the number of pixel data in the horizontal and vertical directions by performing the interpolation processing, and a means for writing the pixel data interpolated by the interpolating means in the horizontal direction in the result memory. .

[0009]

In the first image rotation processing device according to the present invention,
The original image memory in which the original image is stored is scanned diagonally and pixel data is read out. Then, the read pixel data is written in the result memory in the horizontal direction. As a result, a rotated image of the original image is obtained.

In the second image rotation processing apparatus according to the present invention, the original image memory in which the original image is stored is scanned diagonally and pixel data is read out. Reading in the diagonal direction results in reading coarser than reading in the horizontal direction, and the number of pixel data is reduced. Therefore, the number of pieces of pixel data in the horizontal and vertical directions is increased by subjecting the read pixel data to horizontal interpolation processing and vertical interpolation processing. The pixel data after this interpolation is written in the result memory in the horizontal direction. As a result, a rotated image of the original image is obtained.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall construction of the image rotation processing device. FIG. 2 shows an original image and an image after being rotated by the image rotation processing device. FIG. 2 shows an example in which a rectangular area having 8 pixels horizontally and 6 pixels vertically is rotated by 30 °.

In the image rotation processing device, the original image is read out obliquely and sent to the horizontal enlargement unit. In the horizontal expansion section,
Pixels are interpolated in the horizontal direction. The pixel data output from the horizontal enlargement unit is sent to the vertical enlargement unit. In the vertical expansion unit, pixels are interpolated in the vertical direction. The pixel data output from the vertical enlargement unit is written in the result memory in the horizontal direction.

Explaining with reference to FIG. 2, first, pixel data is read from the original image memory in an oblique direction in the order of A1, A2, A3 ... A7. The read pattern of the image data is predetermined according to the image rotation angle. When the pixel data is read in the diagonal direction, the number of read pixels is smaller than that in the case where an image of the same size is read in the horizontal direction.
In this example, since the rotation is 30 °, one pixel has cos30.
= 0.866 pixels, which is reduced by 0.134 pixels per pixel. Therefore, when the accumulation of the reduced pixels becomes 0.5 pixels or more, the average value of the data of the pixels before and after is inserted, so that the pixels in the horizontal direction are interpolated.

In the example of FIG. 2, 0.5 / 0.134 =
At 3.73, the cumulative number of pixels reduced at the 4th pixel becomes 0.5 pixels or more, and one pixel is inserted at the 5th pixel. Therefore, the first pixel is A1, the second pixel is A2, the third pixel is A3, the fourth pixel is A4, and the average value of the previous pixel A4 and the next pixel A5 at the fifth pixel {(A4 + A5) /
2} is added. The same is true in the vertical direction, and the average value of the D and E lines, which are the horizontal lines before and after the fifth horizontal line, is added.

The horizontal enlargement portion and the vertical enlargement portion will be described in detail below. In the following, an image rotation processing device having 512 pixels in the horizontal direction and 512 pixels in the vertical direction with 1 pixel 8-bit data will be described. Needless to say.

FIG. 3 shows the structure of the horizontal enlargement section. FIG. 4 shows signals of the respective parts of FIG. In the memory 6,
Data indicating which pixel the pixel is to be interpolated is stored for each rotation angle (rotation angle) of the image. This data is created in advance within the range of rotation angle ± 45 °,
It is stored in the memory 6. When the rotation angle exceeds ± 45 °, when the pixel data is read from the original image memory, the X coordinate and the Y coordinate are exchanged and read, so that the data within the range of the rotation angle ± 45 ° is obtained. Used.

Table 1 shows a part of the relationship between the number of input pixels (count value of pixels) for each line, the cumulative reduction number of pixels, and the data indicating the necessity of interpolation when the rotation angle is 30 °.
Is shown in.

[0019]

[Table 1]

In Table 1, the interpolation necessity data has a value "1" indicating that interpolation is required when the cumulative reduction number of pixels exceeds 0.5, and a value "0" indicating that interpolation is not required otherwise. .

Assuming that the interpolation necessity data is created at every rotation angle of 1 °, the most significant bit is used as the sign bit for the number of bits of the angle selection signal input to the memory 6.
Since 6 bits are used to select 1 to 45 °, a total of 7
Become a bit. Further, the number of bits of the data representing the number of pixels for each horizontal line input to the memory 6 is 9 bits required to select the number of pixels 512. The angle selection signal line is connected to the upper side of the address line of the memory 6, and the output line of the counter 5 for calculating the number of pixels is connected to the lower side.

The horizontal synchronizing signal * H is L at the beginning of each line.
The level is reached, and the horizontal pixel counter 5 is cleared each time. While the horizontal synchronizing signal * H is at the H level, the horizontal pixel counter 5 counts the clock signal CLK,
The count value is input to the memory 6 as an address of the memory 6 together with the angle selection signal. From the memory 6, the interpolation necessity data corresponding to the count value of the horizontal pixel counter 5 is output. The latch circuit 7 has a clock signal CL.
The interpolation necessity data from the memory 6 is set at the rising timing of K. The output of the latch circuit 7 is sent to the selector & latch circuit 8 as a selection signal.

Pixel data read diagonally from an original image memory (not shown) is input to the FIFO memory 1, and the input pixel data is written by a write signal * HWR. When the horizontal sync signal * H goes high, the read signal * HRD is output in synchronization with the clock signal CLK.
Pixel data is read from the FIFO memory 1 and set in the latch circuit 2. The read signal * HRD normally changes with the change of the clock signal CLK. However, when the horizontal synchronizing signal * H is at L level or the output of the latch circuit 7 is at H level, the clock signal C is changed.
The current level is retained regardless of changes in LK.

The data set in the latch circuit 2 is set in the latch circuit 3 at the next rise of the clock signal CLK. Further, at the same timing, the selector & latch circuit 8 selects either one of the output of the latch circuit 2 and the output of the average value calculation circuit 4, and the selected data is set in the selector & latch circuit 8. . The selector & latch circuit 8 selects the output of the latch circuit 2 when the output of the latch circuit 7 is L level, and selects the output of the average value calculation circuit 4 when the output of the latch circuit 7 is H level.

The average value calculation circuit 4 comprises an adder 41 for adding the output of the latch circuit 2 and the output of the latch circuit 3, and a bit shifter 42 for obtaining the average value of the output of the adder. That is, the pixel data latched by the latch circuit 2 and the pixel data of the previous pixel latched by the latch circuit 3 are added by the adder 41. Adder 4
Both pixel data added by 1 are 8 bits, so
The output of the adder 41 is 9 bits. The least significant bit of the 9-bit addition result data is cut off by the bit shifter 42 and output as 8-bit data representing the average value of both pixel data.

In the example in which the rotation angle is 30 °, the count value of the counter 5 (lower address of the memory 6) is 4, 12, 1
Interpolation required data "1" is written for 9 ...
When the data "1" required for interpolation is latched by the latch circuit 7, the output of the latch circuit 7 becomes H level.

For example, if the number of pixel data for one row read in the diagonal direction is 7, as shown in FIG. 2, the count value of the counter 5 (lower address of the memory 6) is "t" at time t4. When it becomes 4 ", the output of the memory 6 changes to" 1 ", and the output" 1 "of the memory 6 is set in the latch circuit 7 at the next rising timing of the clock signal CLK (time t5).

At time t5, the content "A4" of the latch circuit 2 is set in the latch circuit 3. Also, at this time t5, the output of the latch circuit 7 is at the L level, so the content “A4” of the latch circuit 2 is set in the selector & latch circuit 8. Further, the next pixel data “A5” is set in the latch circuit 2.

Then, at the next rising timing of the clock signal CLK (time t6), the latch circuit 7
Output is at H level, read signal * HRD
Does not change, the contents of the latch circuit 2 remain unchanged.
However, at time t6, the content "A5" of the latch circuit 2 is set in the latch circuit 3. Therefore, the output of the average value calculation circuit 4 is {(A4
+ A5) / 2}.

At time t6, since the output of the latch circuit 7 is at the H level, the output of the average value calculation circuit 4 {(A4 + A5) / 2} is set in the selector & latch circuit 8. The output of the latch circuit 7 is inverted to L level.

At the next rising timing of the clock signal CLK (time t7), the contents of the latch circuit 2 "
A5 ″ is set again in the latch circuit 3 and is set in the selector & latch circuit 8. Further, the next pixel data “A6” is set in the latch circuit 2.

At the next rising timing of the clock signal CLK (time t8), the contents of the latch circuit 2 "
A6 ″ is set in the latch circuit 3 and is also set in the selector & latch circuit 8. Further, the next pixel data “A7” is set in the latch circuit 2. Further, at time t
At 8, the horizontal synchronizing signal * H is inverted to L level, and the counter 5 is cleared.

At the next rising timing of the clock signal CLK (time t9), the contents of the latch circuit 2 "
A7 ″ is set in the latch circuit 3 and the selector & latch circuit 8. Also, the next pixel data “A7” is set in the latch circuit 2. The horizontal synchronizing signal * H becomes L level. Since the read signal * HRD does not change, the contents of the latch circuit 2 do not change and "A
It remains at 7 ". At this time t9, the horizontal synchronizing signal * H is inverted to H level.

In this way, the seven pixel data A1, A2, A3 ... A7 of the first row read from the original image memory.
Is expanded to eight pixel data by adding interpolation data of {(A4 + A5) / 2} between A4 and A5. Interpolation data is similarly added to the pixel data of the second and subsequent rows read from the original image memory.

The data expanded by the horizontal expansion unit is sent from the selector & latch 8 to the vertical expansion unit.

FIG. 5 shows the structure of the vertically enlarged portion. FIG. 6 shows signals of the respective parts of FIG. However, although the number of horizontal lines is 5 in FIG. 2, for convenience of explanation, in FIG. 6, the signal of each part is shown assuming that the number of pixels of one horizontal line is 2.

The memory 20 stores data indicating on which line the pixel is interpolated for each rotation angle. This data is created in advance within the range of the rotation angle ± 45 ° and stored in the memory 20. Rotation angle is ± 4
When the angle exceeds 5 °, the X-coordinate and the Y-coordinate are exchanged and read when the pixel data is read from the original image memory, so that the data within the range of the rotation angle ± 45 ° is used.

The interpolation necessity data has a value "1" indicating that interpolation is required when the cumulative reduction number of pixels exceeds 0.5, and a value "0" indicating that interpolation is not required otherwise. Rotation angle is 30 °
, The interpolation necessity data corresponding to the 4, 12, 19 ... Lines is the value "1" indicating the interpolation necessity.

The horizontal synchronizing signal * H2 is always at H level, and becomes L level at the beginning of each line. The signal ST is a signal indicating that the rotation processing is being performed, and is always at the L level and becomes the H level during the rotation processing. When the signal ST goes low, the line counter 19 is cleared. When the signal ST is at H level, the line counter 19 counts the horizontal synchronizing signal * H2 and inputs it to the memory 20 as an address of the memory 20 together with the angle selection signal.

The memory 20 outputs interpolation necessity data corresponding to the count value of the line counter 19 (lower address of the memory 20). Interpolation necessity data from the memory 20 is set in the latch circuit 21 at the rising timing of the horizontal synchronizing signal * H2. Further, the output of the latch circuit 21 is set in the latch circuit 22 at the next rising timing of the horizontal synchronizing signal * H2. The output signal (VINS) of the latch circuit 22 is sent to the selector & latch circuit 23 as a selection signal.

The interpolation necessity data corresponding to the count value of the counter 19 becomes "1", and when the output signal VINS of the latch circuit 22 becomes H level accordingly, the interpolation processing in the vertical direction is performed.

The line memories 12 and 13 are line memories for temporarily storing horizontally expanded data, and the horizontally expanded data are alternately written by the write selection unit 11 for each horizontal line.

However, when the interpolation processing in the vertical direction is being performed, that is, while the signal VINS is at the H level,
Writing to the line memory 12 and the line memory 13 is prohibited. The signal VINS is also sent to a circuit for reading pixel data from the original image, and reading of new data is stopped while the signal VINS is at the H level.

Line memory 12 or line memory 13
The pixel data written in 1 is read line by line by the read selection unit 14 and sent to the latch circuit 15. The reading selection unit 14 normally switches the line memory 12 and the line memory 13 for each line, but the signal V
In the line next to the line in which INS is at the H level, the same pixel data is read from the same line memory as the previous line.

The pixel data read from the line memory 12 or 13 is set in the latch circuit 15 pixel by pixel by the read signal * VRD1 synchronized with the clock signal CLK. The read signal * VRD1 normally changes with the change of the clock signal CLK, but when the horizontal synchronizing signal * H is at the L level, the current level is held regardless of the change of the clock signal CLK. . The output of the latch circuit 15 is the selector & latch circuit 23.
Sent to.

At the timing when the pixel data is set in the latch circuit 15, the data of one pixel before, which is held in the latch circuit 15 up to that point, is written in the FIFO memory 16. The pixel data written in the FIFO memory 16 is read by the read signal * VRD2 and set in the latch circuit 17. This read signal * VRD2
Occurs in synchronization with the clock signal CLK and the read signal * VRD1, but is a signal delayed by one line period from the read signal * VRD1. Therefore, the latch circuit 17
Is set to the pixel data of the previous line. The output of the latch circuit 17 is sent to the average value calculation circuit 18.

The average value calculation circuit 18 adds the pixel data output from the latch circuit 15 and the pixel data of one line before output from the latch circuit 17 to the adder 51.
And a bit shifter 52 for obtaining the average value of the output of the adder 51. That is, the pixel data latched by the latch circuit 15 and the pixel data of one line before latched by the latch circuit 17 are added by the adder 51. Since both pixel data added by the adder 51 is 8 bits, the output of the adder 51 is 9 bits. This 9-bit addition result data is stored in the bit shifter 5
The least significant bit is cut off by 2 and output as 8-bit data representing the average value of both pixel data.

The selector & latch circuit 23 includes a latch circuit 15 at the rising timing of the clock signal CLK.
And one of the outputs of the average value calculation circuit 18 are selected and set.

In the example in which the rotation angle is 30 °, the lower address of the memory 20 is 4, 12, 19, ...
When "1" has been written and the lower address has these values, the data "1" required for interpolation is output from the memory 20. The data "1" output from the memory 20 is the rising edge of the horizontal synchronizing signal * H2. Latch circuit 21 at the timing
Is set to. Then, at the next rising timing of the horizontal synchronizing signal * H2, the output "1" of the latch circuit 21 is set in the latch circuit 22.

For example, the lower address of the memory 20 is "
4 "(time t4), the latch circuit 2 is turned on at time t41.
The output of 1 becomes H level, and at time t51, the output signal VINS of the latch circuit 22 becomes H level.

During the horizontal line period (t4 to t5) in which the lower address of the memory 20 is "4", the pixel data "E1" and "E" of the fifth line are stored in the line memory 12.
2 ”is written, and the pixel data“ D1 ”and“ D2 ”of the fourth line are read from the line memory 13.

The lower address of the memory 20 is "5".
VI during the horizontal line period (t5 to t6)
Since the NS signal becomes H level, during this period,
Writing to the line memory 12 or 13 is prohibited.
Then, the pixel data "E1" and "E2" of the fifth line are read from the line memory 12.

The lower address of the memory 20 is "6".
In the horizontal line period (t6 to t7), the pixel data of the same line from the same line memory 12 as the previous time
E1 "and" E2 "are read.

In the horizontal line period (t4 to t5) in which the lower address of the memory 20 is "4", the line memory 1
Pixel data "D1" and "D2" read from 3
Are sequentially set in the latch circuit 15 at the rising timing of the read signal VRD1. At this time, VINS
Since the signal is at the L level, the pixel data set in the latch circuit 15 is set in the selector & latch circuit 23 at the rising timing of the clock signal CLK.

On the other hand, the pixel data "D1" and "D2" set in the latch circuit 15 are stored in the FIFO memory 16 as follows.
Are stored in the latch circuit 17 at the rising timing of the read signal VRD2. At this time, in the latch circuit 15, the pixel data “E1” and “E” read from the line memory 12 in the horizontal line period (t5 to t6) in which the lower address of the memory 20 is “5”.
2 "is sequentially set in the latch circuit 15. At this time, since the VINS signal is at the H level, the output of the average value calculation circuit 18 is" {(D1 + E1) / 2} ".
And "{(D2 + E2) / 2}" are clock signals C
It is sequentially set in the selector & latch circuit 23 at the rising timing of LK.

Next, the lower address of the memory 20 is "6".
In the horizontal line period (t6 to t7), the pixel data "E1" and "E2" read again from the line memory 12 are sequentially set in the latch circuit 15 at the rising timing of the read signal VRD1. At this time, since the VINS signal is at the L level, the pixel data E1 and E2 set in the latch circuit 15 are set in the selector & latch circuit 23 at the rising timing of the clock signal CLK.

As described above, between the pixel data "D1" and "D2" on the fourth line and the pixel data "E1" and "E2" on the fifth line sent from the horizontal enlargement unit, 1 Interpolation data for line "{(D1 + E1) /
2} ”and“ {(D2 + E2) / 2} ”are added. That is, the pixel data sent from the horizontal enlargement unit is vertically expanded. The vertically expanded data is the selector & latch. The circuit 23 writes the rotated image data in a result memory (not shown).

[0058]

According to the present invention, high-speed image rotation processing can be performed with a simple and inexpensive circuit configuration.

[Brief description of drawings]

FIG. 1 is an explanatory diagram illustrating a schematic configuration of an image rotation processing device.

FIG. 2 is an explanatory diagram for explaining image rotation processing by an image rotation processing device.

FIG. 3 is an electrical block diagram of a horizontal enlargement unit.

FIG. 4 is a timing chart showing signals of respective parts of FIG.

FIG. 5 is an electrical block diagram of a vertically enlarged portion.

FIG. 6 is a timing chart showing signals of various parts in FIG.

[Explanation of symbols]

 1 FIFO Memory 2 Latch Circuit 3 Latch Circuit 4 Average Value Calculation Circuit 5 Horizontal Pixel Counter 6 Memory 7 Latch Circuit 8 Selector & Latch Circuit 11 Write Selector 12 Line Memory 13 Line Memory 14 Read Selector 15 Latch Circuit 16 FIFO Memory 17 Latch Circuit 18 Average Value Calculation Circuit 19 Line Counter 20 Memory 21 Latch Circuit 22 Latch Circuit 23 Selector & Latch Circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 1/387

Claims (2)

[Claims] 1. An image rotation apparatus comprising: a means for scanning an original image memory storing an original image in an oblique direction to read pixel data; and a means for horizontally writing the read pixel data in a result memory. Processing equipment. 2. A means for reading out pixel data by diagonally scanning an original image memory in which an original image is stored; horizontal direction and vertical direction interpolation processing being performed on the read pixel data so that An image rotation processing device comprising: an interpolation unit that adds the number of pixel data in the vertical direction; and a unit that horizontally writes the pixel data interpolated by the interpolation unit in a result memory.