JPH0720058B2 - Integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and more particularly to an integrated circuit having enhanced power supply noise resistance.

[Conventional technology]

In the conventional integrated circuit, the voltage supply line for supplying the power supply voltage to the input circuit for transmitting the input signal input from the outside of the integrated circuit to the inside is directly connected to the power supply terminal of the integrated circuit chip. That is, as shown in the conventional example of FIG. 5, the two power supply lines of the input inverter circuit 40 composed of the P-channel MOSFET P1 and the N-channel MOSFET N1 are connected to the power supply terminal V and the ground terminal G by a short metal wire. On the other hand, the output of the input circuit 40 is the input of the internal circuit composed of the P-channel MOSFET P2 and the N-channel MOSFET N2, and the power supply line V2 and the ground line G2 of the internal circuit pass through the inside of the integrated circuit respectively. It was an end of an extremely long metal layer wiring connected to many MOSFETs in the integrated circuit chip, and was connected to the power supply terminal V or the ground terminal G at the opposite end.

[Problems to be solved by the invention]

The conventional integrated circuit described above has a drawback that the integrated circuit is apt to malfunction when negative power noise is generated at the power supply terminal V or positive noise is generated at the ground terminal G. This malfunction will be described with reference to FIGS. 5 and 6 (a), (b), (c), (d). For example, in the state where 5V is applied to the power supply terminal V, 0V to the ground terminal, and 3V to the input terminal I as shown in FIG. 6 (a) in FIG. 5, O1 becomes 0V and O2 becomes 5V. In this state, when noise of about several ns is input to the ground terminal G as shown in FIG. 6 (b), the ground terminal G and the N channel MOSF are connected.
Since the metal wiring between the source of ET N1 is short, noise is transmitted as it is, the potential difference between the source and gate of MOSFET N1 becomes small, and the value obtained by subtracting the potential of noise from the potential of input terminal I is lower than the threshold voltage of MOSFET N1. When it becomes smaller, N1 becomes non-conductive. On the other hand, P-channel MOSFET P1 is connected to input terminal I
When the TTL level (3V in FIG. 6) is applied, the potential is −2V as seen from the electrode of the power supply terminal, which is the source potential, and therefore the gate is conductive, so that O1 Rises as shown in FIG. 6 (c).
As a result, the MOSFET N2 becomes conductive, and the O2, which should originally be at the high level, drops to the low level as shown in FIG. 6 (d), and an erroneous signal is transmitted to the inside of the integrated circuit, so that the integrated circuit malfunctions. Will be done.

The present invention smoothes noise input to a power supply terminal or a ground terminal by connecting a power supply line and a ground line that supply a power supply voltage to an input circuit to a power supply terminal and a ground terminal via a CR time constant circuit, respectively. Thus, it is possible to obtain an integrated circuit in which malfunction due to noise in the input circuit is prevented.

[Means for solving problems]

The integrated circuit of the present invention is arranged such that an input circuit supplied with an input signal, an internal circuit connected to the input circuit, and the input circuit and the entire internal circuit are arranged so as to cross the entire input circuit and the internal circuit. First and second power supply lines for supplying first and second power supplies, respectively, and the first and second power supply lines.
For the first and second input circuits for supplying the first and second power supplies to the input circuit via the first and second power supply terminals provided at one end of each of the power supply lines In an integrated circuit including a power supply line, one end is connected to the first power supply terminal and the other end is connected to the first input circuit power supply line, and one end is connected to the first input circuit. A first CR time constant circuit including a power source line and a first capacitive element having the other end connected to the first power source line;
A second resistor having one end connected to the second power supply terminal and the other end connected to the second input circuit power supply line; and one end connected to the second input circuit power supply line and the other end connected to the second And a second CR time constant circuit including a second capacitive element connected to each of the power supply lines.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of an input circuit portion of an integrated circuit of the present invention. A CR time constant circuit composed of a resistance RV and a capacitance CV is installed between the power supply terminal V and the input circuit power supply line V1, and a resistor RG and a capacitance CG are connected between the ground terminal G and the input circuit ground line G1. The CR time constant circuit 12 is provided, and V1 and G1 are the power supply line and the ground potential supply line of the input circuit 10, respectively. Further, the terminal T1 on the side opposite to V1 of the capacitor CV supplies the internal power supply line V2 which supplies power for the internal circuits except the input circuit 10, and the terminal T2 on the side opposite to V2 of the capacitor CG supplies the ground for the internal circuit. Are connected to the internal ground line G2. The internal power supply line V2 and the internal ground line G2 are drawn far from the power supply terminal and the ground terminal, respectively, and contain a huge stray capacitance of the internal circuit element, so that they are hardly affected by the power supply terminal and the ground terminal. By making such a connection, noise input from the power supply terminal and the ground terminal is smoothed, and potential fluctuations (noise) caused by a large current such as when the internal circuits switch all at once, These power lines V through CV or CG
Since the potentials of the high frequency (pulse) components of 1, V2 and the ground lines G1, G2 are always kept at substantially the same potential, the operation of the input circuit can be stably maintained against this internal noise. CR
The time constant circuit 11 prevents malfunction due to noise in the negative direction with respect to the power supply voltage, and the time constant circuit 12 prevents malfunction due to noise in the positive direction with respect to the ground voltage. You may install only a circuit.

FIG. 2 is a circuit diagram showing a more specific first embodiment of the present invention shown in FIG. The time constant circuit 21 is the first
Similar to the figure, it is composed of a resistor RV and a capacitor CV, and the time constant circuit 22 is also composed of a resistor RG and a capacitor CG. The input circuit 20 is an inverter composed of a P-channel MOSFET P1 and an N-channel MOSFET N1 and its output O1 is P which is an internal circuit.
It is the input of the inverter composed of channel MOSFET P2 and N channel MOSFET N2. Also the input circuit
The 20 power supply voltage supply line V1 is taken out from the connection point of RV and CV, and the ground voltage supply line G1 is taken out from the connection point of RG and CG. Similar to the first embodiment, the other end of CV is an internal power supply line.
The other end of CG is connected to V2 and the internal ground line G2, respectively. In the circuit of the embodiment of FIG. 2, for example,
Similar to the circuit of the conventional example in the figure, when noise as shown in FIG. 6 (b) is input to the ground terminal G, the noise is smoothed by the CR time constant circuit 22, so that the noise generated in G1 is The wave height becomes much smaller than the wave height of the noise input to the ground terminal G. Since the noise wave height generated in G1 changes depending on CG and RG, setting RG and CG according to the allowable noise wave height and input time prevents N1 from becoming non-conducting due to G1 potential rise due to noise. Can be held in range, resulting in O1 holding high and O2
Becomes invariable at low level, and it is possible to prevent malfunction.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In the embodiment of FIG. 3, the resistor RV, which is the R portion of the CR time constant circuit in the embodiment of FIG. 2, is connected to the P-channel depletion type MOSFET PD whose drain and gate are connected, and the resistor RG is connected to the drain. N-channel MO with gate connected
It is the same except that it is replaced with SFET ND. In the case of the embodiment shown in FIG. 2, it takes a relatively long time to discharge the potential of G1 raised by noise again, which may adversely affect the switching characteristic of the input circuit and the input voltage-output voltage characteristic. However, in the configuration of the embodiment of FIG. 3, the resistance when viewing V1 from the power supply terminal V or the resistance when viewing G1 from the ground terminal G is large, and conversely when viewing V1 to V or G1 to G. Since the resistance of can be made much smaller, it is possible to discharge the potential rise due to the noise of G1 or V1 promptly, and there is an advantage that the above-mentioned adverse effects can be eliminated or reduced.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention. Between the power supply terminal V and the power supply voltage supply line V1 of the input circuit, a resistor RV which is the R part of the CR time constant in the embodiment of FIG.
R1 and P-channel MOSF with gate connected to drain
The parallel connection circuit 11 of the ET PD is inserted. Further, between the ground terminal G and the ground voltage supply line G1 of the input circuit, a resistance R2 and a parallel connection circuit 12 of N-channel MOSFETs ND whose drains and gates are similarly connected are inserted. The input circuit 10 composed of the P-channel MOSFET P1 and the N-channel MOSFET N1 is connected to V1 and G1, and the signal input from the input terminal I is inverted to form the internal circuit composed of the P-channel MOSFET P2 and the N-channel MOSFET N2. Transmission to the circuit is the same as in the case of FIG. In the circuit of the embodiment shown in FIG. 4, when noise as shown in FIG. 6 (b) is input to the ground terminal G, noise is input to the resistor R2 as in the circuit of the conventional example shown in FIG. Noise is attenuated by the function of the time constant circuit due to the stray capacitance CG of the ground voltage supply wiring G1 of the circuit, and the potential fluctuation of G1 can be reduced, so that the output O1 of the input circuit 10 rises at P2 and It is suppressed below the circuit threshold of the internal circuit composed of N2, and the output O2
Can be eliminated. Also, the ground terminal G
Since the signal input from the input terminal I is TTL level regardless of the presence or absence of noise to the P-channel MOSFET, the P-channel MOSFET may be conductive when the input signal is high level, and the N-channel MOSFET may be conductive. G1 because it is in a state
A current flows into the circuit, which raises the potential of G1, which causes deterioration of the characteristics of the input circuit. In the present invention, when the potential of G1 rises, a current is passed to the ground terminal G through ND. As a result, it is possible to suppress the rise in the potential of G1. Also, regarding the potential rise of G1 at the time of switching the input circuit 10 and the potential rise of G1 due to the noise from the ground terminal, the potential of G is discharged normally through ND in accordance with the normal ground potential of G, It is possible to recover the potential. The negative direction noise generated at the power supply terminal V is also attenuated by R1 and CV as described above, and the decrease in the potential of V1 can be restored to the power supply potential of V by the action of PD. Promptly following and recovering is similar to the above case. In order to prevent the deterioration of the characteristics of the input circuit caused by the installation of the time constant circuit, for example, the deterioration of the input-output characteristics and the switching characteristics, the second
The resistance value of RV in the figure and PD in Figures 3 and 4 is less than 1/10 of the resistance of P1 in conduction, and RG in Figure 2 and in Figure 3 and 4
It is desirable to set the resistance value of ND to 1/10 or less of the resistance when N1 is conducting.

〔The invention's effect〕

As described above, according to the present invention, by installing a CR time constant circuit between either the power supply terminal or the ground terminal, or both and the power supply line to the input circuit, the power supply terminal or the ground terminal is provided. There is an effect that it is possible to obtain an integrated circuit with enhanced reliability against malfunction due to pulse noise generated in the above.

[Brief description of drawings]

1 is a circuit diagram showing a configuration of an input circuit portion of an integrated circuit of the present invention, FIG. 2 is a circuit diagram showing a first embodiment more concretely showing the embodiment shown in FIG. 1, and FIG. Is a circuit diagram showing a second embodiment of the present invention, FIG. 4 is a circuit diagram showing a third embodiment of the present invention, FIG. 5 is a circuit diagram showing a conventional example, and FIG. It is a conceptual diagram explaining. In the figure, V ... power supply terminal, I ... input terminal, G ...
Ground terminal, 11,12 ... CR time constant circuit, RV, RG ... Resistance, C
V, CG ... Capacity, V1 ... Input circuit power supply line, G1 ... Input circuit ground line, 10 ... Input circuit, O1 ... Input circuit output,
21,22,31,32 …… CR time constant circuit, PD …… P channel depletion type MOSFET, ND …… N channel depletion type MOSFET, 20,30 …… Input circuit, P1, P2 …… P Channel enhancement type MOSFET, N1, N2 …… N channel enhancement type MOSFET, V2 …… Internal power supply line,
G2: Internal ground wire.

Claims (3)

[Claims] 1. An input circuit supplied with an input signal, an internal circuit connected to the input circuit, and an input circuit arranged to traverse the input circuit and the entire internal circuit. The first and second power supply lines for supplying a second power supply respectively, and the first and second power supply terminals provided at one end of each of the first and second power supply lines, respectively. An integrated circuit comprising first and second power supply lines for input circuit for supplying the first and second power supplies to an input circuit, wherein one end is the first power supply terminal and the other end is the first input A first resistance element connected to the circuit power supply line, and a first capacitive element having one end connected to the first input circuit power supply line and the other end connected to the first power supply line, respectively. 1 CR time constant circuit and one end of the second power supply terminal A second resistor having the other end connected to the second input circuit power supply line, and one end connected to the second input circuit power supply line and the other end connected to the second power supply line, respectively. An integrated circuit comprising at least one of a second CR time constant circuit including a second capacitance element. 2. The integrated circuit according to claim 1, wherein each of the first and second resistors is a MOSFET in which a drain and a gate are commonly connected. 3. The integrated circuit according to claim 1, wherein the first and second resistors are a parallel connection circuit of a MOSFET having a drain and a gate commonly connected and a third resistor.