JPH0719444B2 - Data playback device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital clock using a self-clocking method.
More specifically, the present invention relates to a data reproducing apparatus which operates stably against a bit rate variation during a high speed search and can perform a higher speed search.

2. Description of the Related Art In recent years, digital recording / reproducing technology has been applied to a wide range of fields, especially digital audio and digital.
It has made remarkable progress in the fields of audio and video such as VTR.

Among them, a high-speed search function for finding target data in a short time is practically important.

For example, a rotary head type digital
In the data playback device, when the tape is run at a high speed, the bit rate of the playback clock changes compared to that during normal running.Therefore, in order to punch out the input digital data correctly with the playback clock, the playback clock extraction phase Locked Loop (PLL)
It was necessary to widen the capture range of the circuit.

Note that the capture range of the PLL circuit is the range of frequencies in which the PLL can be pulled and locked from the free run (unlocked state).

In addition, it was necessary to change the head scan speed according to the tape speed so that the bit rate would not exceed the capture range, and control the bit rate to reduce fluctuations.

An example in which the above-described conventional reproduction clock extraction device is applied to a rotary head type digital data reproduction device will be described below with reference to the drawings.

FIG. 3 shows the configuration of a conventional recovered clock extraction device.

In FIG. 3, 101 is a cassette half, 102 is a reel,
103 is a tape, 104 is a cylinder, 105a, 105b are heads, 106
Is a head amplifier, 107 is a PLL (Phas
e Locked Loop) circuit, 108 is a PLL frequency detection unit that detects the frequency of the reproduction clock (b) output from the PLL circuit, 109 is a tape speed setting unit that sets the target tape speed, and 110 is the PLL frequency Based on the PLL frequency data (c), the PLL frequency detection flag (d) output from the detection unit 108, and the speed data (e) output from the tape speed setting unit 109, the target tape speed is set. , A tape speed control unit for giving control parameters to the cylinder servo 111 and the reel servo 113, 112 is a cylinder driver for driving the cylinder, 114
Is a reel driver for driving the reel.

The operation of the conventional recovered clock extraction device configured as described above will be described.

The reproduction clock extraction device in FIG. 3 uses a method of controlling the tape speed only by driving the reel without using a capstan.

Now, let us consider the change in tape speed when the tape is run with the reel rotation frequency kept constant.

FIG. 4 shows how the tape is wound by driving the reel. R ₀ is the radius of the reel, r is the value obtained by adding the tape thickness of the wound tape to r ₀ , and fr is Reel rotation frequency, v is tape speed.

Here, assuming that the tape thickness is T and the time from the start of winding is t, v = 2π (r ₀ + r) fr = 2π (r ₀ + fr Tt) fr = 2π (r ₀ fr + Tfr ² t) (1) Is plotted on the graph as shown in Fig. 5.

That is, in the tape running by the above reel drive, the tape speed changes with time t, and its inclination also changes depending on the tape thickness, which makes control difficult.

Therefore, in the conventional reproduction clock extraction device, the reel rotation frequency fr is controlled based on the reproduction clock frequency (hereinafter referred to as the PLL frequency) so that a constant tape speed can be obtained.

Next, the principle of controlling the tape speed based on the PLL frequency will be described.

FIG. 6 is a diagram showing the relative speeds of the tape and the head. In FIG. 6, 400 is a cylinder, 401 is a tape,
Vh ₀ is the head scan speed, Vt is the tape speed, Vh ₁ is the tape speed during high speed running, Vh is the relative tape speed of the head during recording, Vh ₁ is the relative speed between the head and tape during high speed running, Vh ₂ is the Vh direction component of Vh ₁ , θ is the head scan elevation angle, θ ₁ is the recorded track elevation angle, θ
₂ Head scan elevation angle during high-speed running, θ ₃ is θ ₃ = θ
_2- θ ₁ .

Here, the relative speed of the tape and the head at the time of recording, Vh is expressed as follows.

Vh ₂ = (Vh ₀ −Vt) ² + 2Vh ₀ Vt (1-cos θ) When θ is sufficiently small VhVh ₀ −Vt …… (2) Similarly, Vh ₁ Vh ₀ −Vt ₁ …… (3) Vh ₁ If the component in the Vh direction is Vh ₂ , then Vh ₂ = Vh ₁ cos θ ₃ = Vh ₁ cos (θ ₂ −θ ₁ ) If this is converted to the PLL frequency fp Here, λb is the minimum recording wavelength.

When θ is sufficiently small, cos (θ ₂ −θ ₁ ) 1 ∴Vt ₁ Vh ₀ −λb fp (5) Therefore, the tape running speed can be obtained from the value of the PLL frequency fp and the head scan speed Vh ₀ . Therefore, the tape speed is controlled to detect the PLL frequency (the frequency of the reproduction clock), and the PLL frequency data (c) and the PLL frequency detection flag (d) indicating that the PLL frequency has been detected are provided to the tape speed control unit 110. Supply.

When the tape speed control unit 110 reaches the target tape speed by the speed data (e) set by the tape speed setting unit 109, the PLL frequency fp is the same as during normal reproduction (reproduction at the same tape speed as when recording). Cylinder servo (111)
Gives the parameter of cylinder speed. Further, the PLL frequency data (c) supplied from the PLL frequency detection unit (108) is used only when the PLL frequency detection flag (d) is valid, and based on the algorithm described in FIG.
By giving the reel servo (113) a parameter of the reel rotation frequency so that the desired tape speed can be obtained and controlling the tape speed, the frequency of the input digital data can be adjusted.
The recovered clock is extracted so that it falls within the capture range of PLL107.

Problems to be Solved by the Invention However, with the above method, it is difficult to follow up when the tape speed changes rapidly, so if you want to change the tape speed rapidly, widen the capture range of the PLL. However, if you try to make the capture range of the PLL wide, the PLL becomes unstable, and the recovered clock should be extracted stably when there are many input data errors, especially during high-speed search. Becomes difficult.

There is another important issue. Since the reproduction data at the time of search is intermittent and the information density is low, the search speed is naturally limited. This limit is as shown in FIG. 8 depending on the search direction and speed. FIG. 8 is a diagram showing a limit speed for reading a subcode recorded on a tape at a standard speed for 9 seconds at the time of searching a DAT having a rotary head of 30φ.

The first quadrant shows the relationship between the fast-forward direction (FF) search speed and the bit rate, and the second quadrant shows the relationship between the rewind direction (REW) search speed and the bit rate.

It is clear from Fig. 8 that the bit rate must be increased in order to increase the search speed.
About 250x speed is the limit for both F side and REW side.

Therefore, in order to realize 300 times or more speed, it is necessary to increase the bit rate during search.

Means for Solving the Problems In order to solve the above two problems, the data reproducing apparatus of the present invention has a means for measuring the bit rate of a reproduced signal, a clock reproducing PLL for extracting a clock from the reproduced signal, and a PLL.
It consists of a range offset control unit, sets multiple bit rate target values, switches the free-run frequency of the clock recovery PLL according to the target values, and outputs the clock based on the difference between the target value and the measured reproduction signal bit rate. It controls the capture range of the PLL and supplies it to the means for adjusting the bit rate of the reproduced signal so that the bit rate becomes a predetermined bit rate.

Effect The present invention can separately set the bit rate target value at the time of normal reproduction and the bit rate target value at the time of search by the above configuration, and the tape speed is set so that the bit rate of the reproduction signal approaches each target value. It is possible to always follow the bit rate of the reproduced signal by adjusting the error and the like, and controlling the width of the capture range of the PLL or moving the center frequency by measuring the error during transition.

Embodiment An embodiment in which the reproduced clock extracting device of the present invention is applied to a rotary head type digital data reproducing device will be described below with reference to the drawings.

FIG. 1 shows the configuration of the recovered clock extraction device of the present invention.

The parts other than the PLL part 616 are the same as those of the conventional recovered clock extracting device described with reference to FIG.

In FIG. 1, 607 is a PLL (Phase Loc) capable of changing the center value of the capture range by externally applied capture range control data (f).
ked loop) circuit and a PLL circuit capable of switching the operating range by another target bit rate setting data (g) given from the outside. 620 sets a target bit rate (BR) according to the mode.

Reference numeral 608 denotes a PLL frequency detection unit that detects the frequency of the reproduction clock output from the PLL circuit 607 and outputs PLL frequency data (c) and PLL frequency detection flag (d). Reference numeral 615 denotes PLL frequency data (c) and PLL. P based on the frequency detection flag (d)
The capture range control unit outputs the capture range control data (f) that determines the center value of the capture range of the LL circuit 607 to the PLL circuit 607.

Next, the operation of the PLL unit 616 will be described with reference to FIG.

FIG. 2 is a graph showing how the PLL frequency data changes according to the frequency change of the input digital data, and the capture range of the PLL circuit 607 changes accordingly.

The vertical axis represents the fluctuation of the PLL frequency data in%, and the horizontal axis is the time axis.

In FIG. 2, 701 represents PLL frequency data and 702 represents P frequency data.
The LL circuit 607 represents the capture range, and 703 represents the center value of the capture range.

Here, the width of the capture range of the PLL circuit 607 is ± 5
%, The capture range control data representing the center value of the capture range is -3%, 0%, + 3% of 3
On the street. Further, the capture range control unit 615 determines the value of the capture range control data (f) by looking at the PLL frequency data (c) when the PLL frequency detection flag (d) output by the PLL frequency detection unit 608 is active. To do.

Here, it is assumed that the capture range control unit 615 outputs the capture range control data under the conditions shown in Table 1.

Therefore, in FIG. 2, the PLL frequency data is (a).
When it exceeds + 3% at the point, the center of the capture range shifts to + 3%, and when it becomes less than + 3% at the point (b), it returns to 0%. On the contrary, when the reproduction clock frequency becomes -3% or less at point (c), the capture
The center of the range shifts to -3% and becomes 0 at point (d).
Return to%.

Further, when the PLL frequency cannot be detected (when a non-recorded portion or the like is reproduced) after the point (e), the chapter range control data is pre-held.

Therefore, by performing the above processing, the PLL
The effective capture range of the entire part 616 is expanded by ± 3% to ± 8%.

Although the steps of the capture range control data have been described as three steps here, a wider capture range can be obtained by increasing the number of steps.

In this way, the effective capture range can be expanded in different areas in each mode according to the target bit rate.

As described above, the present invention comprises means for measuring the bit rate of a reproduction signal, a clock reproduction PLL that extracts a clock from the reproduction signal, and a PLL range offset control unit, and sets a plurality of bit rate target values. , The free-run frequency of the clock recovery PLL is switched according to the target value, and the output based on the difference between the target value and the measured reproduction signal bit rate is used to control the capture range of the clock recovery PLL and the bit of the reproduction signal. By supplying it to the means for adjusting the rate so that the bit rate becomes a predetermined value, a stable clock recovery PLL with a relatively narrow capture range is used to effectively target a wide capture range. Since it can be secured in each area according to the bit rate setting, it can The recovered clock can be stably extracted with respect to the digital signal input, and the entire operation region can be moved to a higher position during the search, so that a high-speed search exceeding the limit so far becomes possible.

Further, the means for measuring the bit rate of the reproduction signal includes a synchronization signal detector for demodulating the reproduction data and detecting the synchronization signal from the digital signal, and a synchronization detection flag when the synchronization signal is input at a specific interval. By measuring the interval between the synchronization signals when the synchronization is detected and the condition determination unit that outputs the output, it is possible to protect the output data of the frequency detection device from an apparent synchronization signal or the like.

Further, the means for measuring the bit rate of the reproduced signal is equipped with an error detecting means for demodulating a digital signal containing an error detecting code to detect an error, and the condition judging section detects the sync signal at a specific interval and The sync detection flag is output when no error is detected from the digital signal corresponding to the sync signal, and the clock recovery PLL is output only when the sync detection flag is set.
By controlling the capture range of, the output data of the frequency detection device can be made highly reliable, and higher-speed search can be stably performed.

In the embodiment of the present invention, the control information of the cylinder speed is supplied with an output based on the difference between the bit rate target value and the measured bit rate value, and is added together with the output information of the tape speed control unit 610. A double servo system is configured, and a system that suppresses gentle fluctuations and a system that suppresses high-speed fluctuations during transients will be added, so that stable servo can be applied. became.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a recovered clock extraction device according to an embodiment of the present invention, FIG. 2 is a graph showing the relationship between PLL frequency data and PLL capture range, and FIG.
FIG. 4 is a block diagram of a reproduction clock extraction device in a conventional example of the present invention, FIG. 4 is a schematic diagram showing winding of a tape, FIG. 5 is a graph showing changes in tape speed, and FIG. FIG. 7 is a flowchart showing the tape speed control algorithm, and FIG. 8 is a graph showing the relationship between the limit search speed and the bit rate. 601 ... Cassette half, 602 ... Reel, 603 ... Tape, 604 ... Cylinder, 605a, 605b ... Head, 606 ...
Head amplifier, 607 ... PLL, 608 ... PLL frequency detection section, 609 ... Tape speed setting section, 610 ... Tape
Speed control unit, 611 ... Cylinder servo, 612 ... Cylinder driver, 613 ... Reel servo, 614 ... Reel driver, 615 ... Capture range control unit, 6
16 …… PLL section, 620 …… Target bit rate setting section.

Claims (3)

[Claims] 1. A means for measuring a bit rate of a reproduction signal and a clock reproduction PLL for extracting a clock from the reproduction signal.
And a PLL range offset control unit that sets multiple bit rate target values and regenerates the clock according to the target values.
While switching the PLL free-run frequency, the output based on the difference between the target value and the measured playback signal bit rate is used to control the capture range of the clock recovery PLL and to adjust the bit rate of the playback signal. A data reproducing device characterized in that the data is supplied so as to have a predetermined bit rate. 2. A means for measuring the bit rate of a reproduced signal, wherein a synchronizing signal detecting section for demodulating the reproduced data to detect a synchronizing signal from a digital signal, and a periodic signal being inputted at a specific interval. The data according to claim (1), which comprises a condition determination unit that outputs a synchronization detection flag and a synchronization signal cycle measurement unit that measures an interval between synchronization signals when synchronization is detected. Playback device. 3. A means for measuring the bit rate of a reproduced signal comprises an error detecting means for demodulating a digital signal containing an error detecting code to detect an error, and the condition judging section detects a sync signal at a specific interval. And a synchronization detection flag is output when an error is not detected from the digital signal corresponding to each synchronization signal, and the capture range of the clock recovery PLL is controlled only when the synchronization detection flag is set. 2. A data reproducing apparatus according to item (2).