JPH07193711A - Picture processor - Google Patents

Abstract

PURPOSE:To provide a device capable of correcting even an error due to the dispersion of a reading characteristic on plural reading positions of a picture reading means in addition to the reading of a reference original on plural positions in the reading range of the reading means and the correction of dispersion on the positions of the original. CONSTITUTION:A calibrating part 312 calibrates the dispersion of a reading characteristic included in a scanner part 201 based upon the read result of a reference original whose density is managed by the scanner part 201 by reading out the reference original on plural positions in the reading range of the scanner part 201.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, for example, an image processing apparatus having a function of detecting a specific original.

[0002]

2. Description of the Related Art In recent years, as image forming apparatuses such as copying machines and printers have become higher in image quality and color, bills, securities, etc.
There is a fear of counterfeiting of manuscripts that should not be copied (hereinafter referred to as "specific manuscripts"). Furthermore, when recognizing a “specific document” in an image processing apparatus such as a copying machine, the characteristic data of a plurality of types of specific originals is held in advance inside the apparatus, and compared with the characteristics of the image signal input from the document reading unit, As a device for determining whether or not at least one of specific types of originals is present and preventing these copying operations from occurring, there are proposed methods such as Japanese Patent Application No. 4-252828 and No. 4-252828. There is.

Further, in order to maintain the recognition accuracy of the "specific document", it is important to suppress the characteristic variation of the reading section. Therefore, as a device provided with a means for calibrating this, as a device for reading a reference white plate for calibration by the image reading unit and calibrating the characteristic variation between the devices of the image reading unit, Japanese Patent Application No. -25820
The device described in No. 7 has been proposed.

That is, as shown in FIG. 79, the reference white plate 651 is placed at a predetermined position of the platen glass 203 of the document reading means, for example, at the center of the left end of the platen glass as shown in FIG. The characteristics of the image reading unit are grasped by reading the, and the characteristic variations are corrected.

[0005]

However, in the above-mentioned prior art, since the reference white plate for calibration is read in only one place of the original plate of the image reading unit to calibrate the characteristics of the image reading apparatus, The following problems occurred. That is, the characteristics of the image reading unit also slightly vary depending on the position on the platen glass.
However, in the above-mentioned conventional example, for example, FIG.
Since the reference white plate for calibration was placed at the position indicated by No. 651 to calibrate the variation in the characteristics, it was unavoidable that a calibration error occurred.

[0006]

The present invention has been made for the purpose of solving the above-mentioned problems, and has the following structure as one means for solving the above-mentioned problems. That is, the image reading means for reading the original image, the image signal processing means for electrically processing the read image signal from the image reading means, and the characteristics of the image signal in advance in the processing of the image signal by the image signal processing means. The calibration means includes a determination means for determining the presence or absence of a registered specific original document, and a calibration means for reading a standard document whose density is controlled and calibrating variations in the reading characteristics of the image reading means based on the reading result. Performs the calibration by reading the standard document at a plurality of locations within the reading range of the image reading means.

[0007]

With the above arrangement, not only the standard original is read at a plurality of positions within the reading range of the image reading means to correct the variation due to the position of the original, but also due to the variation of the reading characteristic at the reading position of the reading means. You can also correct the error.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described in detail below with reference to the drawings. In the following description, an example of a copying machine is shown as an application example of the present invention, but the present invention is not limited to this, and it is needless to say that it can be applied to various other apparatuses.

[0009]

First Embodiment [Apparatus Overview] FIG. 1 shows an overview of an apparatus according to an embodiment of the present invention. In FIG. 1, 201 is an image scanner unit that reads a document and performs digital signal processing, and 202 is a printer unit that prints out an image corresponding to the document image read by the image scanner 201 on paper in full color.

In the image scanner 201, 200
Is a mirror surface plate. A document 204 on a platen glass (hereinafter referred to as a “platen”) 203 is illuminated by a lamp 205, guided to mirrors 206, 207, and 208, and a three-line solid-state image sensor (hereinafter referred to as “CCD”) by a lens 209. An image is formed on the image 210 and three image signals of red (R), green (G), and blue (B) as full-color information are sent to the signal processing unit 211.

The lamp 205 and the mirror 206 are mechanically movable at a speed v, and the mirrors 207 and 208 are mechanically moved at a speed (1/2) v in a direction perpendicular to the line sensor arrangement direction (main scanning direction). Thus, the entire surface of the document is scanned (sub-scanning). Here, the original 204 is subjected to both main scanning and sub scanning.
Scanned at a resolution of 400dpi (dots / inch). A signal processing unit 211 electrically processes an image signal read by the CCD 210, and magenta (M), cyan (C), yellow (Y), and black (B).
It is decomposed into each component of k) and sent to the printer unit 202. In addition, one component of M, C, Y, and Bk is sent to the printer unit 202 for each document scanning by the image scanner 201, and one printout is completed by a total of four document scanning.

The M, C, Y, and Bk image signals sent from the image scanner unit 201 are supplied to the laser driver 2.
Sent to 12. The laser driver 212 modulates and drives the semiconductor laser 213 according to the sent image signal. Laser light from the semiconductor laser 213 scans the photosensitive drum 217 via a polygon mirror 214, an f-θ lens 215, and a mirror 216. Here, 400 dpi (dots / inch) for both main scanning and sub-scanning as in reading
Written in resolution.

Reference numeral 218 denotes a rotary developing device, which includes a magenta developing section 219, a cyan developing section 220, a yellow developing section 221,
The black developing unit 222 is composed of four developing units alternately contacting the photosensitive drum 217 to develop the electrostatic development formed on the photosensitive drum with toner. 223 is a transfer drum, and the paper supplied from the paper cassette 224 or the paper cassette 225 is wound around the transfer drum 223,
The image developed on the photosensitive drum is transferred to a sheet.

In this way, the paper on which the four colors of M, C, Y and Bk are sequentially transferred passes through the fixing unit 226 and the toner is fixed on the paper, and then the paper is ejected. Also, 22
Reference numeral 7 denotes an IC card, which can be inserted into a card reader 228 incorporated in the image scanner 201 to transfer the information held in the IC card 227 to the apparatus.

[Image Scanner] FIG. 2 is a block diagram showing the flow of image processing in the image scanner 201. In FIG. 2, 210-1, 210-2, 21
Reference numerals 0-3 denote CCD (solid-state image sensor) sensors having spectral sensitivity characteristics of red (R), green (G), and blue (B), respectively, which are 8-bit output (0 to 0) after A / D conversion. 255) signal is output.

Reference numerals 312-1, 312-2 and 312-3 are calibrating means for calibrating variations in the reading characteristics of the image reading section, which will be described in detail later. Furthermore, CCD sensors 210-1 and 21 used in this embodiment.
Since 0-2 and 210-3 are arranged at a fixed distance, the spatial shifts of the delay elements 301 and 302 are corrected, and R, G, and B image signals are output.

Reference numerals 303, 304 and 305 denote log converters, which are constituted by a look-up table ROM or RAM and convert a luminance signal into a density signal. 306 is a known masking and UCR (under color removal) circuit,
Although a detailed description is omitted, each of the three signals that have been input causes the magenta (M), cyan (C), yellow (Y), and black (Bk) signals to be output in a frame-sequential manner for each reading operation. Is output with a bit length of, for example, 8 bits.

Here, the CNO signal is a 2-bit field sequential signal, and is a control signal indicating the order of four read operations as shown in Table 1, and the masking / UCR circuit 306.
Switch the operating conditions of.

[0019]

[Table 1] A known spatial filter circuit 307 corrects the spatial frequency of the output signal. 308 is a density conversion circuit,
The density characteristic of the printer unit 202 is corrected, and the printer unit 202 is composed of the same ROM or RAM as the log converters 303 to 305.

On the other hand, reference numeral 309 denotes a specific manuscript judging means, which judges the specific manuscript based on 32 kinds of judgment conditions, and outputs the judgment result as a 32-bit HIT signal. That is, for each of the 32 types of determination conditions, if the conditions are met, "1" is generated as a HIT signal, and if not, "0" is generated as a HIT signal. Reference numeral 311 denotes a microprocessor (hereinafter referred to as “CP
"U". ). The CPU 309 has a determination circuit 30.
9 which is a judgment result based on a plurality of judgment conditions.
If it is determined based on the IT signal that at least one specific document among the plurality of specific documents registered in advance is present, the copy inhibition signal INHIBIT is output. Further, the CPU 311 can recognize the unique identification code (ID) added to the read-only memory (ROM) in the determination circuit 309, and the control signal at that time is R
The ID signal is the ID signal, and the read IDs are the ROM1-ID signal and the ROM2-ID signal.

Reference numeral 310 denotes a copy prohibiting means, which is an OR gate circuit for preventing a plurality of specific originals from being copied, which corresponds to the 8-bit output V of the density converting means 308.
Output ORHIBIT signal from CPU 311 and logical OR
Is output and V'is output. As a result, INHIBI
When T = “1”, that is, when it is determined that the specific document is read, the output becomes V ′ = FF / Hex (255 / DEC) regardless of the value of the input signal V, and the determination signal When INHIBIT = 0, that is, when it is determined that the specific document is not read, the value of the input signal V is output as it is as the output signal V ′.

[Calibration of Image Scanner] The calibrating means 312-1, 312-2, 312-3 shown in FIG. 2 are for correcting variations in the reading characteristics of the document reading section.
The calibration method of this embodiment will be described below with reference to FIG. In this embodiment, five points on the platen glass 203 shown in FIG. 78, that is, 641 (upper left), 642.
(Lower left), 643 (center), 644 (upper right), 645
By reading a standard white plate for calibration whose density is known in advance at five points (lower right), it is possible to grasp the variation in the reading characteristics based on the difference in the reading position of the document reading unit.

The read values (R, G, B signals) of the standard white plate at five points are respectively (RT1, GT1, B).
T1), (RT2, GT2, BT2), (RT3, GT
3, BT3), (RT4, GT4, BT4), (RT
5, GT5, BT5), the calibration means 312-1,
The 312-2 and 312-3 are calibrated by the following correction formula.

That is,

[0025]

## EQU1 ## RT0 = (RT1 + RT2 + RT3 + RT4 +
RT5) / 5 GT0 = (GT1 + GT2 + GT3 + GT4 + GT5)
/ 5 BT0 = (BT1 + BT2 + BT3 + BT4 + BT5)
The read signals at the five reading positions are averaged by the formula / 5 to reduce the influence of variations due to the reading positions.

Further, the calibration means 312-1 carries out calibration according to the following equation.

[0027]

## EQU00002 ## Rout = Rin.times.RTGT / RT0 where Rin; pre-calibration data, that is, input to the calibration means Rout; post-calibration data, that is, output from the calibration means RTGT; In 312-2, calibration according to the following equation is performed.

[0028]

## EQU00003 ## Gout = Gin.times.GTGT / GT0 where Gin; pre-calibration data, that is, input to the calibration means Gout; post-calibration data, that is, output from the calibration means GTGT; Is calibrated by the following equation.

[0029]

## EQU4 ## Bout = Bin × BTGT / BT0 where Bin; pre-calibration data, that is, input to the calibration means Bout; post-calibration data, that is, output from the calibration means, BTGT; As a result, it is possible to correct the variation in the reading characteristic between the devices and reduce the influence of the error due to the characteristic variation in the reading position on the original reading platen glass.

[Synchronization signal timing chart] FIG. 3 shows a timing chart of the synchronization signal in the apparatus of this embodiment. Reference numeral 401 is a timing chart showing the timing of the main scanning, 402 is a timing chart showing the timing of the sub scanning in the short section, and 403 is a timing chart showing the timing of the sub scanning in the long section. The details will be described below.

First, at 401 indicating the timing of main scanning, the CLK signal is the basic clock signal in this embodiment, and the image processing is performed in pixel units in synchronization with the rising edge of the CLK signal. The HSYNC signal is a main scanning synchronization signal, and the start of main scanning is synchronized with the rising edge of the HSYNC signal. The CLK4 signal is a signal obtained by dividing the CLK signal by four, and together with the CLK signal, the determination circuit 3 shown in FIG.
This is a signal for synchronizing the basic operation of 09. The XPHS signal is a main scanning phase signal, and corresponds to the CLK4 signal.
This signal repeats 0 to 3.

XD0 is a signal which becomes "0" when the XPHS signal is "0" and becomes "1" when the XPHS signal is other than "0". XD1 is a signal that becomes "0" when the XPHS signal is "1" and becomes "1" when the XPHS signal is other than "1". The XD2 is a signal that becomes "0" when the XPHS signal is "2" and becomes "1" when the XPHS signal is other than "2". XD3 is a signal that becomes "0" when the XPHS signal is "3" and becomes "1" when the XPHS signal is other than "3".

In 402 of FIG. 3, the YPHS signal is a sub-scanning phase signal, and values 0 to 3 are repeatedly output in synchronization with the rising edge of the HSYNC signal. The HS4 signal is a signal obtained by frequency-dividing the HSYNC signal by 4 so as to be "1" for one cycle width of the CLK4 signal. YD0 is YP
If the HS signal is "0", it becomes "0", and YPHS
It is a signal that becomes "1" when the signal is other than "0". YD1 is a signal that becomes "0" when the YPHS signal is "1" and becomes "1" when the YPHS signal is other than "1". YD2 is a signal that becomes "0" when the YPHS signal is "2" and becomes "1" when the YPHS signal is other than "2". YD
3 is a signal which is "0" when the YPHS signal is "3" and is "1" when the YPHS signal is other than "3".

In 403 of FIG. 3, the VS signal is a sub-scan enable signal, and magenta (M), cyan (C), yellow (Y), black (B) in the section of "1".
Image formation is performed in the order of k). The CNO signal is the above-mentioned frame sequential signal, and is 0, in synchronization with the rising edge of the VS signal.
It takes the values of 1.2 and 3. [Unit of determination] The determination processing in the determination circuit 309 shown in FIG. 2 is performed in units of 4 × 4 pixel blocks. FIG. 4 shows a 4 × 4 pixel block. 4 as shown at 501 in FIG.
The determination processing is performed in the × 4 pixel block, and the XPHS described above in the main scanning direction is synchronized with the 4 × 4 pixel block.
The signal repeats the values of 0, 1.2 and 3, and the YPHS signal described above repeats the values of 0, 1.2 and 3 in the sub-scanning direction.

In this embodiment, when the YPHS signal is "0", "1", "2", and "3", the determination conditions are determined by time division with respect to eight different determination conditions. A total of 32 types of determination conditions are determined. [Normal Operation Mode and Test Mode] Further, the image processing mode in this embodiment is divided into a normal operation mode and a test mode.

In the test mode, "specific document" is set in advance.
By reading a test document created by imitation and performing a judgment operation, the operation of the image scanner and the judgment circuit is confirmed. (Test Original) FIG. 75 shows an example of the test original used in this embodiment. The test manuscript is a copy of the target specific manuscript, and is created to have characteristics similar to those of the particular manuscript. In this embodiment, major countries (for example, Japan, US,
(British, French, German, etc.) Main bills are targeted, but with some exceptions, the features common to many of these main bills are as follows.

That is, most of the main banknotes are drawn by line drawings of plural colors, and the pitch thereof is about 2 / mm to 6 lines.
/ mm. Therefore, the determination circuit 309 of this embodiment is also designed in consideration of this feature. Therefore, as a test document, a document containing a pattern drawn with a line drawing of multiple colors of approximately 2 lines / mm to 6 lines / mm should be used as the test document.

(Timing Chart showing Flow of Test Mode) The flow chart shown in FIG. 76 is a flow chart showing the operation of the above-mentioned test mode of this embodiment. The test mode processing of this embodiment will be described below with reference to FIG. When the apparatus power is turned on in step 6101, the process moves to the process of FIG. 76, and in step 6102, it is determined whether the operation mode is the normal operation mode or the test mode.
This determination is made based on whether or not there is a specific key input from the operation unit immediately after the power is turned on. FIG. 77 shows the appearance of the operation unit of the apparatus of this embodiment.
"*", "1", "2", "3", "3", "2",
If "1" or "*" is input, it is determined to be the test mode, and if not, the normal operation mode is set.
If it is determined in step 6102 that the operation mode is the normal operation mode, the process proceeds to step 6103 to set the normal operation mode. (Detailed description will be given later.) In a succeeding step 6104, it is determined whether or not the copy start key is pressed. If it is determined in step 6104 that copy start has been pressed, step 61
In step 05, the bill detecting operation process is executed. Then, the process returns to step 6104.

On the other hand, if it is determined in step 6102 that the mode is the test mode, the flow advances to step 6106 to set the test mode. (Detailed description will be given later.) In a succeeding step 6107, it is determined whether or not the copy start key is pressed. If it is determined in step 6107 that the copy start key has been pressed, the test document detection operation processing in step 6108 is executed. Then, the process returns to step 6107.

[Determination Circuit 309] FIG. 5 shows a detailed block diagram of the determination circuit 309 of this embodiment. In FIG. 5, R, G and B signals which are digital color image signals are input in synchronization with the CLK signal and the HSYNC signal,
The determination result is sent to the CPU 311 as a HIT signal.

Reference numeral 101 denotes a coefficient setting circuit, which is a judgment circuit 3
When operating 09, various setting coefficients are held. 102 is a coefficient ROM (hereinafter referred to as "ROM1").
The coefficient to be set in the coefficient setting circuit 101 is held in advance, the ROM 1 (102) is addressed by the address generated by the counter circuit 144, and the coefficient to be set is sequentially set in the coefficient register 148.

Reference numeral 103 is a frequency dividing circuit for dividing the CLK signal and the HSYNC signal, 104 is an image feature extracting circuit for detecting image features in the read original, 105 is a smoothing circuit for smoothing the read image signal, and 106 is 400 dp.
Read image signal input at i (dots / inch) is 100dp
It is a thinning circuit for thinning out to i. Reference numeral 110 denotes a comprehensive determination circuit, which comprehensively determines the presence or absence of a specific document based on the detection results of the image feature extraction circuit 104 and the outputs of the smoothing circuit 105 and the thinning circuit 106.

(Dividing circuit 103) Dividing circuit 3 shown in FIG.
FIG. 6 shows the detailed configuration of 03. In FIG. 6, 601 is an inverter, 602 is a 2-bit counter, the output of the counter 602 is the XPHS described above, and HSYN
The C signal is initialized to "1", that is, "0" at the main scanning reference position, and "0" is synchronized with the rising edge of the CLK signal.
The values of "1", "2", and "3" are repeated. Reference numeral 603 is a 2-input 4-output decoder, and the logic is shown at 603-1. The decoder 603 has a lower bit (bit) of the XPHS signal.
0) and upper bits (bit1) are input, and XD0, X
The signals D1, XD2, and XD3 are output. Furthermore, 6
Reference numeral 04 is an inverter, which inverts the lower bit (bit 0) of the XPHS signal to obtain the CLK4 signal.

By providing the above-mentioned configuration, it is possible to obtain
Each control signal indicated by 01 is obtained. Further, 605 is a 2-bit counter, the output of the counter 605 is the above-mentioned YPH signal, and the values of “0”, “1”, “2”, and “3” are repeated in synchronization with the rising edge of the HSYNC signal. . Reference numeral 606 denotes a NOR gate, which is a lower bit (bit 0) and an upper bit (bit 1) of the YPHS signal.
Is input and its output becomes "1" only when the YPHS signal is "0". Flip-flops 607 and 608 are synchronized with the CLK4 signal.

The AND gate 609 receives the positive logic output of the flip-flop 607 and the negative logic output of the flip-flop 608, and the output of the AND gate 609 is set to 1 of CLK4 at the rising timing of the output of the NOR gate 606. A pulse signal for the clock is output, and this becomes the HS4 signal. The decoder 610 is the decoder 60
It is a 2 to 4 decoder similar to that of No. 3 and has the same logic as the decoder 603 as shown in 603-1. Decoder 610
The low-order bit (bit0) and the high-order bit (bit1) of the YPHS signal are input to the YDHS, YD0, YD1, and YD.
2 and YD3 signals are output.

By providing the above-mentioned structure, 4 in FIG.
The control signal indicated by 02 is obtained. (Image feature extraction circuit 104) FIG. 7 shows a detailed block configuration of the image feature extraction circuit 104 shown in FIG. In FIG. 7, reference numeral 701 denotes an ND circuit, which obtains an ND signal which is a black and white lightness signal from the three primary color signals of R, G and B. (Detailed configuration is shown in FIG. 8.) 702 is a halftone dot removal circuit that removes halftone dot components in the read document, 703 is a line image enhancement circuit that emphasizes line image components in the read document, and 704 is a feature extraction unit. Each of the four types of features (flat component, valley component, line drawing component, edge component) in the read document is extracted.

Reference numeral 705 denotes a post-processing circuit for removing noise from the feature signal extracted by the feature extraction unit 704, and 706 each of the detected four types of features (flat component, valley component,
A selection circuit for selecting a necessary signal from the line drawing component and the edge component), and the selection circuit 706 uses a selection criterion such that the characteristics of the specific original can be most specified according to the type of the specific original to be determined. Select.

(ND Circuit 701) FIG. 8 shows the ND circuit shown in FIG.
3 shows a detailed block diagram of circuit 701. N as shown in FIG.
The D circuit 701 obtains an ND signal which is a black and white lightness signal from the R, G and B primary color signals. 801,80
2 and 803 are (A × B / 1
6) is a multiplier, 804 is an adder that outputs (A + B + C) to three inputs of A, B, and C, and 805 is a flip-flop for synchronizing with the CLK signal. On the other hand, Gr,
Gg and Gb are preset values and are set by the count determination circuit 101, and as a result, the input signals R and
With respect to G and B, an ND signal representing light and darkness of black and white is generated by an expression represented by the following expression (1).

ND = R × Gr / 16 + G × Gg / 16 + B × Gb / 16 (1) (Dot removal circuit 702) FIGS. 9 and 10 show a dot removal circuit 702 shown in FIG. 3 shows a detailed block configuration diagram of FIG. The purpose of the halftone dot removal circuit 702 is to remove only the halftone dot component in the original document and improve the accuracy of the line drawing determination in the latter stage, the details of which will be described later.

In FIG. 9, reference numeral 901 denotes an inverter, and 90
2 and 903 are FIFOs (First
In First Out) memory (for example, it can be composed of Mitsubishi Electric M66251 or the like). Here, the HSYNC signal is logically inverted by the inverter 901 and input to the reset terminals of the FIFO memories 902 and 903.
The O memories 902 and 903 are initialized (reset) line by line.

The ND signal input is input to the FIFO memory 902, and is output as the ND1 signal after being delayed by one line in the FIFO memory 902. The ND1 signal is output as the ND2 signal after being delayed by one line by the FIFO memory 903. Further, the ND signal is the flip-flop 90.
4,905,906 delays pixel by pixel and E1
1, E12, E13 signals, the ND1 signal is delayed by one pixel by the flip-flops 907, 908, 909 to become E21, E22, E23 signals, and the ND2 signal is delayed by one pixel by the flip-flops 910, 911, 912. It becomes E31, E32, E33 signals.
These nine signals form a 3 × 3 pixel window as shown in FIG.

That is, the pixel of interest (Xi, j) and peripheral pixels (Xi-1, j-1), (Xi-1, j), (Xi-1, j + 1), (X
i, j-1), (Xi, j + 1), (Xi + 1, j-1), (Xi + 1, j
), (Xi + 1, j + 1). These nine signals from FIG. 9 are sent to the calculators 913, 914, 915, 916 shown in FIG. The computing units 913 to 916 compute (A + C) / 2 and | A + C−2C | / 2 with respect to three inputs of A, B, and C, respectively, and output them. Therefore, the computing unit 913 calculates that Y0 = (E11 + E33) / 2 and e0 = | E11 + E
33.2E22 | / 2 is output. Here, Y0 is 3 × 3 shown in FIG. 11 described above.
The pixel is subjected to a strong smoothing process in the upper left lower right direction on the window, and e0 is the absolute value of the second derivative amount in the upper left lower right direction and represents the edge strength in the same direction.

The arithmetic unit 914 calculates that Y1 = (E12 + E32) / 2 and e1 = | E12 + E.
32-2E22 | / 2 is output. Here, Y1 is 3 × 3 shown in FIG. 11 described above.
What is strongly smoothed in the vertical direction on the window of pixels, e1 is the absolute value of the second-order differential amount in the vertical direction, and represents the strength of the edge in the same direction.

The computing unit 915 calculates that Y2 = (E13 + E31) / 2 and e2 = | E13 + E.
Outputs 31-2E22 | / 2. Here, Y2 is 3 × 3 shown in FIG. 11 described above.
A pixel that has been strongly smoothed in the lower left and upper right directions on the window, e2 is the absolute value of the second derivative amount in the lower left and upper right directions, and represents the edge strength in the same direction.

The computing unit 915 calculates that Y3 = (E21 + E23) / 2 and e3 = | E21 + E.
23-2E22 | / 2 is output. Here, Y3 is 3 × 3 shown in FIG. 11 described above.
What is strongly smoothed in the left-right direction on the pixel window, e3 is the absolute value of the second-order differential amount in the left-right direction, and represents the edge strength in the same direction.

Reference numerals 917, 918 and 920 are comparators, and 919 is a comparator.
Is a 2-input 1-output selector, and the logic of the selector 919 is shown in 919-1. Here, the output s of the selector 919
0 and the output s1 of the comparator 920 are e0, e1, e
Due to the magnitude relationship between 2 and e3, the following values result. That is, when e0 is the minimum value of e0, e1, e2, e3, s0 = 0, s1 = 0, and e1 is e0, e1,
When the minimum values of e2 and e3 are obtained, s0 = 1, s1 =
0, and when e2 is the minimum value of e0, e1, e2, and e3, s0 = 0 and s1 = 1, and e3 is e0,
When the minimum values of e1, e2, and e3 are obtained, s0 = 1,
s1 = 1.

Reference numeral 921 denotes a 2-input 4-output decoder circuit, and the logic of the decoder circuit 921 is shown by 921-1. 9
Reference numeral 22 is a multiplexer with four inputs and one output. The decoder 921 is provided with s from the selectors 919 and 920 described above.
0, s1 are input, and four outputs from the decoder 921 and Y0, Y1, Y2, and Y3 signals from the arithmetic units 913 to 916 are input to the multiplexer 922 as shown in FIG.

As a result, e0 is e0, e1, e2, e
When the minimum value of 3 is reached, Y is output from the multiplexer 922.
0 is output. When e1 is the minimum value of e0, e1, e2, e3, the multiplexer 922 outputs Y1. When e2 is the minimum value of e0, e1, e2, and e3, the multiplexer 922 outputs Y2, and e2
When 3 is the minimum value of e0, e1, e2, e3,
Y3 is output from the multiplexer 922.

That is, 2 in 8 directions centering on the target pixel Xi, j
The second derivative is calculated, and strong smoothing is performed in the direction of the minimum of these four second derivative amounts.
Is output as the NE signal in synchronization with the rising edge of the CLK signal. The effect of these treatments is shown in FIG. For example, in the line drawing pattern 1101 shown in FIG.
Although the secondary differential amount in the vertical direction (e1 in FIG. 10) takes the minimum value among the secondary differential amounts in the four directions, and strong vertical smoothing processing (Y1 in FIG. 10) is performed, 1102
The line drawing is saved as shown in. Similarly in other directions (left, right,
The line drawings in the upper left lower right and the lower left upper right are similarly saved. On the other hand, the pattern of halftone dots indicated by 1103 is removed as indicated by 1104. In this way, the halftone dot component can be removed without damaging the line drawing component.

(Line Drawing Enhancement Circuit 703) The line drawing enhancement circuit 703 shown in FIG. 7 is the output NE of the halftone dot removal circuit 702 described above.
This is a circuit that receives a signal and emphasizes a line drawing component, and details thereof are shown in FIGS. 13 and 14. First, in FIG.
01 is an inverter, and 1202 and 1203 are FIFO memories for delaying one line. HSYNC here
The signal is logically inverted by the inverter 1201 and
It is input to the reset terminals of the O memories 1202 and 1203, and the FIFO memories 1202 and 1203 are initialized (reset) line by line. The NE signal input is input to the FIFO memory 1202 and is output as the NE1 signal after delaying one line. The NE1 signal is stored in the FIFO memory 12
After being delayed by one line by 03, it is output as the NE2 signal.

The NE signal is the flip-flop 1204.
One pixel is delayed by each of 1205 and 1206, resulting in AE11, AE12, and AE13 signals. Also N
The E1 signal is the flip-flops 1207, 1208, 1
It is delayed by 1 pixel by 209, and AE21, AE2
2, AE23 signal. Further, the NE2 signal is delayed by one pixel by the flip-flops 1210, 1211 and 1212 and becomes AE31, AE32 and AE33 signals. With these nine signals, 3 as shown in FIG.
Form a window of x3 pixels.

Of the above nine signals shown in FIG. 13, eight pixels (Xi-1, j-1), (Xi-1, j) surrounding the pixel of interest (Xi, j) shown in FIG. (Xi-1, j + 1),
(Xi, j-1), (Xi, j + 1), (Xi + 1, j-1), (Xi +
1, j), and signals AE11, AE corresponding to (Xi + 1, j + 1)
12, AE13, AE21, AE23, AE31, AE
32 and AE33 are sent to the maximum value / minimum value detectors 1213, 1214, 1215, 1216 shown in FIG.

Maximum value / minimum value detector 1213, 121
4, 1215 and 1216 output the maximum value max and the minimum value min for the two inputs A and B, respectively. Further, 1217, 1219, and 1221 are maximum value detectors, respectively, which output the maximum value max for two inputs A and B. Reference numerals 1218, 1220 and 1222 denote minimum value detectors, which output the minimum value min with respect to the two inputs A and B. Therefore, the output MX signal of the maximum value detector 1221 includes signals AE11 and AE1 corresponding to eight peripheral pixels.
2, AE13, AE21, AE23, AE31, AE3
2, the maximum value of AE33 is selectively output, and the minimum value detector 1
The output MN signal of 222 includes signals AE11, AE12, AE13, AE21, AE2 corresponding to eight peripheral pixels.
The minimum value of 3, AE31, AE32, and AE33 is selectively output.

Further, reference numeral 1223 denotes an adder for adding the MX signal and the MN signal, and the average value (M
X + MN) / 2 is output. 1224 is an adder 122
The value of (MX + MN) / 2 from 3 and the target pixel (Xi, j)
Is a comparator for comparing the value of the AE22 corresponding to, and a reference numeral 1225 is a 2-input 1-output selector whose operation logic is 122
It is shown in 5-1.

As a result, the output of the selector 1225 is A
When E22> (MX + MN) / 2 (that is, AE22-
If MN> MX-AE22), MX is output.
When AE22 ≦ (MX + MN) / 2 (that is, AE
22-MN≤MX-AE22), MN is output. The output of the selector 1225 is output as an NF signal through the flip-flop 1226.

With the above configuration, the value at the target pixel AE22 is either the maximum value MX of the peripheral pixel group or the minimum value MN of the peripheral pixel group, whichever is closer (the difference The pixel of interest can be replaced by the value of (smaller). The effect of the above operation is shown in FIG. That is, in the case of the pattern as shown by 1301 in FIG. 15 (a broken-line cross-sectional graph is shown by 1302), the change point of the density is replaced by the maximum value or the minimum value of the peripheral pixels, whichever is closer.
A pattern as shown in 303 (a broken line cross-section graph
4). Therefore, the blunting of the signal due to the characteristics of the reading element is eliminated, and as a result, the line drawing pattern is emphasized.

(Feature Extraction Circuit 704) Next, the detailed configuration of the feature extraction circuit 704 shown in FIG. 7 will be described with reference to FIGS. 16 to 21 show the feature extraction unit 704.
3 is a block diagram showing a detailed configuration of FIG. Feature extraction unit 704
Receives the output NF signal of the line drawing enhancement circuit 703 and extracts four types of features (line drawing portion, flat portion, edge portion, and valley portion) of the pixel of interest from the read image signal.

In FIG. 16, 1401 is an inverter,
Reference numerals 1402, 1403, 1404 and 1405 are FIFO memories for delaying one line, respectively. Here, the HSYNC signal is logically inverted by the inverter 1401 and input to the reset terminals of the FIFO memories 1402-1405 to initialize (reset) the FIFO memories 1402-1405 line by line.

The NF signal input is input to the FIFO memory 1402, delayed by one line, and output as the NF1 signal. The NF1 signal is output as the NF2 signal after being delayed by one line by the FIFO memory 1403. Similarly, the NF2 signal is output as the NF3 signal after being delayed by one line by the FIFO memory 1404. Furthermore, the NF3 signal is set to 1 by the FIFO memory 1405.
After being delayed by the line, it is output as an NF4 signal.

Further, the NE signal is the flip-flop 140.
6, 1407, 1408, 1409, 1410 sequentially delays one pixel at a time, and BE11, BE12, BE1
3, BE14, and BE15 signals. The NE1 signal is the flip-flops 1411, 1412, 1413, 141.
4, 1415 are sequentially delayed by one pixel, and BE2
1, BE22, BE23, BE24, BE25 signals. The NE2 signal is the flip-flops 1416 and 141.
7, 1418, 1419, 1420 sequentially delays by one pixel, BE31, BE32, BE33, BE3.
4, BE35 signal. The NE3 signal is the flip-flops 1421, 1422, 1423, 1424, 1425.
Are sequentially delayed by one pixel, and BE41, BE42,
The BE43, BE44, and BE45 signals are obtained. Furthermore, NE
The four signals are flip-flops 1426, 1427, 142.
8, 1429, 1430 sequentially delays by one pixel, BE51, BE52, BE53, BE54, BE5.
There are 5 signals.

These 25 signals in total form a 5 × 5 pixel window as shown in FIG. That is, it is a window composed of a total of 25 pixels of 5 × 5 pixels including a range of ± 2 pixels vertically and horizontally centering on the pixel of interest (Xi, j) and peripheral pixels. The flatness determination circuit, which is one of the feature quantities, will be described below. In FIG. 17, 1431 is a maximum / minimum detector, which has five inputs A, B, C,
The maximum value max (A, B, C, D, E) and the minimum value min (A, B, C, D, E) are output for D and E.
BE11, BE corresponding to pixels delayed by one line at the same main scanning position with respect to the maximum / minimum value detector 1431
21, BE31, BE41, BE51 are input, and their maximum and minimum values are output. In other words,
In FIG. 22, (Xi-2, j-2), (Xi-1, j-2), (Xi-2, j-2)
i, j-2), (Xi + 1, j-2), and (Xi + 2, j-2), the maximum and minimum values of the values of the pixels are calculated.

Further, the detected maximum value is sequentially delayed in pixel units by flip-flops 1432, 1433, 1434, 1425 and output as M1, M2, M3, M4, M5. Similarly, the minimum value detected is the flip-flops 1437, 1438, 1439, 1440, 14
41 are sequentially delayed in pixel units, and N1, N2, N
It is output as 3, N4, N5.

Further, M1, M2, M3, M4 and M5 are
The maximum value detector 1442 shown in FIG.
The maximum value of M5 is calculated and output as an MM signal. on the other hand,
N1, N2, N3, N4 and N5 are input to the maximum value detector 1443 shown in FIG. 18, and the minimum values of N1 to N5 are calculated and output as the NN signal. As a result, the MM signal shows the maximum value within the window of 5 × 5 pixels shown in FIG. 22, and the NN signal shows the minimum value within the window of 5 × 5 pixels shown in FIG. 1444 shown in FIG.
Is a subtracter and outputs the value of MM-NN. And
The flip-flop 1445 synchronizes with the CLK signal and outputs the YB signal.

Reference numeral 1446 is a comparator, which compares the value TH preset by the coefficient setting circuit 101 shown in FIG. 5 with the YB signal from the flip-flop 1445. The comparison result of the comparator 1446 is output as an H signal via the flip-flop 1446. That is, YB <
If TH, H = 1, and if YB ≧ TH, H =
It becomes 0.

The operation of the above configuration will be described below. In FIG. 22, when the neighborhood of the pixel of interest (Xi, j) is flat, the values of the pixels in the 5 × 5 window are close to each other, and the difference between the maximum value MM and the minimum value NN in the window is small. As a result, H = 1. On the other hand, when the neighborhood of the pixel of interest (Xi, j) is not flat, the values of the pixels in the 5 × 5 window vary widely, resulting in a difference between the maximum value MM and the minimum value NN. And H = 0. That is, H = 1 if the neighborhood of the target pixel (Xi, j) is flat, and H = 0 if the neighborhood of the target pixel (Xi, j) is not flat. From this, it can be said that the H signal from the flip-flop 1446 is a flatness determination signal.

Next, with reference to FIGS. 19 to 21, the edge determination circuit, line drawing determination circuit, and valley determination circuit using the incoming signal described above of the feature extraction circuit 704 will be described. 19 shows an edge determination circuit, FIG. 20 shows a line drawing determination circuit, and FIG. 21 shows a valley determination circuit. The edge determination circuit is an arithmetic unit 1501, 1502, 150 shown in FIG.
3, 1504, maximum value detection circuit 1505, comparator 150
6 and a flip-flop 1507.

Computing units 1501, 1502, 1503, 1
504 is max for each of three inputs A, B, C
Output (A, C) -B. The computing unit 1501 is shown in FIG.
EB11, EB33, EB55, that is, three pixels corresponding to (Xi + 2, j + 2), (Xi, j), and (Xi-2, j-2) in FIG. The value of every 3 pixels) is input, and EBY1 = max (EB11, EB55)
-EB33 is output. The computing unit 1502 has a configuration shown in FIG.
EB13, EB33, EB53, that is, 3 corresponding to (Xi, j + 2), (Xi, j), and (Xi, j-2) in FIG.
The value of one pixel (every third pixel in the vertical direction) is input, and EBY2 = max (EB13, EB53) -EB3
3 is output.

The arithmetic unit 1503 has an EB1 shown in FIG.
5, EB33, EB51, that is, (Xi + 2, j-2 in FIG.
), (Xi, j), and (Xi-2, j + 2), the values of three pixels (every other three pixels in the upper right direction) are input, and EBY3 = max (EB15, EB51) -EB3.
3 is output. The computing unit 1504 has an EB from FIG.
31, EB33, EB35, that is, (Xi + 2, j in FIG.
), (Xi, j), and (Xi-2, j), the values of three pixels (every other pixel in the horizontal direction) are input, and EBY is input.
4 = max (EB31, EB35) -EB33 is output.

The principle of edge detection in the above configuration is
It demonstrates below using FIG. In FIG. 23, 17
When there is a pattern as shown in 01, the value in the cross section indicated by the chain line is shown at 1702, and the value of EBY4 is shown at 1703. Although detailed description is omitted, as indicated by 1703, the value of EBY4 becomes large at the edge portion where the density changes in the horizontal direction.

Similarly, the value of EBY2 increases at the edge portion where the density changes in the vertical direction, the value of EBY1 increases at the edge portion where the density changes to the upper left diagonal, and the value of EBY1 increases to the upper right. EB at changing edges
The value of Y3 becomes large. Also, the maximum value detection circuit uses the maximum value max (EBY1, EBY2, EB) of these four values.
Y3, EBY4) is output. These outputs have a large value when an edge component exists in any of the four directions (horizontal direction, vertical direction, diagonally left upward direction, diagonally right upward direction), and the comparator shown in FIG. 1506, a value TE predetermined by the coefficient setting circuit 101
And the result of the comparison is
It is output as an E signal through the line 7.

That is, max (EBY1, EBY2, EB
When Y3, EBY4)> TE, E = 1 and ma
x (EBY1, EBY2, EBY3, EBY4) ≦ TE
In the case of, E = 0. In other words, if the pixel of interest (Xi, j) in FIG.
= 1 and E = 0 if the pixel of interest (Xi, j) in FIG. 22 is not an edge portion. From this, it can be said that the E signal is an edge determination signal.

Next, the line drawing determination circuit and the valley portion detection circuit will be described. In FIG. 20 showing the line drawing determination unit,
1508, 1509, 1510, 1511, 1512,
Reference numerals 1513, 1514, and 1515 are arithmetic units, and for three inputs A, B, and C, min (A, C) -B
-| A-C |, and B-max (A, C)-| A-C |
And output. 1516 is a maximum value detector, 15
Reference numeral 17 is a minimum value detector, 1518 is a subtracter, 1519 and 1520 are comparators, 1521 is an AND gate, 152
2 is a flip-flop, 1522 is a maximum value detector, 1523 is a minimum value detector, 1524 is a subtractor, 15
Reference numeral 25 is a comparator, and 1526 is a flip-flop.

The arithmetic unit 1508 is provided with EB1 from FIG.
1, EB33, EB44, that is, (Xi + 2, j + 2 in FIG.
), (Xi, j), and (Xi-1, j-1) corresponding to the values of three pixels (three pixels in the upper left diagonal direction) are input, and Y11 = min (EB11, EB44) -EB33- |
EB11-EB44 | Y21 = EB33-max (EB11, EB44)-|
The value of EB11-EB44 | is output.

The arithmetic unit 1509 has an EB1 shown in FIG.
3, EB33, EB43, that is, 8Xi, j + 2 in FIG.
), (Xi, j), and the values of three pixels (three pixels in the vertical direction) corresponding to (Xi, j-1) are input, and Y12 = min (EB13, EB43) -EB33- |
EB13-EB43 | Y22 = EB33-max (EB13, EB43)-|
The value of EB13-EB43 | is output.

The arithmetic unit 1510 has the EB1 shown in FIG.
5, EB33, EB42, that is, (Xi + 2, j-2 in FIG.
), (Xi, j), and the values of three pixels (three pixels in the upper right direction) corresponding to (Xi-1, j + 1) are input, and Y13 = min (EB15, EB42) -EB33- |
EB15-EB42 | Y23 = EB33-max (EB15, EB42)-|
The value of EB15-EB42 | is output.

The arithmetic unit 15011 has an EB from FIG.
31, EB33, EB34, that is, (Xi, j + 2 in FIG.
), (Xi, j) and (Xi, j-1) corresponding to the values of three pixels (three pixels in the horizontal direction) are input, and Y14 = min (EB31, EB34) -EB33- |
EB31-EB34 | Y24 = EB33-max (EB31, EB34)-|
The value of EB31-EB34 | is output.

The arithmetic unit 1512 is provided with EB2 from FIG.
2, EB33, EB55, that is, (Xi + 1, j + 1) in FIG.
), (Xi, j) and (Xi-2, j-2) corresponding to the values of three pixels (three pixels in the upper left direction) are input, and Y15 = min (EB22, EB55) -EB33- |
EB22-EB55 | Y25 = EB33-max (EB22, EB55)-|
The value of EB22-EB55 | is output.

The arithmetic unit 1513 is provided with EB2 shown in FIG.
3, EB33, EB53, that is, (Xi, j + 1 in FIG.
), (Xi, j), and the values of three pixels (three pixels in the vertical direction) corresponding to (Xi, j-2) are input, and Y16 = min (EB23, EB53) -EB33- |
EB23-EB53 | Y26 = EB33-max (EB23, EB53)-|
The value of EB23-EB53 | is output.

The arithmetic unit 1514 is provided with EB2 from FIG.
4, EB33, EB51, that is, (Xi + 1, j-1) in FIG.
), (Xi, j), and (Xi-2, j + 2) corresponding to three pixels (three pixels in the upper right direction) are input, and Y17 = min (EB24, EB51) -EB33- |
EB24-EB51 | Y27 = EB33-max (EB24, EB51)-|
The value of EB24-EB51 | is output.

The arithmetic unit 15015 has an EB from FIG.
32, EB33, EB35, that is, (Xi, j + 1 in FIG.
), (Xi, j), and (Xi, j-2) corresponding to three pixels (three pixels in the horizontal direction) are input, and Y18 = min (EB32, EB35) -EB33- |
EB32-EB35 | Y28 = EB33-max (EB32, EB35)-|
The value of EB32-EB35 | is output.

FIG. 24 shows the principle of detecting a line drawing pattern with the above configuration. For example, in the case of a vertical line drawing pattern as shown by 1801 in FIG. 24, the image signal of the cross section shown by the chain line becomes as shown by 1802. On the other hand, FIG.
Value of Y14 is 1803, and the value of Y18 is 1804
Shown in. In addition, the maximum value max (Y1
The value of 4, Y18) is shown at 1085. As shown in FIG. 24, the value of max (Y14, 18) becomes large in the vertical line drawing portion.

A characteristic feature here is that Y14 and Y18 do not take large values in a line drawing pattern having a line width of 3 pixels or more as shown in FIG. 25 or a simple edge as shown in FIG. Is. Therefore, according to the above-described arithmetic expression of the present embodiment, it is possible to accurately capture a thin line drawing on many major national banknotes and securities. Also, in the case of this line drawing pattern in the vertical direction, although not shown, the values of Y12 and Y16 are both small. A line drawing pattern other than the vertical direction is detected by the output of any of the other arithmetic units.

In consideration of the above points, in this embodiment, FIG.
The difference between the maximum value detected by the maximum value detection circuit 1516 and the minimum value detected by the minimum value detection circuit 1517 is obtained by the subtractor 1518 shown in FIG. 1, and is preset by the coefficient setting circuit 101 shown in FIG. 5 by the comparators 1519 and 1520. Value TS1,
Compared with TS2, the comparison result is flip-flop 1522
It is configured to be output via.

With the above configuration, in the present embodiment, the output of the maximum value detection circuit 1516 shown in FIG. 21 is large, the output of one of the arithmetic units is small, and the output of the minimum value detection circuit 1517 is small. Will be things. Therefore, the value of the output ES signal of the subtractor 1518 that subtracts the minimum value from the maximum value becomes large. On the other hand, 200 in FIG.
In the case of the halftone dot pattern as shown in Fig. 1, the value of the output min (A, C) -B- | A-C | of the computing unit may be large, but there is no directivity, A large value is output in any of the two directions (horizontal, vertical, diagonally upward left, diagonally right upward). Therefore, FIG.
Maximum value detection circuit 1518 and minimum value detection circuit 151 shown in FIG.
There is not much difference in the output of 7. As a result, the value of the output ES signal of the subtractor 1518 becomes smaller.

As a result, in the case of the line drawing pattern, the value of the ES signal output from the subtractor 1518 becomes large. That is, the comparators 1519 and 1520 are compared with the values TS1 and TS2 (TS1> TS2) preset by the coefficient setting circuit 101 shown in FIG.
As a result, S = 1 when TS2 <ES <TS1, and S = 0 when ES ≦ TS2 or TS2 ≦ ES.
Becomes

In order to detect only many line drawings of major banknotes and securities, the distribution of ES signal values in many major banknotes and securities line drawings is checked in advance and a certain fixed value (TS1 and It is possible to improve the determination accuracy by determining that the target pixel (Xi, j) is between TS2), and S = 1 if the target pixel (Xi, j) is a line drawing, and S = 0 if the target pixel (Xi, j) is not a line drawing. Becomes

Next, the valley portion detection will be described. Figure 21
The difference between the maximum value detected by the maximum value detection circuit 1522 and the minimum value detected by the minimum value detection circuit 1523 is obtained by the subtractor 1524 shown in FIG. 4, and the coefficient setting circuit 1 shown in FIG.
The value TT is compared with a preset value TT by 01, and the comparison result can be output via the flip-flop 1526.

In FIG. 24, in the pattern 1801, the output results of Y24 and Y28 are set to 1806 and 1807, and the maximum value max (Y24,
The calculation result of Y28) is shown in 1808. As you can see here Y
24 and Y28 are signals that increase in the valley portion in the vertical direction. Further, in the case of the valley pattern in the vertical direction, although not shown, the values of Y22 and Y26 are both small.

Further, in the valley pattern other than the vertical direction, the output of the maximum value detection circuit 1522 shown in FIG. 21 is large because it is detected by the output of any other arithmetic unit, and the output of any arithmetic unit is large. Becomes smaller, and the output of the minimum value detection circuit 1523 becomes smaller. For this reason,
The value of the output ET signal of the subtractor 1524 increases. Further, in the comparator 1525, a comparison result with the value TT set by the coefficient setting circuit 101 in advance is output, and the comparison result T is a determination result as to whether or not the pixel of interest (Xi, j) is a valley portion. It That is, T = 1 if the target pixel (Xi, j) is a valley portion, and S = 0 if the target pixel (Xi, j) is not a valley portion.

(Post-Processing Circuit 705) FIG. 27 shows a detailed block diagram of the post-processing unit 705 shown in FIG. The post-processing circuit 705 performs post-processing on the line drawing portion signal S and the edge portion signal E to remove noise included in the signals. In FIG. 27, reference numeral 4201 is an inverter, and reference numeral 4202 is a FIFO memory for one line delay equivalent to the FIFO memory 902 shown in FIG. Here, the HSYNC signal is logically inverted by the inverter 4201, and the FIFO memory 4
202 is input to the reset terminal of the FIFO memory 42.
02 is initialized (reset) for each line. The flat portion signal H and the valley portion signal T are transferred to the FIFO memory 4202.
Is delayed by one line and output as H1 and T1 signals.

Reference numeral 4203 denotes a line drawing signal post-processing circuit,
Reference numeral 4204 is an edge signal post-processing circuit. Three signals SS1, SS2, and SS3 are input to the line drawing portion signal post-processing circuit 4203. The SS1 signal is the same signal as the S signal, the SS2 signal is a signal obtained by delaying the SS1 signal (that is, the S signal) by one line, and the SS3 signal is a signal obtained by delaying the SS2 signal by one line. In the line drawing section signal post-processing circuit 4203, the output signal S1 is calculated from these input signals.
To get

The edge signal post-processing circuit 4204 has an EE
Three signals of 1, EE2 and EE3 are input. EE1
The signal is the same signal as the E signal, the EE2 signal is a signal obtained by delaying the EE1 signal (that is, the E signal) by one line, and the EE3 signal is a signal obtained by delaying the EE2 signal by one line. In the edge signal post-processing circuit 4204, the output signal E1 is obtained by calculation from these input signals. (Line drawing non-signal post-processing circuit 4203) FIG. 28 is a detailed block diagram of the line drawing section signal post-processing circuit 4203 shown in FIG.
Through FIG. 31.

Reference numerals 4301 to 4309 shown in FIG. 28 are flip-flops, which give a delay of one pixel unit. Then, the SS1 signal is the flip-flop 4301,
ED1 after being delayed by one pixel by 4302 and 4303
1, ED12, ED13 signals, SS2 signal is delayed by one pixel by flip-flops 4304, 4305, 4306 to become ED21, ED22, ED23 signals, and SS3 signal is flip-flops 4307, 430.
Delayed by 1 pixel by 8, 4309 and ED31, E
It becomes the D32 and ED33 signals. With these nine signals,
A window of 3 × 3 pixels as shown in 1 is formed. That is, the target pixel (Xi, j) and the peripheral pixels (Xi-1, j-1)
), (Xi-1, j), (Xi-1, j + 1), (Xi, j-1),
(Xi, j + 1), (Xi + 1, j-1), (Xi + 1, j), (Xi +
It is a window composed of 1, j + 1).

Inputting these nine signals, 4320, 4321, 4322, 4323, 432 shown in FIG.
4, 4326 and 4327 are 2 inputs 1 output NA
ND gate, 4328, 4329, 4330, 4331
Are 4-input 1-output NAND gates 4332,
4333, 4334, 4335, 4346, 4347,
4348 and 4349 are 2-input 1-output NANDs, respectively
Gates 4340, 4341, 4342, and 4343 are 2-input 1-output NAND gates, respectively.

Now, considering the case where the output of the NAND gate 4333 becomes "1", the NAND gate 432.
This is the case where the output of any one of 0, 4321, 4322, and 4323 becomes "1" and the value of ED22 becomes "1". When this is shown by the image of the 3 × 3 pixel window shown in FIG. 11, it is 4346-1, 4344-2, 43.
In the patterns 46-3 and 4346-4, the output of the NAND gate 4333 becomes "1".

In FIG. 29, the mark ■ indicates "1" and the mark □
The mark indicates that it may be "1" or "0". Also, NA
The output of the ND gate 4332 takes the value of “1” in the pattern shown in 4346-5, and the NAND gate 434 has the same value.
0 output, that is, Y0 signal is 4346 (4346-1,4
346- 2,4346- 3,4346- 4,4346-
It becomes "1" in the five patterns shown in 5), and becomes "0" in other cases. Here, according to these five patterns, the line drawing portion in the left-right direction becomes "1". That is, a line drawing continuous to three pixels (Xi + 1, j, Xi + 1, j + 1, Xi + 1, j + 2) in a straight line on the right and left or a line drawing with a faint pixel is detected at 4346-5. A line drawing slightly bent from the right and left straight lines is 4346-
It is detected at 1,4346-1,2346-3,4346-4. That is, it can be said that the Y0 signal is a line drawing portion determination signal in the left-right direction.

Similarly, the Y1 signal is 5 shown at 4347.
It becomes "1" in one pattern and becomes a line drawing portion determination signal in the lower left upper right direction. The Y2 signal becomes "1" in the five patterns 4348, and becomes the line drawing portion determination signal in the vertical direction.
The Y3 signal becomes "1" in the five patterns shown in 4349, and becomes the line drawing portion determination signal in the upper left lower right direction. Furthermore, Y
The signals of 0, Y1, Y2 and Y3 are flip-flops 43
At 44, the signal is synchronized with the rising edge of the CLK signal and output as the SF signal. The SF signal is also input to a FIFO memory (for example, TMS4C1060 manufactured by TEXAS INSTRUMENTS) 4345.

On the other hand, the FIFO memory 4345 is reset by the FRST signal in the figure. (The above TEXAS INSTRUME
The reset input of NTS TMS4C1060 is positive logic. )
As shown in FIG. 32, the FRST signal is a pulse that is repeatedly generated at a period that is 15 times the HSYNC period.
The FIFO memory 4345 will give a delay of 15 lines. Therefore, the SD signal output from the FIFO memory 4345 is the SF signal delayed by 15 lines.

Next, FIG. 30 and FIG. 31 show circuit configurations for counting "1" pixels for each bit of the SF signal described above in a window of 31 × 15 pixels. First, in the circuit shown in FIG. 30, addition in the sub-scanning direction is performed, and
As shown by 4601, the pixels in the 1 × 15 sub-scanning one column are counted. In the circuit shown in FIG. 31, the circuit shown in FIG.
Upon receiving the counting result from the above, addition is performed in the main scanning direction, and addition is performed in a 31 × 15 pixel window as indicated by 4602 in FIG.

In FIG. 30, 4401 is a flip-flop, 4402, 4403, 4404 and 4405 are subtractors, 4405, 4406, 4407, 4408 and 440.
9 is an adder, 4410, 4411, 4412, 4413
Is an AND gate, 4414, 4415, 4416, 44
17, 4418 is a flip-flop, 4419 is a FIF
O memory (for example, M66251 of Mitsubishi Electric Corporation), 4420
Is an inverter, and 4421 and 4422 are flip-flops.

In FIG. 30 having the above configuration, the above-mentioned SF signal has a 4-bit configuration and has four directions (left and right directions,
Lower left upper right direction, vertical direction, upper left lower right direction) line drawing determination signal, and SD signal indicates a signal obtained by delaying the SF signal by 15 lines. Here, in general, the sequence X (i) [i = 1,2,
3, .....], the moving sum Y (i) of N terms of array X (i) is Y (i) = X (i) + X (i + 1) + X (i + 2) + ....... + X (i + N-1) ・ ・ ・ (2) Y (i + i) = X (i + 1) + X (i + 2) + ....... + X (i + N-1) + X (i + N) ・ ・ ・ (3), and Y (i + 1) = Y (i) + (X (i + N) -X (i)} (4)

On the other hand, as the initial value of X (i), X (1) = X (2) = X
When (3) = .... = X (N) = 0, Y (1) = 0 is fixed, so Y (2) = Y (1) + (X (1 + N) -X (1)} ・ ・ ・ (5) Y (3) = Y (2) + {X (2 + N) -X (2)} ・ ・ ・ (6): Y (i + 1) = Y (i ) + {Y (i + N) -Y (i)} (7), and Y (i) is sequentially calculated.

Similarly, a two-dimensional array X (i, j) [i = 1,2,
3 ,, ...... j = 1,2,3, ........], Y (i, j) = X (i, j) + X (i + 1, j ) + X (i + 2, j) + ..... + X (i + M-1, j) ・ ・ ・ (8) Y (i + 1, j) = X ( i + 1, j) + X (i + 2, j) + ..... + X (i + M-1, j) + X (i + M, j) ・ ・ ・ (9), Y (i + 1, j) = Y (i, j) + {X (i + M, j) -X (i, j)} (10).

On the other hand, as the initial value of X (i, j), X (1, j) = X
When (2, j) = X (3, j) = .... = X (M, j) = 0, Y (1, j) = 0
Y (2, j) = Y (1, j) + {X (1 + M, j) -X (1, j)} ・ ・ ・ (11) Y (3, j) = Y (2, j) + {X (2 + M, j) -X (2, j)} ... (12): Y (i + 1, j) = Y (i, j) + {Y ( i + M, j) -Y (i, j)} (13), and Y (i, j) is sequentially calculated.

Furthermore, Z (i, j) = X (i, j) + X (i + 1, j) + X (i + 2, j) + ..... + X (i + M, j ) + X (i, j + 1) + X (i + 1, j + 1) + X (i + 2, j + 1) + ..... + X (i + M, j + 1) + X (i, j + 2) + X (i + 1, j + 2) + X (i + 2, j + 2) + ..... + X (i + M, j + 2): + X (i, j + N-1) + X (i + 1, j + N-1) + X (i + 2, j + N-1) + ..... + X (i + M, j + N-1) ・ ・ ・ (14) Z (i, j) = Y (i, j) + Y (i, j + 1) + Y (i, j + 2) + .... . + Y (i, j + N-1) ・ ・ ・ (15), Z (i, j + 1) = Y (i, j + 1) + Y (i, j + 2) +. .... + Y (i, j + N-1) + Y (i, j + N) ... (16) and Z (i, j + 1) = Z (i, j) + ( Y (i, j + N) -Y (i, j)} (17)

On the other hand, as an initial value of Z (i, j), Z (i, 1) = Z
When (i, 2) = Z (i, 3) = .... = Z (i, N) = 0, Z (i, 1) = 0 is established, so Z (i, 2) = Z (i, 1) + {Y (i, 1 + N) -Y (i, 1)} ・ ・ ・ (18) Z (i, 3) = Z (i, 2) + {Y (i, 2 + N) -Y (i, 2)} ・ ・ ・ (19): Z (i + 1, j) = Z (i, j) + {Y (i, j + N) -Y (i, j )} ・ ・ ・ (20), Z (i, j) is sequentially calculated.

Applying to the counting in the 31 × 15 window in consideration of the above points, first, as shown by 4601 in FIG. 33, 15 lines are added in the sub-scanning direction, and the addition result is 31 pixels in the main scanning. And add 31 as shown in 4602.
Addition within the window of × 15 is performed. In FIG. 30, if i is the sub-scanning position, j is the main scanning position, and M = 15, then each bit of the SF signal corresponds to the X (i + M, j), and SD
Each bit of the signal corresponds to the X (i, j). Where SF
The signal and the SD signal are divided into each bit through the flip-flop 4401, and the subtractors 4402, 4403,
Subtraction is performed at 4404 and 4405, respectively.
Further, the calculation result of each subtractor is obtained by adding
It is input to the B inputs of 7, 4408 and 4409, and the subtracter and the adder perform the calculation corresponding to the equation (13). The A input of the adder will be described later.

Here, 4410, 4411, 4412, 4
413 is an AND gate, 4414, 4415, 441
6, 4417 and 4418 are flip-flops, 441
9, 4420 is a FIFO memory (for example, M662 of Mitsubishi Electric Corp.)
51), 4420 is an inverter, 4421, 442
2 is a flip-flop. The logic of the HSYNC signal is inverted by the inverter 4420, and the FIFO memory 441 is
It is input to the read reset terminal RSTR of 9, 4420, and is input to the write reset terminal RSTW signal after a delay of two pixels in the flip-flops 4421 and 4422. Therefore, the FIFO memories 4419 and 4420 are provided with a pixel delay of "1 line-2 pixels".

Based on this, the output of the adder 4406 (or 4407, 4408, 4409) is the flip-flop 4415 (or 4415, 4416, 441).
7) delays by 1 pixel, FIFO memory 4419 (or 4420) delays by (1 line-2 pixels), flip-flop 4401 delays by 1 pixel and is input to the A input of adder 4406 (or 4407, 4408, 4409). Is entered. Therefore, together with these delays, the A input of the adder is obtained by delaying the output of the same adder by one line.

Therefore, if the A input of this adder is Y (i, j) in the equation (13), the output can be Y (i + 1, j). On the other hand, since each bit of the SF signal is X (i + M, j) and each bit of the SD signal is X (i, j), the adder 4406 (or the adders 4407, 4408, 4409) (13) above
You're computing an expression. Since the VSYNC signal becomes "0" before the start of the sub-scan, the AND gate 4410 sets X (i, j) = X (i + 1, j) as the initial value of X (i, j). Since = X (i + 2) = ..... = X (i + M) = 0 (where M = 15) is guaranteed, based on the algorithm shown in the equation (13), FIG. The total sum in the 1 × 15 pixel window corresponding to 4601 is calculated. Although the FO output in FIG. 30 is a 16-bit signal, bits 0 to 3 of the FO signal are 1 × with respect to bit 0 of the SF signal.
It becomes the sum within the window of 15, and the FO signal bit 4 to
Bit 7 is the sum within the 1 × 15 window for bit 1 of the SF signal, and bits 8 to 11 of the FO signal are the sum within the 1 × 15 window for bit 2 of the SF signal, and bit 12 of the FO signal. ~ Bit 15 is the sum within the 1 × 15 window for bit 3 of the SF signal. The SF2 signal is obtained by delaying the SF signal by two pixels and synchronizing it with the FO signal.

The circuit shown in FIG. 31 is a circuit for obtaining the total sum indicated by 4602 in FIG. 33 based on the equations (14) to (20). In FIG. 31, reference numeral 4501 denotes a group of 31 flip-flops, 4502, 4503, 4504, and 450.
5 is a subtractor, 4506, 4507, 4508, 4509
Is an adder, and 4510, 4511, 4512, 4513 are flip-flops.

In FIG. 31, the FO signal is delayed by 31 pixels by the flip-flop group 4501,
It becomes an OD signal. Therefore, the FOD signal is converted to the above-mentioned Y (i, j + N)
Then, the FOD signal becomes Y (i, j) as well, and the subtracter 45
02 (or subtractor 4503, 4504, 4505, 4
The calculation result of 506) is the adder 4506 (or the adder 4).
507, 4508, 4509, 4520) is output as Z (i,
If it is written as (j + 1), it is delayed by one pixel by the flip-flop 4510 (or the flip-flops 4511, 4512, 4513) and input to the A input of the adder as Z (i, j).

Therefore, the operation corresponding to the equation (20) is performed, and the content held in the flip-flop group 4501 is initialized to "0" by the HSYNC signal logically inverted by the inverter 4514. Therefore, in the algorithm based on the equation (20), the total sum within the 16 × 31 window indicated by 4602 in FIG. 33 is calculated.

That is, the SU0 signal is the bit 0 of the SF signal.
That is, the Y0 signal, which is a line drawing portion determination signal in the left-right direction, is
SU1 is added in a 6 × 31 window.
The signal is bit 1 of the SF signal, that is, the Y1 signal that is the line drawing portion determination signal in the lower left upper right direction added within the 16 × 31 window, and the SU2 signal is the bi signal of the SF signal.
t2, that is, the Y2 signal which is the vertical line drawing portion determination signal is added within the 16 × 31 window, and SU
The 3 signal is obtained by adding the bit 3 of the SF signal, that is, the Y3 signal, which is the line drawing portion determination signal in the upper left lower right direction, within the 16 × 31 window.

In the system which does not use the algorithm of the present embodiment described above, the circuit shown in FIG. 34 has conventionally been adopted. Although detailed description is omitted, the number of FIFO memories and adders used here is enormous as compared with the present embodiment described above. For example, in terms of the number of adders including subtractors, the above-described circuit of this embodiment is 16 in number, whereas the method of FIG. 34 requires 464 (= 31 × 15−1) adders. Met.

Therefore, when this circuit portion is formed into an LSI, in the case of the present embodiment described above, not only the circuit scale becomes smaller as compared with the conventional example shown in FIG.
The number of inputs and outputs to and from the FO memory and the LSI is reduced (40 in the present embodiment, 64 in the conventional example), which is extremely effective in realizing an LSI. Next, in FIG. 31, 4515,
4516, 4517, and 1518 are 8-bit limiters, which output 255 when the calculated signal values of SU0, SU1, SU2, and SU3 exceed the maximum value of 8 bits, that is, 255, and otherwise. The input value is output as it is. 4519, 4520, 4521, and 4522 are comparators, respectively. Here, TA is the coefficient setting circuit 1
The value is preset by 01, and in 4519, the value of the SU0 signal output through the limiter 4515 and the value of TA are compared. If SU0> TA, “1” is set, and if SU0 ≦ TA, Output "0".

Further, 4523 is an AND gate, and S
The F2 signal is ANDed with bit 0 of the SF3 signal delayed by 16 pixels. The SF3 signal is obtained by adding the operation delay amount of the circuits of FIGS. 30 and 31 to the SF signal, and is the SF signal itself when 4603 of FIG. 33 is the target pixel. Therefore, the output of the AND gate 4523 is that, in the Y0 signal which is the line drawing portion determination signal in the left-right direction, the number of “1” in the 31 × 15 window shown in 4602 of FIG. Four
If the Y0 signal in 603 is "1", it becomes "1", and otherwise it becomes "0". In other words,
This signal is "1" when the pixel of interest itself is a line drawing part in the left-right direction and there are a certain number or more of line drawing parts in the same direction around the pixel of interest.

Similarly, as for the output of the AND gate 4524, in the Y1 signal which is the line drawing portion determination signal in the lower left upper right direction, the number of “1” in the 31 × 15 window 4602 shown in FIG. "1" when the Y1 signal in the target pixel 4603 is large and is "1"
And 0 otherwise. In other words, if the target pixel itself is the line drawing part in the upper left lower right direction, and there are a certain number or more of line drawing parts in the same direction around the target pixel, the value is "1".

The output of the AND gate 4525 is 4 in FIG. 32 in the Y2 signal which is the line drawing portion determination signal in the vertical direction.
If the number of “1” s in the 31 × 15 window shown in 602 is larger than TA and the Y2 signal in the target pixel 4603 is “1”, it is “1”, and otherwise it is “0”. In other words, when the pixel of interest itself is a line drawing part in the vertical direction and there are a certain number or more of line drawing parts in the same direction around the pixel of interest, the value is "1".

The output of the AND gate 4526 is the Y3 signal which is the line drawing portion determination signal in the lower left and upper right direction shown in FIG.
"1" in the 31x15 window shown in 4602
Is larger than TA and the Y3 signal in the pixel of interest 4603 is “1”, it is “1”, and otherwise it is “0”. In other words, when the pixel of interest is the line drawing portion in the lower left upper right direction, and there are a certain number or more of line drawing portions in the same direction around the pixel of interest, the value is "1".

Further, 4527 is an OR circuit, and AND
The outputs of the gates 4523, 4524, 4525, and 4526 are ORed, and the outputs are flip-flops 452.
It is output as S1 signal after passing through 8. Therefore, in the S1 signal, in the 31 × 15 window 4602 shown in FIG. 32, the target pixel 4603 itself is a line drawing part in any direction, and there are a certain number or more of line drawing parts in the same direction around the target pixel. The signal is "1" when it is, and is "0" otherwise.

(Edge signal post-processing circuit 4204) FIG.
5 shows details of the edge signal post-processing circuit 4204 shown in FIG. In FIG. 35, 4801, 4802, 48
03, 4804, 4805, 4806, 4807, 48
08 and 4809 are flip-flops, EC11,
EC12, EC13, EC21, EC22, EC23,
EC31, EC32, and EC33 are obtained by arranging the edge determination signals in the 3 × 3 window shown in FIG.

Further, 4810, 4811, 4812,
4813, 3814, 4815, 4816, 4817,
4818, 4819, 4820 and 4821 are each 2
Input 1 output NAND gate, 4822 is 12 input 1 output NAND gate, 4823 is 2 input 1 output AND
Although it is a gate, detailed explanation is omitted, but as a result, A
The output E00 signal of the ND gate 4823 becomes "1" when the edge part signal has 12 patterns shown in FIG. 36, that is, when the edge part continuously exists around the target pixel including the target pixel. , Otherwise, it becomes “0”.

Further, the E00 signal is the flip-flop 4
824 to be output as an E1 signal. (Selecting circuit 706) FIGS. 37 to 39 are detailed circuit diagrams of the selecting circuit 706 shown in FIG. 7, and FIG. 40 is a timing chart thereof.

In FIG. 37, S1, H1, T1, E1
The signals are the line drawing portion signal, the flat portion signal, the valley portion signal, and the edge portion signal that have been post-processed by the post-processing circuit 706, respectively. 4901, 4902, 4903, 4904 are flip-flops, 4905 is a 2-input 1-output selector (logic is shown in 4905-1), 4906 is a flip-flop, 4907 is an encoder (logic is 4908).
4909 is a 2-input 1-output selector (logic is shown in 4905-1), and 4910 is a flip-flop.

Here, the signals of S1, H1, T1 and E1 in four consecutive pixels are arranged and input to the encoder 4907 as shown in the figure. That is, of the 16-bit X input, bits 15 to 12 have an S1 signal indicating a line drawing portion for four consecutive pixels, and bits 11 to 8 have an H1 signal indicating a flat portion for four consecutive pixels. 〜4 is T1 which shows the valley part about 4 consecutive pixels
An E1 signal indicating an edge portion for four consecutive pixels is input to the signal, bits 3 to 0, and an EC signal is encoded and output.

Here, the logic of the encoder 4907 is 49
08, the logic is that first four consecutive 4
If the S1 signal becomes "1" in a pixel, the value of the coordinate (0 to 3) that becomes "1" for the first time is output, and if the S1 signals in four consecutive pixels are all "0". If the H1 signal becomes “1” in four consecutive pixels,
The value of the coordinate (0-3) that became "1" for the first time is output,
All S1 and H1 signals in 4 consecutive pixels are "0"
In this case, if the T1 signal becomes “1” in four consecutive pixels, the coordinate (0 to 0) that becomes “1” for the first time is displayed.
The value of 3) is output and S1, H1, and T in four consecutive pixels are output.
When all the 1 signals are “0”, if the E1 signal becomes “1” in four consecutive pixels, it is “1” for the first time.
The value of the coordinate (0 to 3) that has become is output, and when the S1, H1, T1, and E1 signals in four consecutive pixels are all "0", "0" is output.

Further, the output of the encoder 4907, E
The C signal is input to the A input of the 2-input 1-output selector 4909. The logic of the selector 4909 is 4905- in the figure.
Shown in 1. The output Y of the selector 4907 is output to the selector 4909 as an EC4 signal through the flip-flop 4910.
Is fed back to the B input of the selector 4909.
The control input S of the XD1 signal is a signal which becomes "0" only when the XPHS signal of the 4-pixel cycle is "1".
(Shown in the figure) is entered. Therefore, EC4 is X
The value of EC when the D1 signal is "0" is latched in the flip-flop 4910 during the interval of 4 pixels.

Reference numeral 4911 denotes a 4-input 1-output selector (logic is shown in 4911-1), the above-mentioned EC4 signal is inputted to the control input S, and X is inputted to each of A, B, C and D inputs.
The D2, XD3, XD0, and XD1 signals are input, respectively. On the other hand, the output of the flip-flop 4904 is input to the A input of the selector 4905, the output of the selector 4911 is input to the control input S of the selector 4905, and the Y output of the selector 4905 is input to the B input of the selector 4905 via the flip-flop 4906. The signal is fed back as a signal, and as a result, the SH4 signal corresponding to the coordinate values of 0 to 3 output from the encoder 4907 is latched in the flip-flop 4906 during the interval of 4 pixels.

Further, 4912 is a 2-input / 1-output selector (logic is 4905-1), 4913 is a flip-flop, 4914 is 2-input / 1-output selector (logic is 490).
5-1), 4915, 4916, 4917, 4918,
4919, 4920, 4921 are flip-flops, 4
Reference numeral 922 is an OR gate. With the above configuration,
In the selection circuit 706, S1, H1, T1, and E1 signals having a resolution of 400 dpi in four consecutive pixels are sampled at a rate of 1/4 and S0, H0, T having a resolution of 100 dpi are sampled.
It is possible to obtain 0 and E0 signals. And at this time,
Instead of simple thinning, sampling can be performed by selecting coordinates such that the input signal is "1".

Further, in synchronization with each signal of S0, H0, T0, and E0, F indicating the sampling point is shown.
The WE signal is output when the YD3 signal is "0".
FIG. 40 shows the above timing charts. Further, the output S0, H0, T0 and E0 are input to the circuits shown in FIGS. 38 and 39. First, in FIG. 38, 500
1,500,5003,5004,5005,500
Reference numerals 6,5007,5008 denote 2-input / 1-output selectors, which are composed of AND gates, NOR gates and inverters as shown in the figure. FZSEL0 and FZSEL1
Is a value preset by the coefficient setting circuit 101.

Similarly, 5009, 5010, 50 of FIG.
11,5012,5013,5014,5015,50
Reference numeral 16 is a 2-input 1-output selector. SZSEL is a value preset by the coefficient setting circuit 101. As will be described later, in this embodiment, the presence / absence of a plurality of types of specific originals is simultaneously determined. Further, the required feature amount is selectively extracted for each of the plurality of types of specific originals. That is, the optimum feature amount is selected according to the type of the specific document.

The selection control is performed by the circuits shown in FIGS. 38 and 39. FZSEL0 in FIGS. 38 and 39,
The selection is controlled by FZSEL1 and SZSEL. The first feature signal FZ and the second feature signal SZ are sent as the feature signals used for the determination. The FZ signal can be selected from three types: (1) flat part (2) valley part (3) flat part or valley part, and SZ signal can be selected from (1) line drawing part signal (2) edge part signal. The choice is considered. The FZ signal and the SZ signal are 8-bit signals, and each bit is used for determination based on eight types of determination conditions that are simultaneously subjected to determination processing.

[Thinning Circuit 106] FIG. 41 shows a detailed circuit diagram of the thinning circuit 106 shown in FIG. 5, and FIG. 42 shows a timing chart thereof. In FIG. 41, 5201 is an inverter, and 5202 and 5203 are FIFO memories (for example, M66251 manufactured by Mitsubishi Electric Corporation). The thinning circuit 106 is 400d
This is a circuit that samples the R, G, and B signals (upper 5 bits each) of pi and thins them out to 100 dpi. As shown in FIG. 42, "0", "1", and
When the value of the YPHS signal that repeats “2” and “3” is “3” (that is, when the YD3 signal is “0”), R,
The G and B signals are written to the FIFO memories 5202 and 5203. That is, it is written once every four lines.

The values of the R, G, B signals are written only when the above-mentioned FWE signal becomes "0". Also, since the written data is thinned out at a rate of 1/4,
The CLK4 signal is used as the clock signal for reading from the FIFO memories 5202 and 5203. By adopting the above circuit configuration, it is possible to perform sampling in which the characteristic pixels are prioritized, rather than the simple thinning-out as described above.

[Smoothing circuit 105] FIG.
FIG. 44 is a circuit diagram of the smoothing circuit 105 shown in FIG. The smoothing circuit 105 performs smoothing by adding and averaging the R, G, and B signals of 400 dpi in the unit of 4 × 4 block 501 shown in FIG. 4 described above.

In FIG. 43, 5401, 5402, 5
403 is an AND gate, 5404, 5405, 5406
Is an adder, 5407, 5408, 5409 are flip-flops, 5410, 5411, 5412 are 2-input 1-output selectors (logic is shown at 5410-1 in the figure), 54
13, 5414, 5415 are flip-flops, 541
Reference numerals 6, 5417 and 5418 denote inverters, 5419 denotes a multiplexer having three inputs and one output, and 5420 denotes a flip-flop.

Further, 5421 and 5422 are FIFO memories (for example, M66251 of Mitsubishi Electric Corporation), 5423 is a flip-flop, 5424 is an AND gate, 5425 is an adder,
5426 is a flip-flop, 5427 is an inverter,
5428, 5429, 5430, 5431, 5432 are flip-flops, 5433 is an OR gate, 5434,
5435 is a FIFO memory (for example, M66251 of Mitsubishi Electric Corporation)
Is.

As shown in the timing chart of FIG. 44,
The value of the output X1 of the flip-flop 5407 is sequentially input R
The signals are cumulatively added by the adder 5404. Also,
The B input of the adder 5407 is once every four pixels (XD1 =
When it is "0", that is, when the XPHS signal is "1", it becomes "0", so that cumulative addition is performed every four pixels.
That is, when the XPHS signal is "0", the input value of the R signal is "r0", when the XPHS signal is "1", the input value of the R signal is "r1", and when the XPHS signal is "2", the R value is If the input value of the signal is “r2” and the input value of the R signal when the XPHS signal is “3” is “r3”, then when the XPHS signal is “1” with a delay of 1CLK signal from these, The X1 signal becomes "r0", the X1 signal becomes "r0 + r1" when the XPHS signal is "2", the X1 signal becomes "r0 + r1 + r2" when the XPHS signal is "3", and the XPHS signal becomes "r0 + r1 + r2". In the case of “0”, the X1 signal becomes “r0 + r1 + r2 + r3”.

Further, this value (rsm = r0 + in FIG. 44)
r1 + r2 + r3) is latched as an X2 signal at the output of the flip-flop 5413 for 4CLK signals. Here, the value of rsm = r0 + r1 + r2 + r3 is the sum of R signals corresponding to four consecutive pixels in the main scanning direction. In exactly the same manner, the output Y2 signal of the flip-flop 5414 is latched by the sum of the G signals corresponding to four pixels continuous in the main scanning direction gsm = g0 + g1 + g2 + g3 for 4CLK signals, and is output to the output Z2 signal of the flip-flop 5415. Is the sum of B signals corresponding to four pixels continuous in the main scanning direction, and the value of bsm = b0 + b1 + b2 + b3 is latched for 4CLK signals.

Furthermore, the multiplexer 54 having three inputs and one output
As shown in FIG. 44, the output SS signal of the flip-flop 5420 via 19 outputs the values of rsm, gsm, and bsm in a time division manner. The SS signal is input to the A input of the adder 5425. The output of the adder 5425 is input to the B input of the adder 5425 via the flip-flop 5426, the FIFO memories 5421 and 5422, the flip-flop 5423, and the AND gate 5425. Where FIFO
In the memories 5421 and 5422, since a delay of (1 line-2 pixels) is realized, the flip-flop 54
23 and the flip-flop 5426 are combined to form a delay of one line, and the adder 5425 performs cumulative addition.

The ratio YD of 1 out of 4 lines is YD
When the 0 signal becomes "0" (that is, the YPHS signal is "0")
In the case of), the output of the AND gate 5424 becomes "0". Therefore, the adder 5424 calculates the cumulative addition value for every four lines. Further, as described above, the SS signal is the sum of the R, G, and B signals that are the input signals in the four main scanning pixels, and therefore the SFSUM signal (output of the adder 5425) and the FI signal (flip-flop 5426) shown in FIG. 4) of the main scanning and sub-scanning 4 pixels
The sum in the × 4 pixel block is output.

Further, the upper 5 bits of the SFI are synchronized with the CLK signal by the flip-flops 5430, 5431 and 5432, respectively, and are SFS1, SFS2 and SFS.
There are 3 signals. In addition, since the SS signal is the sum of the R, G, and B signals, which is sequentially output in time division, SF signal
With respect to each of the I, SFS1, SFS2, and SFS3 signals, the sum of the R, G, and B signals is sequentially output in a time division manner. Here, as shown in FIG. 44, the XPHS signal is "2".
, The SFS1 signal is bs which is the sum of B inputs.
m'is the sum of G inputs for the SFS2 signal gsm '
However, the SFS3 signal holds rsm ′, which is the sum of the R inputs.

Here, these values are transferred to the FIFO memories 5434 and 543 at the timing when the XPHS signal is "2".
Write to 5 and hold. That is, when the XD2 signal is “2” and the YD3 signal is “0”, the SFWE signal becomes “0”, and the FIFO memories 5434 and 54.
Writing to 35 is permitted. This will be described with reference to FIG. As shown in FIG. 45, the YPHS signal becomes "3" and the YD3 signal becomes "0" at the rate of one line in four lines. Further, the XD2 signal becomes “0” at a ratio of 1 pixel to 4 pixels, and both the YD3 signal and the XD2 signal become “0”.
The SFWE signal becomes "0" only when the above condition occurs, and becomes "1" otherwise. When the SFWE signal is "0", the SFS1, SFS2 and SFS3 signals are FIFO
Written to memories 5434 and 5435. Further, the reading is performed in synchronization with the CLK4 signal having a cycle four times that of the CLK signal, and the same value is repeatedly output for four lines.

As a result, the RS, GS and BS signals are signals obtained by averaging and smoothing the R, G and B signals in the 4 × 4 pixel block shown in FIG. [Comprehensive Judgment Circuit 110] FIG. 46 shows a detailed block diagram of the comprehensive judgment circuit 110 shown in FIG. In FIG. 46,
Reference numeral 108 denotes a tint matching ROM (hereinafter referred to as “ROM2”), which has a capacity of 256K × 16 bits.
(For example, Mitsubishi Electric M5M27C402K), and it is determined whether the tint of the read signal is close to the tint of the specific document. 109 is a smoothing color matching ROM (hereinafter referred to as "RO
It is called "M3". ), And the capacity can be realized by a ROM of 256K × 8 bits (for example, Mitsubishi Electric M5M27C201K),
It is determined whether the smoothed tint of the read signal is close to the tint of the specific document.

FIG. 47 shows an example of the distribution of the tint in the RGB space in the line drawing portion of the specific original in FIG. 47, and FIG. 48 shows an example of the distribution of the tint in the flat area in the specific original in the RGB space. In this way, the line drawing portion and the flat portion show characteristic distributions. Similarly, although not shown, the edge portion, the valley portion, and the like of the specific document show a characteristic distribution. These show the color distribution peculiar to a specific document, but R
The OM2 (108) holds the specific tint information of the above-mentioned first characteristic portion and the second characteristic portion based on the 32 predetermined determination conditions, and the input image has these tint components. Is determined. Similarly, ROM3 (109) is 3
The distribution of the tint in the RGB space when the specific document is smoothed based on the two types of determination conditions is retained.

RS from the thinning circuit 106 shown in FIG.
The GS and BS signals are input to the lower address 15 bits of the ROM 2 (108) via the selector 117 and the tri-state gate 119. The data output of the ROM 2 (108) has a 16-bit configuration, and the lower 8 bits (D0 to D7) determine whether or not the tint of the first characteristic portion and the read image signal match. The signal is FC0
The signal is output as a signal, and a determination signal as to whether or not the tint of the second characteristic portion and the read image signal match is output as the SC0 signal in the upper 8 bits (D8 to D15).

Further, the RS, GS and BS signals from the smoothing circuit 105 of FIG.
Then, it is input to the lower address 15 bits of the ROM 3 (109). The output SMC signal of the ROM 3 (109) is a signal indicating whether or not the smoothed tint of the specific document based on certain eight kinds of determination conditions matches the smoothed tint of the read image signal.

Further, the AND gate 112-1 outputs S from
The logical product FC signal of the MC signal and the FC0 signal is output.
That is, the FC signal is such that the color tone of the first characteristic portion of the specific document based on eight kinds of determination conditions matches the read image signal, and the smoothed color tone of the specific document and the read image signal. This signal is "1" when the smoothed colors of the signals match.

Further, the AND gate 112-2 outputs SM
The logical product FC signal of the C signal and the SC0 signal is output. That is, the SC signal is such that the tint of the above-mentioned second characteristic portion of the specific original and the read image signal based on eight kinds of determination conditions match, and the smoothed tint of the specific original and the read image. This signal is "1" when the smoothed colors of the signals match. In this way, the accuracy of detecting the specific original can be improved by adding the smoothed color matching to the condition.

Reference numeral 117 denotes a 2-input 1-output selector,
117-1 in the figure shows the operation logic. In the case of a normal determination operation, the control signal CCL of the selector 117 becomes "1". The case of setting the counter 116 and the CCL signal to "0" will be described later in the section of RAM clear control. The control signal RID of the tri-state gate 119 is "0" in the case of the normal determination operation, but when the RID signal is "1", it will be described in the section of the ID reading mode.

Reference numeral 118 denotes a bank switching means, which outputs a 3-bit PSEL signal to the upper 3 of ROM 2 and ROM 3.
Is supplied as a bit address signal. FIG. 49 shows a detailed block diagram of the bank switching means, and FIG. 50 shows a timing chart thereof. In FIG. 49, 2101 is N
It is an AND gate and receives 2 bits of the YPHS signal. Reference numeral 2102 denotes an AND gate, which includes the lower 1 bit CNO (0) of the 2-bit field sequential signal CNO signal,
The output of the NAND gate 2101 is input and its output becomes the upper 1 bit of the PSEL signal. Further, the YPHS signal is output as the lower 2 bits of the PSEL signal.

Therefore, when the CNO (0) signal is "0", the PSEL signal repeats "0", "1", "2", "3" in synchronization with the rising edge of the HSYNC signal, and the CNO signal. If the (0) signal is "1", PSE
The L signal is synchronized with the rising edge of the HSYNC signal,
“4”, “5”, “6”, “3” are repeated. In FIG. 49, first, the CNO (0) signal is M, C, Y, Bk.
“0”, “1”, “0”, and
It becomes "1". Therefore, when the developing colors are M and Y, the PSEL signal repeats "0", "1", "2" and "3" in synchronization with the rising edge of the HSYNC signal, and when the developing colors are C and Bk. The PSEL signal is HSYN
In synchronization with the rising edge of the C signal, "4", "5",
Repeat “6” and “3”.

That is, in the image processing mode, as shown in Table 2, the address of 37FFF is accessed from the address 00000 of ROM2. The details are as follows: When the development color is M and Y, the address is from the address 00000 to 1FFFF. If the developed color is C or Bk, access 18000 to 37FFF. Note that, in the normal image processing mode, at the same time, a specific original based on eight types of determination conditions (which will be described later, one of them is a tint based on a test original)
Of the PSEL signal, and the eight types to be determined vary depending on the value of each PSEL signal. Switching is performed in units of four main scanning lines, and a plurality of specific originals are determined based on a total of 32 types of determination conditions.

Further, depending on the developing color to be developed, the PSE
Although the L signal is switched and there is some overlap (addresses 18000 to 1FFFF), it is possible to make judgments for a plurality of specific originals based on a total of 56 kinds of judgment conditions. The second
Image processing mode, ID reading mode and RID in the table
The signals will be described later. Here, in the present embodiment, when assigning these 56 types of determination conditions, the assignment is changed according to the importance of a particular document (which one should not be copied most).

First, the eight kinds of judgment conditions held at the addresses 18000 to 1FFFF are judged at the time of all image formation of M, C, Y and Bk unlike the other 48 kinds, and therefore the most reliable. Is determined. Therefore, the eight types of determination conditions are assigned to determine the most important specific document. Next, regarding the 24 kinds of determination conditions held from the address 00000 to the address 17FFF, the M image formation performed at the first scanning and the Y image formation performed at the third scanning are performed. Judgment is made.

On the other hand, the 24 kinds of judgment conditions held at the addresses 20000 to 37FFF are as follows: the image formation of C performed at the time of the second scanning and the image formation of Bk performed at the time of the fourth scanning. Sometimes decisions are made. Comparing the two, the latter (addresses 20000 to 37FFF) has the following drawbacks. That is, B, which is the fourth image formation
When forming the image of k, there is a possibility that a part of the specific original has already been copied at the time when the existence of the specific original is recognized. Compared to this, the former (from address 00000 to 17FF
In the case of (F address), even if the presence of a specific document is detected during the image formation of either M or Y, the output image can be painted black during the subsequent image formation of Bk. Since it can be done, there is no problem in the former case.

Therefore, comparing the two, the former (000
It can be said that the copy protection can be surely performed at addresses 00 to 17FFF). Therefore, the 24 types of judgment conditions to be held from the address 00000 to the address 17FFF are assigned the specific manuscript which seems to be the next most important. In addition, 24 other judgment conditions are assigned to addresses 20000 to 37FFF.

[0169]

[Table 2] (Integrator circuit 1) The above-mentioned FC signal and FZ signal are sent to the integrator circuit 1 (122) in FIG. Integration circuit 1 (12
In 2), a two-dimensional (XY direction) IIR digital filter is used to remove noise of the FC signal indicating the first characteristic portion of the specific original based on the eight types of determination conditions. The integrating circuit 1 (122) has an FZ signal, a ROM 2
From (108), the FC signal, the FIFO 140, indicating the match between the color tone of the first characteristic portion of the specific document and the read image signal.
And a FOA signal connected to the input of the FIFO 141, F
FI which is the output of the IFO140 and FIFO141 signals
It is connected to the A signal.

A detailed block diagram of the integration circuit 1 (122) is shown in FIG. In FIG. 51, 2401, 2
Reference numeral 402 denotes a serial-parallel converter, 2403-1, 240
03-2, ..., 2403-8 are integrators IIR
Filters 2404 and 2405 are parallel-serial converters. Serial-parallel converters 2401 and 204
2 serial-parallel converts the output FIA signals of the FIFO 140 and 141.

Serial / parallel converters 2401 and 240
52 and a timing chart of FIG.
3 shows. In FIG. 52, 2501, 502, 25
Reference numerals 03 and 2504 denote flip-flops which latch the input signal at the rising edge of the CLK4 signal. 2505 is 2
It is a selector with one input and one output, and the operation logic is shown at 2512. 2506 and 2507 are flip-flops, and C
Latch at the rising edge of the LK4 signal. On the other hand, 2508
Is an inverter, 2509 is a 3-bit counter, 251
Reference numeral 0 is a 2-input 4-output decoder whose operation logic is 25
11 shows.

Here, the X signal which is the input signal is CLK
It is input in synchronization with the rising edges of the four signals. The input signals sequentially delayed by the flip-flops 2501, 502, 2503, 2504 are sent to the selector 2505.
On the other hand, the X4PHS output by the counter 2509
The signals are "0", "1", "2", "3", "4", "5", in synchronization with the rising edge of the CCLK4 signal.
The values of "6" and "7" are repeatedly output, but the lower 2
Bits X4PHS (1-0) are "0", "1",
The values of “2” and “3” are repeatedly output, and the decoder 251
X4D1 signal output from 0 is X4PHS (1-0)
It becomes "0" only when the signal is "1", and "1" in other cases.
Becomes

Therefore, as shown in FIG. 53, the signals "a", "b", "c" and "d" sequentially input to the X signal are the outputs A0 and B of the flip-flop 2506.
0, C0, D0 are output in parallel, and the flip-flop 2
From 507, these signals are output after being delayed by one cycle of the CLK4 signal. In FIG. 51, 2403-
1, 2403-2, ..., 2403-8 are IIR filters, and each IIR filter has the same structure.
The processing under each of the judgment conditions is performed, and the processing for the eight kinds of judgment conditions is performed by simultaneously processing the eight IIR filters.

FIG. 54 shows a detailed block diagram of the IIR filter described above. In FIG. 54, 2701 and 27
Reference numerals 02 and 2703 denote selectors each having 3 inputs and 1 output, and the operation logic is shown at 2704. 2705,270
6 is a multiplier, and the product A is applied to the inputs of A and B.
Output xB / 32. 2707 is an adder, A,
The sum A + B + C is output for the inputs of B and C. 2708
Is a flip-flop, which latches and outputs the input signal at the rising edge of the CLK4 signal. Here, the adder 270
The output signal of 7 is yi, j (i is the sub-scanning position after thinning, j
Is the main scanning position signal after thinning, the output of the flip-flop 2708 is yi, j-1. In addition, FIF
Serial parallel converters 2401 and 240 from O104
The FI signal sent via 2 is a signal obtained by delaying the yi, j signal in the sub-scanning direction using the FIFO, and y
It can be expressed as i-1, j.

Here, yi, j is expressed by equation (21). yi, j = (α / 32) yi-1, j + (β / 32) yi, j-1 + γ ··· (21) Further, α1, α2, α3, β1, β2, β3, γ1, γ
2 and γ3 are values preset by the coefficient register described above, and by setting these appropriately,
Noise can be removed by integrating the FC signal.

55, 56 and 57 show examples of processing results by the IIR filter (j indicates the main scanning position). FIG. 55 is a diagram showing an example of an FC signal (a determination signal indicating whether the tint of the read signal matches the tint of the first characteristic portion of the specific original document; 1; match 0; not match). FIG. 56 shows the FZ signal (the reading signal is the first of the specific document.
FIG. 3 is a diagram showing an example of (1; first characteristic portion 0; non-first characteristic portion) in the determination signal of whether or not the characteristic portion of FIG.

As shown in FIGS. 55 and 56, the above α
1, α2, α3, β1, β2, β3, γ1, γ2, γ3
By properly taking the value of, yi, j has a waveform as shown in FIG. That is, 32101 and 32 are included in yi, j.
A waveform in which the noise component is smoothed (integral effect) as shown by 102 is output. 2 with a threshold value of ε
By digitizing, the noise components indicated by 32101 and 32102 can be removed.

Further, in FIG. 54, reference numeral 2710 is a comparator, which compares the output of the flip-flop 2708 with ε shown in FIG. 57 and outputs the comparison result as an FL signal. The FL signal is a signal for determining whether or not the read image signal is highly similar to the first characteristic portion of the specific document.
Reference numeral 2709 denotes an average value circuit, which is a flip-flop 270.
Average 4 consecutive data at 8 outputs.

FIG. 58 shows a detailed block diagram of the average value circuit 2709 shown in FIG. 54, and FIG. 59 shows an operation timing chart thereof. In FIG. 58, reference numeral 2801 is an AND gate, 2802 is an adder, 2803 is a flip-flop, 2804 is a 2-input 1-output selector, and its operation logic is shown by 2808. Reference numeral 2805 designates a flip-flop, 2806 designates a selector having two inputs and one output, and its operation logic is indicated by 2808 as in the case of 2804. 280
7 is a flip-flop.

Here, the X4D0 signal and the X4D3 signal are signals output from the decoder 2510 in FIG.
The X4D0 signal is "0" only when the X4PHS (1-0) signal is "0" and the other signals are "1". The X4D3 signal is "only" when the X4PHS (1-0) signal is "3". A signal that is "0" and the other is "1". Therefore, FIG.
, The X4PHS (1-0) signal is "0",
When the input signal X takes the values of “a”, “b”, “c”, and “d” in order in response to the change of “1”, “2”, and “3”, as a result, Is the four consecutive values "a",
Average value of "b", "c", and "d" (a + b + c + d) /
4 is output from Y.

The output of this integrator is fed back through the FIFO memory. By averaging four consecutive data in this way and holding it in the FIFO,
The capacity of the IFO memory can be reduced to 1/4.
Further, as shown in FIG. 57, since the output of this integrator does not have a high frequency component, replacement with four continuous data average values has almost no effect.

In FIG. 51, IIR2403-1 and IIR2403-1
FO output from 403-2, ..., 2403-8
The signals are parallel to serial converters 2404 and 240.
5 is sent as a FOA signal to the FIFOs 140 and 141, and again as a FIA.
01,402, IIR2403-1,2403
-2, ..., 2403-8 is fed back.

FIG. 60 is a detailed block diagram of the parallel-serial converter shown in FIG. 51, and FIG. 61 is its operation timing chart. In FIG. 60, 3001 is a 4-input / 1-output selector, and the operation logic thereof is shown by 3006. Reference numerals 3002, 3003, 3004 and 3005 are flip-flops. As shown in FIG. 61, as a result, the values “a”, which are input in parallel to A, B, C, and D,
"B", "c", and "d" are sequentially output serially from Y.

Here, in FIG. 51, the parallel-to-serial converter outputs the output to the FIFO serially, and the signal from the FIFO is serial-to-parallel converted, whereby the number of FIFO memories is reduced and the LSI.
It is possible to reduce the number of I / O pins, reduce costs, and improve reliability of circuits including LSI.

In FIG. 51, FL signals output from the eight IIR circuits (signals for determining whether or not the read image signal is highly similar to the first characteristic portion of the specific original).
Is an integration circuit 2 (12
It is output to 3). Further, in FIG.
FR for controlling writing and reading of 40 and 141
The E signal and the FWE signal are generated by the FIFO control circuit 114, and are controlled by the integration circuit 1 (122) in consideration of the delay of the integration circuit 1 (122) so that the expression (21) is satisfied.

(Integrator circuit 2) In FIG. 46, the above-mentioned S
The Z signal is sent to the integrating circuit 2 (123). Integrating circuit 2
(123) is a two-dimensional (XY direction) IIR digital filter similar to that of the integration circuit 1 (122), and is a noise (noise) of the SC signal indicating the second characteristic portion of the specific document based on eight kinds of determination conditions. ) Is removed. The integrating circuit 2 (123) stores the ROM 2 together with the above SZ signal.
In the output of the SC signal indicating the second characteristic portion of the specific document from (108), the FLSG signal output from the integration circuit 1 (122), the FOB signal to which the inputs of the FIFO 142 and the FIFO 143 are connected, and the FIFO 142 and the FIFO 143 signal. It is connected to some FOB signal.

FIG. 62 shows a detailed block diagram of the integration circuit 2 (123). In FIG. 62, 3301,3
Reference numeral 302 denotes a serial / parallel converter 240 shown in FIG.
Serial-parallel converter equivalent to 1,2402, 330
3-13303-2, ..., 3303-8 are IIR filters which are integrators, and 3304 and 3305 are parallel-serial converters equivalent to 2404 and 2405 in FIG.

IIR filters 3303-1, 3303-2, ..., 3303-in the integrating circuit 2 (123).
A detailed block configuration diagram of No. 8 is shown in FIG. In FIG. 63, 3401, 3402, and 3403 are 5 inputs 1 respectively.
It is an output selector and its operation logic is shown at 3404. Multipliers 3405 and 3406 output the product A × B / 32 with respect to the inputs A and B. Reference numeral 3407 is an adder, which outputs the sum A + B + C with respect to the inputs of A, B, and C. 3408 is a flip-flop, and CLK4
The input signal is latched and output at the rising edge of the signal. Here, when the output signal of the adder 3407 is the y'i, j (i is the sub-scanning position after thinning-out and j is the main scanning position after thinning-out) signal, the output of the flip-flop 3408 is y'i, j. -1, and the FI signal from the FIFO is the y'i, j signal delayed in the sub-scanning direction using the FIFO,
It can be expressed as y'i-1, j.

Here, y'i, j is expressed by the following equation (22). y'i, j = (α '/ 32) y'i-1, j + (β' / 32) y'i, j-1 + γ '... (22) Further, α1', α2 ', α3' , Α4 ', α5', β
1 ', β2', β3 ', β4', β5 ', γ1', γ
2 ′, γ3 ′ γ4 ′, and γ5 ′ are values preset by the coefficient register described above, and by appropriately setting them, the SC signal can be integrated and noise can be removed.

FIG. 64 shows an example of the processing result (j indicates the main scanning position). In the uppermost part of FIG. 64, an SC signal (a determination signal indicating whether the tint of the read signal matches the tint of the second characteristic portion of the specific document is 1; match 0;
Example of non-matching) of the SZ signal (a read signal is a determination signal of whether or not the second characteristic portion of the specific document is 1; second characteristic portion 0; not second characteristic portion) An example
The FL signal (a signal for determining whether the read image signal has a high similarity to the first characteristic portion of the specific original,
1; the first characteristic portion is 0; it is not the first characteristic portion).

At this time, the above-mentioned α1 ′, α2 ′, α3 ′
, Α4 ′, α5 ′, β1 ′, β2 ′, β3 ′, β4 ′,
By appropriately taking the values of β5 ', γ1', γ2 ', γ3' γ4 ', and γ5', y'i, j has a waveform as shown in the lowermost stage. That is, y'i, j includes 35101 and 35102
A waveform in which the noise component is smoothed (integral effect) as shown in is output. By binarizing with a threshold value of ε ′, the noise components indicated by 35101 and 35102 can be removed.

On the other hand, in FIG. 63, reference numeral 3410 is a comparator, which compares the output of the flip-flop 3408 with the threshold value ε'shown at the bottom of FIG. 64 and outputs the comparison result. On the other hand, 3411 is a flip-flop, 3412 is an AND gate, 3413 is a flip-flop, 3414.
Is an AND gate, and the output of the comparator 3410 is logically ANDed with the SC signal and the SZ signal and output as the CN signal. This CN signal is "1" when the read image is likely to be a part of the second feature of the specific document.
Becomes

On the other hand, reference numeral 3409 denotes 2709 shown in FIG.
This is an average value circuit equivalent to, and averages four consecutive data at the output of the flip-flop 3408 for the same reason as in the case of the integrating circuit 1 (122). In FIG. 62, I
IR3303-1, 3303-2, ..., 3303-
The FO signal output from the signal No. 8 passes through parallel-to-serial converters 3304 and 3305 and is converted into a FI signal as a FI signal.
The data is sent to the FOs 142 and 143, and again passes through the parallel-serial converters 3301 and 3302 as the FIB to the IIR3.
It is fed back to 303-1, 3303-2, ..., 3303-8.

In FIG. 62, the CN signal (a signal for determining whether or not the read image signal is highly likely to be a part of the second characteristic portion of the specific original) output from the eight IIR circuits is , 8-bit CEN signal is output to the volume ratio determination circuit 128. Furthermore, in FIG.
The FRE signal and the FWE signal that control the writing and reading of the FIFOs 140 and 141 are the FIFO control circuit 1
And is controlled by the integration circuit 2 (123) in consideration of the delay of the integration circuit 2 (123) so that the expression (21) is satisfied. (Volume Ratio Judgment and Final Judgment) In FIG. 46, the CEN signal output from the integration circuit 2 (123) is sent to the volume ratio judgment circuit 128.

The volume ratio determining circuit 128 includes an integrating circuit 2
From (123), how much the pixel group in which each bit of the CEN signal is “1” occupies in the tint distribution range (three-dimensional RGB volume) of the second characteristic portion of the specific document shown in FIG. Under the condition that the volume ratio and the volume ratio are equal to or greater than a certain value, the number of hit pixels, which is the total number of pixels in which each bit of the CEN signal is “1”, is counted, and the final determination of the presence or absence of the specific document is completed. To be done.

The volume ratio determination circuit 128 is provided with a static RAM (hereinafter referred to as “SRAM”) via a bidirectional buffer 130.
Called. ) 136, 137, 138, and 139 data buses are connected. On the other hand, the signal of the lower 17 bits of the 18 bits input to the address of ROM2 (108) is
The delay circuit 124 synchronizes the delays of the integrating circuit 1 (121) and the integrating circuit 2 (122), and passes through the tri-state buffer 125 to the lower 15 bits (that is, RG).
SRA signal of 5 bits for each B)
For each of the addresses 6, 137, 138, and 139, the upper 2 bits (that is, the YPHS signal) have a 2-input 4-output decoder 1
31 (the operation logic is 149). Decoder 13
The four outputs Y0, Y1, Y2, Y3 of 1 are ANDed with the CCL signal by AND gates 132, 133, 134, 135, and four SRAMs 136, 137, 13
It is inputted to each chip select terminal (CS) of 8,139.

Therefore, the SRAM 136 is accessed when the YPHS signal is "0", and the SRAM 137 is YPH.
When the S signal is "1", the SRAM 138 is accessed.
Is accessed when the YPHS signal is "2", and SRA
M139 is accessed when the YPHS signal is "3". Further, in each SRAM, after being initialized (cleared to zero), each address is accessed to the lower 15 bits of the address of the ROM 2 (108), and 5 bits of each 5 bits of the RGB signal are sent in total, and one of the CEN signals is sent. RGB corresponding to when the bit becomes "1"
"1" is written in the address indicating the value of. In addition, S
The initialization of the RAM will be described later.

Further, with respect to each bit of the 8-bit data, a process for a specific original is performed based on eight different judgment conditions. An SRAM control circuit 129 is an RWE signal that controls the write enable terminals (WE) of the four SRAMs 136, 137, 138, and 139, an ROE signal that controls the output enable terminals (OE) of the four SRAMs, and the bidirectional buffer 130. Generates a RID signal for controlling the control terminal of the.

Here, 126 is an inverter, 127 is a tri-state buffer, and one of the two tri-state buffers 125 and 127 becomes active depending on the value of the control signal CCL. However, since the CCL signal is "1" during normal operation, the tri-state circuit 125 becomes active. FIG. 65 shows the detailed block configuration of the volume ratio determination circuit 128, and its operation timing is shown at 402 and 403 in FIG. In FIG. 66, the RID signal is a control signal for controlling the direction of the bidirectional buffer 130, the RWE signal is a write enable control signal for four SRAMs, the ROE signal is an output enable control signal for four SRAMs, and these signals are SRAMs. It is generated by the control circuit 129.

As shown in the timing 402 of FIG. 66 and the table 403, when the XPHS signal is "0" and "1", the RID signal is "1", so the direction of the bidirectional buffer is As the direction goes from SRAM to LSI101, the RWE signal is "1" and the ROE signal is "0".
Therefore, the SRAM is in the read state. Furthermore, X
When the PHS signal is “2”, the RID signal is “0”, so the direction of the bidirectional buffer is “direction from the LSI 101 to the SRAM”, the RWE signal is “0”, and the ROE signal is “1”. ", The SRAM is in a write state.

When the XPHS signal is "3", RID
Since the signal is "0", the direction of the bidirectional buffer is "L".
From SI101 to the direction of SRAM ", RWE signal,
Since the ROE signals are both "1", the SRAM is in neither a reading state nor a writing state. Also,
Since the SRA signal which is the address of the SRAM changes in synchronization with the rising edge of the CLK4 signal, the XPHS signal does not change for one cycle from "0" to "3". Therefore, in SRAM, so-called read / modify
/ Write (read / modify / write) operation is performed.

Next, in FIG. 65, reference numeral 3601 denotes a 2-input 1-output selector (operational logic is indicated by 3602), 36
03 and 3605 are flip-flops, 3604 is an inverter, 3606 and 3608 are AND gates, 3607 is an OR gate, 3609-1, 3609-2, ..., 3
Reference numerals 609-8 are counter circuits. Where R
The O signal is a signal read from the SRAM, but RO
When the E signal is "0", it passes through the selector 3601 and is latched by the flip-flop 3603 at the rising edge of the CLK signal to become the RO1 signal.

On the other hand, the flip-flop 3605 outputs CLK.
The CEN signal synchronized at the rising edge of the four signals is C
It becomes the EN1 signal. In the TEN signal calculated by the inverter 3604 and the AND gate 3606, since the CCL signal is normally "1", the RO1 signal is "0".
That is, only when the CEN signal is "1", the operation of "1" is performed for each of the 8 bits.

Further, since the "VS" signal is "1" at the time of image reading, the OR gate 3607 and the AND gate are connected.
The RI signal calculated by the gate 3608 is RO1.
The OR of the signal and the CEN signal is calculated for each of the 8 bits. Therefore, in the SRAM, after the initialization, the CEN signal and the data stored in the address of the SRAM corresponding to the RGB signal at that time are logically ORed and written to the same address. Further, when any of the 8 bits of the SRAM data changes from "0" to "1", the corresponding bit in the TEN signal becomes "1". That is, the "volume ratio" can be counted by counting the number of times "1" is output for each bit of the TEN signal.

3601-1, 3601-2, ..., 3
A counter circuit 601-8 counts the number of occurrences of "1" for each bit of the TEN signal. Counter circuits 3601-1, 3601-2, ...
67 shows the detailed block configuration of 3601-8.
In FIG. 67, reference numeral 3701 is a 2-input 4-output decoder (the operation logic is shown by 3702), which is 3703,3.
704, 3705, 3706 are AND gates, 370
7, 3708, 3709, 3710 are counters, 371
Reference numeral 2 denotes a 4-input 1-output selector (operational logic is shown at 3713).

In this way, four independent counters 370 are provided.
7, 3708, 3709, 3710. When the YPHS signal is “0”, the counter 3707 counts,
The output of the counter 3707 is output as the Q output. On the other hand, when the YPHS signal is “1”, the counter 370
The output of the counter 3708 is output as the Q output. When the YPHS signal is "2", the counter 3709 counts and the output of the counter 3709 is Q.
It is output as output. When the YPHS signal is "3", the counter 3710 counts, and the output of the counter 3710 is output as the Q output. That is, the YPHS signal is subjected to time-division processing, and the determination of the specific original is made based on eight different determination conditions.

In FIG. 65, reference numeral 3610 denotes an 8-input 1-output selector (operation logic is shown at 3625), 3611.
Reference numerals 3612 and 3612 are selectors of 16 inputs and 1 output (operation logic is shown in 3626), and reference numerals 3613 and 3614 are comparators. Also, MS00, MS01, ..., MS3
, 1 and M00, M01, ..., M15 are values preset in the above-mentioned counting register 148, and have values specific to a particular document based on 32 types of determination conditions to be determined. MS00 to MS31 are set values of the dead zone of the hit pixel number count described later, and M00 to M15 are mask signals of the hit pixel number count result described later.

Selectors 3610 and 3611, 3612
Allows the processing by the comparators 3613 and 3614 to be X4P.
It is time-divided corresponding to HS, and the result is sent to serial-parallel converters 3615 and 3616. FIG. 68 shows a detailed block configuration of the serial / parallel converters 3615 and 3616, and FIG. 6 shows an operation timing chart thereof.
9 shows. That is, in FIG. 68, 3801, 380
2,3803,3804,3805,3806,380
Reference numerals 7, 3808, 3812, 3813 are flip-flops, 3809 is an OR gate, and 3810 is a 2-input 1-output selector (operation logic is shown by 3811).

As a result of the provision of the above configuration, the values sequentially (serially) input to X are simultaneously (parallelly) output corresponding to each bit of the 8-bit Y output. Therefore, the MK signal and the MASK signal in FIG. 65 are output at the same time, although with some delay, on the specific original document based on the eight kinds of determination conditions.

In FIG. 65, 3618-1, 3618
Reference numerals -2, ..., 3618-8 are hit pixel number counting circuits and have the same structure. 3619 is AN
A D gate, 3620 are a counter group, and 3621 is a comparator. Further, GS00, GS01, ..., GS31 are values preset in the count register 148, and 3
626-1, 3626-2, ..., 3626-8 is 4
Input 1 output selector (operation logic is shown in 3627)
Is.

The counter group 3620 is composed of four counters. FIG. 70 shows a detailed block configuration of the counter group 3620. In FIG. 70, 5701 and 570
2,5703,5704 are AND gates, 5705,5
Reference numerals 706, 5707, 5708 are counters, and 5709 is a maximum value circuit. That is, the counter 5705 counts up when the GENA signal is "1" and the EN signal is "1". In other words, the case where the EN signal is "1" is counted in the section where the GENA signal is "1". Similarly, the genb signal of the counter 5706 is "1".
, The counter 5707 counts when the EN signal is "1", and the counter 5708 counts the case where the EN signal is "1". The case where the EN signal is "1" in the section of "1" is counted. Further, by the maximum value circuit 5709, the four counters 5705, 570 are
The maximum value of the count values of 6, 5707 and 5708 is output as Q.

On the other hand, GENA, GENB, GENC, G
END is a signal as shown in FIG. 71 and divides the main scan. The principle will be described later. In FIG. 65, the number of times each bit of the TEN signal is “1” is independently counted by the counter circuits 3609-1 to 3609-8, and the counting result is a predetermined value MS00 to MS31.
(If the YPHS signal is "0", MS00 to MS0
7. MS08 to MS1 when YPHS signal is "1"
5, MS16 to MS2 when YPHS signal is "2"
3. If the YPHS signal is "3", MS24 to MS3
If it is larger than the value of 1), the corresponding bit of the MASK signal becomes "1" and the group of counters 3620 starts counting the number of the corresponding bit of the CEN signal being "1".

In FIG. 65, reference numeral 3621 denotes an inverter,
3622-1, 3622-2, ..., 3622.8 are A
It is an ND gate. Further, the TESTMODE signal is a signal set by a CPU (not shown) and switches between the normal operation mode and the test mode. Specifically, it is "0" in the normal operation mode and "1" in the test mode.

Here, the counting result of the CEN signal indicates that the corresponding GS00 to GS31 (GS00 to GS07 when the YPHS signal is "0", GS08 to GS15, and the YPHS signal when the YPHS signal is "1"). In the case of "2", when the value of GS16 to GS23 is larger than the value of GS16 to GS23, and in the case of YPHS signal being "3", it is larger than the value of GS24 to GS31), and the counting result (that is, volume ratio) of the CEN signal corresponds to M
00 to M31 (M00 when the YPHS signal is "0")
~ M07, M08 ~ M when YPHS signal is "1"
15. If the YPHS signal is "2", M16 to M2
3. If the YPHS signal is "3", M24 to M31)
AND gate 36 only when it becomes larger than the value of
The outputs of 22-1, 3622-2, ..., 3622-8 can be “1”.

In addition to the above conditions, AND gate 3
622-1 can be set to "1" only when the TESTMODE signal is "1" (that is, in the test mode), and AND gates 3622-2, ..., 3622-8 are connected to TESTMODE.
It can be "1" only when the signal is "0" (that is, in the normal operation mode). That is, of the eight types of determination means that are processed and determined at the same time, one type is for a test original and the other seven types are for a normal specific original.

Reference numeral 3623 is a HIT signal generator, and AN
D gate 3622-1, 3622.2, ..., 3622-
The 32-bit HIT signal described above is generated in accordance with the 8-bit signal generated in time division by the value of the YPHS signal from 8. FIG. 72 shows a detailed block configuration of the HIT signal generator shown in FIG. In FIG. 72, 630
1, 6302, 6303, 6304 are inverters, 63
05, 6306, 6307, 6308, 6309, 63
10, 6311, 6312, ..., 6313, 631
4, 6315, 6316 are AND gates, 6317, 6
318, 6319, 6320, 6321, 5322, 6
323, 6324, ..., 6325, 6326, 632
Reference numeral 7,6328 is a JK flip-flop.

The 8-bit X signal in FIG.
ND gates 3622-1, 3622-2, ..., 362
It is a signal transmitted from 2-8, and is an 8-bit signal indicating the determination result based on the above-mentioned 32 types of determination conditions, which is generated in four time divisions according to the value of the YPHS signal. Also,
YD0, YD1, YD2, YD3 are signals dependent on the YPHS signal, as indicated by 402 in FIG.

YD0 is a signal which becomes "0" only when the YPHS signal is "0", and becomes "1" otherwise, YD1
Is a signal that becomes "0" only when the YPHS signal is "1", and becomes "1" otherwise, and YD2 is a signal that becomes "0" only when the YPHS signal is "2" and becomes "1" otherwise. , YD3 is a signal which becomes "0" only when the YPHS signal is "3" and becomes "1" otherwise.

Here, the least significant bit of the X signal, bit0
Are AND gates 6305, 6306, 6307, 63
08 is input to one input terminal. Further, a signal obtained by logically inverting the YD0 signal is input to the other input terminal of the AND gate 6305. A signal obtained by logically inverting the YD1 signal is input to the other input terminal of the AND gate 6306.
A signal obtained by logically inverting the YD2 signal is input to the other input terminal of the AND gate 6307. AND gate 6308
A signal obtained by logically inverting the YD3 signal is input to the other input terminal of the.

As a result, JK flip-flop 630
In FIG. 5, when the YPHS signal is "0" and the least significant bit bit0 of the X signal is "1", its output becomes "1" and is held. Further, in the JK flip-flop 6306, when the YPHS signal is "1" and the least significant bit bit0 of the X signal is "1", its output becomes "1" and is held.

The JK flip-flop 6307 has a YP
When the HS signal is "2" and the least significant bit bit0 of the X signal is "1", the output is "1" and is held. The JK flip-flop 6308 has
When the YPHS signal is "3" and the least significant bit of the X signal, bit0, is "1", its output becomes "1" and is held.

Similarly, bit 1 which is the second least significant bit of the X signal is AND gates 6309, 6310, 631.
1, 6312. Further, the AND gate 63
A signal obtained by logically inverting the YD0 signal is input to the other input terminal of 09. A signal obtained by logically inverting the YD1 signal is input to the other input terminal of the AND gate 6310. AND
A signal obtained by logically inverting the YD2 signal is input to the other input terminal of the gate 6311. A signal obtained by logically inverting the YD3 signal is input to the other input terminal of the AND gate 6312.

As a result of these, in the JK flip-flop 6309, when the YPHS signal is "0",
When bit1 of the X signal is "1", its output becomes "1" and is held. In addition, the JK flip-flop 6310 has a YPHS signal of "1",
When the least significant bit bit1 of the X signal is "1", its output becomes "1" and is held.

The JK flip-flop 6311 has a YP
When the HS signal is "2" and the least significant bit bit1 of the X signal is "1", the output becomes "1" and is held. In the JK flip-flop 6312, when the YPHS signal is "3" and the least significant bit bit1 of the X signal is "1", the output becomes "1" and is held.

Note that only bit7 in the figure is shown, and bit2
Although not shown in the figure for ~ bit6, the other 6 bits (bit2, bit3, bit4, bit5, bit6, bit7) of the X signal are similarly time-divided into JK flip-flops and their values are held. . The outputs of these 32 JK flip-flops in total are output as a 32-bit HIT signal.

Here again, the meaning of the HIT signal is the judgment result under 32 kinds of judgment conditions for judging the predetermined specific original. The initialization (zero clear) of the HIT signal is performed by the VSTR signal described later. (Judgment When Specific Manuscript Exists And Processing In That Case) As a result of judgment by a plurality of judgment conditions by the above process, the 32-bit HIT signal is CP
It is sent to U311. The CPU 311 shown in FIG.
The presence or absence of a specific document is determined according to a rule predetermined by the T signal.

Here, (Example 1) and (Example 2) will be given as examples of determining the presence or absence of a specific document. (Example 1) This is a case of determining the presence or absence of a total of 22 types of specific originals, and is the nth bit (n = 0,1,) of the 32-bit HIT signal.
2, ..., 31) is HIT (n), and the logical product is &, the presence or absence of specific manuscript No. 1 (test specific manuscript) is
Judgment by (0) Whether or not there is a specific original No. 2 (test specific original) is HIT
Judgment in (8) Whether or not there is a specific original No. 3 (test specific original) is HIT (1
Judgment in 6) Whether or not there is a specific original No. 4 (test specific original) is HIT (2
Judgment in 4) Judgment of specific manuscript No.5 is judged by HIT (1) Judgment of existence of specific manuscript No.6 is judged by HIT (2) Judge of existence of specific manuscript No.7 is judged by HIT (3) Existence of original No.8 is judged by HIT (4). Existence of specific original No.9 is judged by HIT (5). Existence of specific original No.7 is judged by HIT (6). Presence / absence is judged by HIT (7) Presence / absence of specific original No.12 is judged by HIT (9) Presence / absence of specific original No.13 is judged by HIT (10) Presence / absence of specific original No.14 is HIT ( Judgment in 11) Presence or absence of specific original No.15 is determined by HIT (12) Presence of specific original No.16 is determined by HIT (13) Presence or absence of specific original No.17 is HIT (14) & HIT ( 1
Judgment in 5) HIT (17) & HIT (1
Judgment in 8) HIT (19) & HIT (2
0) & HIT (21) Judges whether there is a specific manuscript No. 20 by checking HIT (22) & HIT (2
3) & HIT (25) Judgment Whether there is a specific manuscript No. 21 is HIT (26) & HIT (2
7) & HIT (28) Judgment Whether there is a specific manuscript No. 22 is HIT (29) & HIT (3
0) & HIT (31) Judgment formula in the test mode is J = HIT (0) | HIT (8) | HIT (16) | HIT (24) The version formula in the normal operation mode is J = HIT (1) | HIT (2) | HIT (3) | HIT (4) | HIT (5) | HIT (6) | HIT
(7) | HIT (9) | HIT (10) | HIT (11) | HIT (12) | HIT (13) | {HIT (14) & HIT (15)} | {HIT (17) & HIT (18)} | {HIT (19) & HIT (20) & HIT (21)} | {HIT (22) & HIT (23) & HIT (2
5)} | {HIT (26) & HIT (27) & HIT (28)} | {HIT (29) & HIT (30) & HIT (3
1)}, the presence or absence of a specific manuscript is determined by the value of J.
If J = "0", it is determined that the target specific document does not exist on the platen. If J = "1", at least one of the target specific documents exists on the platen. Then it is judged.

Here, the No. 1 to No. 16 specific originals are judged by one kind of judgment condition for each one special original, and the No. 17 to No. 18 specific originals are judged as one Judgment is made with two kinds of judgment conditions for a specific document, No. 19 to N
For the specific original of o.22, each specific original is judged by three kinds of judgment conditions. (Example 2) In the case of determining the presence or absence of a total of 19 types of specific originals, the n-th bit of the 32-bit HIT signal (n = 0, 1,
2, ..., 31) is HIT (n), and the logical product is &, the presence or absence of specific manuscript No. 1 (test specific manuscript) is
Judgment by (0) Whether or not there is a specific original No. 2 (test specific original) is HIT
Judgment in (8) Whether or not there is a specific original No. 3 (test specific original) is HIT (1
Judgment in 6) Whether or not there is a specific original No. 4 (test specific original) is HIT (2
Judgment in 4) Judgment of specific manuscript No.5 is judged by HIT (1) Judgment of existence of specific manuscript No.6 is judged by HIT (2) Judge of existence of specific manuscript No.7 is judged by HIT (3) Existence of original No.8 is judged by HIT (4). Existence of specific original No.9 is judged by HIT (5). Existence of specific original No.7 is judged by HIT (6). Presence / absence is judged by HIT (7). Presence / absence of specific original No.9 is determined by HIT (9). Presence / absence of specific original No.10 is HIT (10) & HIT (1
Judgment in 1) HIT (12) & HIT (1
Judgment in 3) HIT (14) & HIT (1
Judgment in 5) HIT (17) & HIT (1
Judgment in 8) HIT (19) & HIT (2
Judgment in 0) HIT (21) & HIT (2
Judgment in 2) HIT (23) & HIT (2
Judgment in 5) HIT (26) & HIT (2
7) & HIT (28) Judgment Whether there is a specific manuscript No. 19 is HIT (29) & HIT (3
0) & HIT (31) Judgment formula in the test mode is J = HIT (0) | HIT (8) | HIT (16) | HIT (24) The version formula in the normal operation mode is J = HIT (1) | HIT (2) | HIT (3) | HIT (4) | HIT (5) | HIT (6) | HIT
(7) | HIT (9) | {HIT (10) & HIT (11)} | {HIT (12) & HIT (13)} | {HIT (14) & HIT
(15)} | {HIT (17) & HIT (18)} | {HIT (19) & HIT (20)} | {HIT (21) & HIT (22)} | {HIT (23) & HIT
(25)} | {HIT (26) & HIT (27) & HIT (28)} | {HIT (29) & HIT (30) & HIT (3
1)}, the presence or absence of a specific manuscript is determined by the value of J.
If J = "0", it is determined that the target specific document does not exist on the platen. If J = "1", at least one of the target specific documents exists on the platen. Then it is judged.

Here, the No. 1 to No. 9 specific originals are judged by one kind of judgment condition for each one special original, and the No. 10 to No. 17 specific originals are judged as one No.18 to No is judged for the specific original by two kinds of judgment conditions.
19 specific manuscripts, 3 for each one
Judgment is made based on the kind of judgment conditions.

It is needless to say that these two examples given above are only one example, and there may be any combination other than this. Further, the CPU 311 sets the INHIBIT signal to “1” after the value J of the above-described evaluation formula becomes “1”, and uses the OR circuit 310 to make the subsequent images “solid images”.

As shown in Table 2 above, the 32 kinds of judgment conditions can be made different during M, Y image formation and during C, Bk image formation, and the four original scanning (M , C, Y, Bk) corresponding to each image formation). For example, a combination of the example shown in (Example 1) at the time of forming M and Y images and the example shown in (Example 2) at the time of forming C and Bk images may be performed.

[Initialization of SRAM and counters] To count the volume ratio and the number of hit pixels, the SRAM 136 is used.
-139 and each counter (3707-3610,362)
00) must be initialized (cleared to zero). Initialization of these SRAMs and counters is performed by C shown in FIG.
It is formed by the CCL signal generated by the CL generation circuit 149. Further, the VSTR signal is also generated by the CCL generation circuit 149 as initialization of the HIT signal which is the final determination result. The timing chart is shown in FIG.
Shown in 1.

In FIG. 66, the VS signal is a signal which becomes "1" in the image forming section. At the rising edge of the VS signal, the VSTR signal becomes "0", and otherwise it becomes "1" and the HIT signal is initialized. Turn into. The CCL signal is V
The t1 section “0” and the t2 section “1” are repeated from the rising edge of the S signal. In the t1 section in which the CCL signal is “0”, the counter 116 of FIG. 46 displays 0000 / HEX to 3F.
Count up to FF / HEX. On the other hand, since the CCL signal is “0”, the count output of the counter 116 passes through the selector 117 and the tri-state gate 127,
It is supplied to the addresses of the SRAMs 136 to 139. Further, since the CCL signals input to the AND gates 132 to 135 are "0", the CS terminals of the four SRAMs are all "0", and the four SRAMs are simultaneously accessed.

The CCL signal is also supplied to the AND gate 3608 shown in FIG. 65, and the RI signals output to the SRAM are all "0". On the other hand, the SRAM control circuit 12
Since 9 generates the RWE signal as indicated by 401 in FIG. 66, "0" is written in all addresses of the four SRAMs to complete initialization. When the initialization of the SRAM is completed, the CCL signal becomes "1", the above-described normal determination operation is started, the initialization is performed again after the elapse of the period t2, and this is repeated. On the other hand, the counter group 3620 shown in FIG. 65 described above has the control signal GE shown in FIG. 71.
It is controlled by NA, GENB, GENC, and GEN, and the relationship with the above-mentioned CCL signal will be described with reference to FIG.

In FIG. 73, the counter group 3620 is
The main scan is divided into sections 5901, 5902, 5903, 5904, the CEN signal is independently counted, and the maximum value of the four count results is output. still,
Reference numeral 203 is a platen glass, and 204 is a document. on the other hand,
It is divided by the CCL signal in the sub-scanning direction.
5, 5906, 5907, 5908 are divided, each is counted, and their maximum values are latched. For example, the section indicated by 5902 for the main scan and 5906 for the sub-scan is the area indicated by 5909, and the CEN signal is counted for each such area. In this way, the image reading signal is divided into main scanning and sub-scanning (vertical direction and horizontal direction), and the determination is made independently of each other, so that erroneous detection in a large-area general document can be prevented.

[Image processing mode and ID reading mode]
The apparatus in this embodiment has two modes, an image processing mode and an ID reading mode. In the image processing mode, the device performs normal image processing, and the ROM1 (101), RO
The M2 (108) and the ROM3 (109) are used as a table for determining the presence / absence of a specific document. ID
In the read mode, ROM1 (101), RO
The respective IDs held in advance at the highest addresses of M2 (108) and ROM3 (109) are read out. ROM control in each mode is performed by RID signal, PSEL
It is done by a signal.

ROM 2 (108) and R in Table 2 described above
The contents held in each address of the OM3 (109) and the conditions for accessing the contents are shown. First, in the image processing mode, the RID signal is set to "0" by the CPU 311, and the ROM 2 (108) and the ROM
The PSEL signal by the bank switching means 118 is input to the upper 2 bits of 3 (109), and the output R ″, G ″, B ″ signals from the serial-parallel conversion circuit are input to the lower 15 bits. Is entered.

On the other hand, in the ID reading mode, the CPU 311 sets the RID signal to "1" in FIG. At this time, the outputs of the tri-state gates 119 and 145 become high impedance, and the pull-up resistor 12
ROM3 (109), ROM2 by 0 and 146
The addresses of (108) and ROM1 (101) are all "1".

At this time, ROM2 (108) and ROM3
The data output of (109) is 3FFF which is the highest address.
Output the contents stored in address F. A ROM ID is held in advance in the lower 8 bits of the data of the highest address, and is read by the CPU 311 as ROM2-ID and ROM3-ID. In addition, ROM1 (1
The data output of 01) outputs the contents held in the address FF which is the highest address. The ROM ID is held in advance in the 8 bits of the data of the highest address, and is read by the CPU 311 as ROM1-ID.

Here, although the ID is an 8-bit code, a code other than "00 / HEX" and "FF / HEX" is used. The reason is that ROM1 (101), ROM2 (10
8) and ROM3 (109) are intentionally removed, or ROM1 (101), ROM2 (108)
And ROM3 (109) is defective, or ROM1 (101), ROM2 (108) and ROM3
If (109) is replaced with an inappropriate ROM,
This is because it is very likely that the value of “00 / HEX” in which all 8 bits are “0” or the value of “FF / HEX” in which all 8 bits are “1” will be read.

Here, the special thing is that in the case of the image processing mode, ROM2 (108) and ROM3
37FFF address is accessed from 00000 address of (109), 3F in the ID reading mode of ROM
That is, the FFF address is accessed and control is performed without duplication. [ID Reading Operation] FIG. 74 shows a control flowchart in the ID reading mode of this embodiment.

First, at 4101, RID is set to "1". As a result, as described above, the ROM1 (101)
The address of the ROM 2 (108) is set to the highest address, and the ID (hereinafter ROM-ID) held in advance at that address can be read. Continued 410
In step 2, ROM1-ID is read. And 4103
If ROM1-ID is "00 / H", then R
It is determined that the OM1 (101) or its peripheral circuit is not mounted, has a failure, or is maliciously modified, and stops the operation of the device.
Similarly, in 4104, if ROM1-ID is "FF
In the case of / H ", the operation of the similar device is stopped.

Further, at 4105, the ROM2-ID is read. Then, at 4106, if ROM2-I
If D is "00 / H", it is determined that the ROM 2 (108) or its peripheral circuit is not mounted, has a failure, or is maliciously modified, and the operation of the apparatus is stopped. Similarly, in ROM 4107, if the ROM2-ID is "FF / H", the operation of the same device is stopped.

Further, the ROM3-ID is read in 4108, and if the ROM3-ID is "00" in 4109.
If it is "/ H", it is determined that the ROM 3 (109) or its peripheral circuit is not mounted, is out of order, or is maliciously modified, and the operation of the device is stopped.
When the M3-ID is "FF / H", the operation of the same device is stopped.

Further, in 4111, ROM1-ID
And ROM2-ID ROM3-If all three IDs are not the same, it is determined that the ROM1, ROM2, and ROM3 or their peripheral circuits are not mounted, have a failure, or are maliciously modified, and the operation of the device is stopped. Note that the CLK signal is input as a clock input to each of the flip-flops described above, and for the flip-flops that have no particular instruction.

As described above, according to this embodiment, in the image processing apparatus for determining the presence / absence of a specific original, a calibration-like original (reference white plate) as a reference is read and variations in the characteristics of the image reading means are detected. When calibrating, the reference white plate for calibration is read at multiple points on the platen glass to correct the characteristic variations between the devices, and at the same time, the correction due to the variations due to the reading position on the platen glass in the reading section of the device. The error can be effectively corrected. The present invention may be applied to a system including a plurality of devices or an apparatus including a single device. Further, it goes without saying that the present invention can also be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0247]

As described above, according to the present invention, it is possible to correct the characteristic variation between the devices and also effectively correct the reading error for each reading position of the reading means of the device.

[Brief description of drawings]

FIG. 1 is a schematic view of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an image processing unit of the image scanner shown in FIG.

FIG. 3 is a timing chart showing the timing of a synchronization signal in this embodiment.

FIG. 4 is a diagram for explaining a 4 × 4 pixel block.

5 is a block diagram showing a detailed configuration of a determination circuit shown in FIG.

6 is a block diagram showing a detailed configuration of a frequency dividing circuit shown in FIG.

7 is a block diagram showing a detailed configuration of an image feature extraction circuit shown in FIG.

8 is a block diagram showing a detailed configuration of the ND circuit shown in FIG. 7.

9 is a block diagram showing a detailed configuration of a halftone dot removal circuit shown in FIG. 7.

10 is a block diagram showing a detailed configuration of a halftone dot removing circuit shown in FIG.

11 is a diagram showing a relationship between pixel positions used in the halftone dot removal circuit shown in FIG.

FIG. 12 is a diagram for explaining the operation principle of the halftone dot removal circuit shown in FIG. 7.

13 is a block diagram showing a detailed configuration of the line drawing emphasis circuit shown in FIG. 7. FIG.

14 is a block diagram showing a detailed configuration of the line drawing emphasis circuit shown in FIG. 7. FIG.

FIG. 15 is a diagram for explaining the operation principle of the line drawing emphasis circuit shown in FIG. 7.

16 is a block diagram showing a detailed configuration of a feature extraction unit shown in FIG. 7.

17 is a block diagram showing a detailed configuration of a feature extraction unit shown in FIG. 7.

18 is a block diagram showing a detailed configuration of a feature extraction unit shown in FIG.

19 is a block diagram showing a detailed configuration of a feature extraction unit shown in FIG.

20 is a block diagram illustrating a detailed configuration of a feature extraction unit illustrated in FIG.

FIG. 21 is a block diagram showing a detailed configuration of a feature extraction unit shown in FIG. 7.

22 is a diagram showing a relationship between pixel positions used in the feature extracting unit shown in FIG. 7.

FIG. 23 is a diagram for explaining the operation principle of the feature extraction unit shown in FIG. 7.

FIG. 24 is a diagram for explaining the operation principle of the feature extraction unit shown in FIG. 7.

FIG. 25 is a diagram for explaining the operation principle of the feature extraction unit shown in FIG. 7.

FIG. 26 is a diagram for explaining the operation principle of the feature extraction unit shown in FIG. 7.

27 is a block diagram showing a detailed configuration of a post-processing unit shown in FIG. 7.

28 is a block diagram showing a detailed configuration of the line drawing portion signal post-processing circuit shown in FIG. 27. FIG.

29 is a block diagram showing a detailed configuration of the line drawing portion signal post-processing circuit shown in FIG. 27. FIG.

30 is a block diagram showing a detailed configuration of the line drawing portion signal post-processing circuit shown in FIG. 27.

31 is a block diagram showing a detailed configuration of a line drawing portion signal post-processing circuit shown in FIG. 27.

FIG. 32 is an FRS of the line drawing portion signal post-processing circuit shown in FIG. 27.
It is a figure explaining T signal.

FIG. 33 is a diagram for explaining the operation of the line drawing portion signal post-processing circuit shown in FIG. 27.

FIG. 34 is a diagram showing an example of a conventional line drawing portion determination circuit.

35 is a block diagram showing a detailed configuration of the edge signal post-processing circuit shown in FIG. 27.

FIG. 36 is a diagram showing an example of an edge signal pattern of the edge signal post-processing circuit shown in FIG. 27.

37 is a block diagram showing a detailed configuration of the selection circuit shown in FIG. 7. FIG.

38 is a block diagram showing a detailed configuration of the selection circuit shown in FIG. 7. FIG.

39 is a block diagram showing a detailed configuration of the selection circuit shown in FIG. 7. FIG.

FIG. 40 is an operation timing chart of the selection circuit shown in FIGS. 37 to 39.

41 is a block diagram showing a detailed configuration of the thinning circuit shown in FIG.

42 is an operation timing chart of the thinning circuit shown in FIG. 41. FIG.

43 is a block diagram showing a detailed configuration of the smoothing circuit shown in FIG.

44 is an operation timing chart of the smoothing circuit shown in FIG. 43.

45 is an operation timing chart of the smoothing circuit shown in FIG. 43.

46 is a block diagram showing a detailed configuration of the comprehensive determination circuit shown in FIG.

FIG. 47 is a diagram showing an example of color distribution of a specific original.

FIG. 48 is a diagram showing an example of color distribution of a specific original.

49 is a block diagram showing a detailed configuration of the bank switching means shown in FIG. 46.

50 is an operation timing chart of the bank switching means shown in FIG. 49.

51 is a block diagram showing a detailed configuration of the integrating circuit 1 shown in FIG. 46. FIG.

52 is a block diagram showing a detailed configuration of the serial-parallel converter shown in FIG. 51. FIG.

53 is a timing chart of the serial-parallel converter shown in FIG. 52.

54 is a block diagram showing a detailed configuration of the IIR shown in FIG. 51.

55 is a diagram showing an example of the processing result by the IIR shown in FIG. 54.

56 is a diagram showing an example of the processing result by the IIR shown in FIG. 54.

57 is a diagram showing an example of the processing result by the IIR shown in FIG. 54.

58 is a block diagram showing a detailed configuration of the average value circuit shown in FIG. 54.

FIG. 59 is an operation timing chart of the average value circuit shown in FIG. 58.

FIG. 60 is a block diagram showing a detailed configuration of the parallel / serial converter shown in FIG. 51.

FIG. 61 is an operation timing chart of the parallel-serial converter shown in FIG. 60.

62 is a block diagram showing a detailed configuration of the integrating circuit 2 shown in FIG. 46. FIG.

63 is a block diagram showing a detailed configuration of the IIR shown in FIG. 62.

64 is an operation timing chart of the IIR shown in FIG. 63.

65 is a block diagram showing a detailed configuration of the volume ratio determination circuit shown in FIG. 46. FIG.

FIG. 66 is a timing chart of SRAM control.

67 is a block diagram showing a detailed configuration of the counter circuit shown in FIG. 65.

68 is a block diagram showing a detailed configuration of the serial-parallel converter shown in FIG. 65. FIG.

69 is an operation timing chart of the serial-parallel converter shown in FIG. 68.

70 is a block diagram showing a detailed configuration of a counter group 3620 shown in FIG. 65.

71 is a control timing chart of the counter group 3620 shown in FIG. 70.

72 is a block diagram showing a detailed configuration of the HIT signal generator shown in FIG. 65. FIG.

FIG. 73 is a diagram showing division of main scanning and sub-scanning in this embodiment.

FIG. 74 is a flow chart of ROM ID check in the present embodiment.

FIG. 75 is a diagram showing an example of a test document in this example.

FIG. 76 is a flowchart showing an outline of operation processing in the device of the present embodiment.

77 is a diagram showing an example of an operation unit in the device of the present embodiment. FIG.

FIG. 78 is a diagram for explaining a method of calibrating image reading characteristics in the image reading apparatus of this embodiment.

FIG. 79 is a diagram for explaining a method of calibrating the image reading characteristic in the conventional image reading apparatus.

[Explanation of symbols]

 104 image feature detection circuit 105 smoothing circuit 106 thinning circuit 110 comprehensive judgment circuit 118 bank switching means 101, 107, 108, ROM 136, 137, 138, 139 SRAM 122, 123 integration circuit 148 counting register 201 image scanner 202 printer 210 CCD 309 Judgment circuit 310 Copy prohibition means 311 CPU 312-1, 312-2, 312-3 Calibration means 651 Standard white plate for calibration

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location G06F 15/64 400 C (72) Inventor Yasumichi 3-30-2 Shimomaruko, Ota-ku, Tokyo Kiya Non-Incorporated (72) Inventor Koichi Ishimoto 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Go Aoyagi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. Within

Claims (1)

[Claims] 1. An image reading unit for reading a document image, an image signal processing unit for electrically processing a read image signal from the image reading unit, and an image signal processing unit for processing the image signal by the image signal processing unit. A determination unit that determines the presence or absence of a characteristic and a specific document registered in advance; and a calibration unit that reads a standard document whose density is controlled and calibrates variations in the reading characteristics of the image reading unit based on the reading result, The image processing apparatus, wherein the proofreading unit performs the proofreading by reading the standard original document at a plurality of locations within a reading range of the image reading unit.