JPH07193560A - Transmission line signal switching system - Google Patents

Transmission line signal switching system

Info

Publication number
JPH07193560A
JPH07193560A JP5330287A JP33028793A JPH07193560A JP H07193560 A JPH07193560 A JP H07193560A JP 5330287 A JP5330287 A JP 5330287A JP 33028793 A JP33028793 A JP 33028793A JP H07193560 A JPH07193560 A JP H07193560A
Authority
JP
Japan
Prior art keywords
difference
delay
transmission path
transmission
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5330287A
Other languages
Japanese (ja)
Other versions
JP2771440B2 (en
Inventor
Isao Daito
功 大東
Kiyoji Uchiumi
喜代治 内海
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Miyagi Ltd
Original Assignee
NEC Corp
NEC Miyagi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Miyagi Ltd filed Critical NEC Corp
Priority to JP5330287A priority Critical patent/JP2771440B2/en
Publication of JPH07193560A publication Critical patent/JPH07193560A/en
Application granted granted Critical
Publication of JP2771440B2 publication Critical patent/JP2771440B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Electronic Switches (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To precisely detect a phase and to realize complete no-hit switch by measuring the absolute delay time difference and a frame phase difference of two transmission lines. CONSTITUTION:In an absolute delay difference detection circuit 14, a transmission-side marker 105 from a marker generation circuit 13 and markers 107a and 107b turned back from opposite stations are respectively timing- compared so as to measure absolute delay time. Then, the absolute delay differences are detected. A delay control circuit 17 calculates a final correction delay difference from absolute delay difference information 109 and frame phase difference information 110. Then, delay circuits 16 and 18 are controlled and the phases of two reception signals are matched. A selector 19 switches the reception signals whose phases are matched without bit. In the calculation of the correction delay difference in the delay control circuit 17, whether or not the delay difference is equal to or more than a frame period is judged from the absolute delay difference, and the correction delay difference is calculated from the known frame period and the frame phase difference.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は伝送路信号切替方式に関
し、特にCCITT G707,708,709に勧告
されているSDH(Synchronous Digi
tal Hierareky)方式の同期伝送装置にお
いて送信装置から異なる伝送路を経て入力されたNNI
(Network Node Interface)フ
レーム構成の受信伝送路信号を無瞬断で切り替える伝送
路信号切替方式に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission path signal switching system, and in particular, SDH (Synchronous Digi) recommended in CCITT G707, 708, 709.
TNI Hierareky) synchronous transmission apparatus, the NNI input from the transmission apparatus via different transmission paths.
(Network Node Interface) The present invention relates to a transmission path signal switching method for switching a reception transmission path signal having a frame structure without interruption.

【0002】[0002]

【従来の技術】従来、この種の伝送路信号切替方式を用
いたシステム構成例を図3に示す。図3はSDH方式同
期伝送装置のシステム構成を示すブロック図である。
2. Description of the Related Art Conventionally, FIG. 3 shows an example of a system configuration using this type of transmission path signal switching system. FIG. 3 is a block diagram showing the system configuration of an SDH system synchronous transmission device.

【0003】本同期伝送装置は、フレーム構成がSTM
−1(Synchronous Transport
Mode−1)で伝達方式がATM(Asynchon
ous Tranfer Mode)方式のものであ
る。図3のA局において、VC(バーチャルコンテナ)
パス生成終端装置3で生成されたVC−3,4パスを入
力とするSOH(Section Over Hea
d)生成終端装置1では、送信されるNNIフレーム構
成の伝送路信号を2分岐し、同一の信号をそれぞれ伝送
路5a、伝送路5bの送信側へ送信する。伝送路5a、
5bはそれぞれ送受信が別個の4線式伝送路で冗長関係
にある。
The frame structure of this synchronous transmission apparatus is STM.
-1 (Synchronous Transport)
The transmission method is ATM (Asynchon) in Mode-1).
It is of a House Transfer Mode system. At station A in Figure 3, VC (Virtual Container)
SOH (Section Over Hea) with VC-3, 4 paths generated by the path generation termination device 3 as input
d) In the generation / termination device 1, the transmission path signal having the NNI frame structure to be transmitted is branched into two, and the same signal is transmitted to the transmission sides of the transmission path 5a and the transmission path 5b, respectively. Transmission line 5a,
5b is a 4-wire type transmission line for which transmission and reception are separate, and has a redundant relationship.

【0004】B局において、伝送路5a、伝送路5bよ
りSOH生成終端装置2に入力された各々の伝送路信号
は、切替部で一方が選択された後、VCパス生成終端装
置4へ送出される。また、B局からA局方向についても
上記と同様である。SOH生成終端装置1、2における
切替部は、無瞬断切替を行うために先ず伝送路1、2か
らの受信伝送路信号の位相を合わせ、それから切替えを
行うが、この位相を合わせるためには位相差を検出する
必要がある。この位相差検出はフレーム同期信号の位相
差を検出するのが一般的である。
In the B station, each transmission path signal input to the SOH generating and terminating device 2 from the transmission paths 5a and 5b is sent to the VC path generating and terminating device 4 after one of them is selected by the switching unit. It The same applies to the direction from station B to station A. The switching units in the SOH generation termination devices 1 and 2 first match the phases of the reception transmission path signals from the transmission paths 1 and 2 and then perform the switching in order to perform the hitless switching. It is necessary to detect the phase difference. This phase difference detection generally detects the phase difference of the frame synchronization signal.

【0005】[0005]

【発明が解決しようとする課題】このように従来の伝送
路信号切替方式は、2つの異なる経路を経て入力される
受信伝送路信号の遅延差を検出するのにフレーム同期信
号を用いてフレーム位相差を検出しているが、このフレ
ーム位相差がフレーム周期以内であれば問題ないが、遅
延がフレーム周期以上あった場合検出ができなくなる。
このため例えばフレーム同期信号あるいはマーカをマル
チフレームで挿入したりしてフレーム周期以上の遅延差
を検出するが、この場合マルチフレームとなるので検出
精度が低下したり、また検出範囲をオーバーする可能性
があり不確実であるという問題がある。
As described above, according to the conventional transmission line signal switching system, the frame synchronization signal is used to detect the delay difference between the reception transmission line signals input via two different routes. Although the phase difference is detected, there is no problem if this frame phase difference is within the frame period, but if the delay is more than the frame period, it cannot be detected.
For this reason, for example, a frame synchronization signal or a marker is inserted in multiple frames to detect a delay difference of a frame period or more. However, in this case, since multiple frames are used, the detection accuracy may decrease, or the detection range may be exceeded. There is a problem that there is uncertainty.

【0006】[0006]

【課題を解決するための手段】本発明の伝送路信号切替
方式は、SDHに関する基本勧告のCCITT G70
7,708,709に規定するNNIフレーム構成の伝
送路信号を冗長関係にある2つの4線式の伝送路を介し
送受信するA局とこれに対向するB局とのそれぞれの受
信側で2つの前記伝送路からの受信伝送路信号を受信し
位相を合わせてから無瞬断で交互に切替える伝送路信号
切替方式において、前記A局あるいはB局は、前記伝送
路信号のSOH部分に遅延測定用のマーカを挿入した送
信伝送路信号を2つの前記伝送路に同時に送信しまた2
つの前記受信伝送路信号からそれぞれ前記マーカを抽出
しこれを折返しマーカに変換し対となる前記送信伝送路
信号のSOH部分に挿入して折返し、また2つの前記受
信伝送路信号からそれぞれ前記折返しマーカを抽出し送
信した前記マーカとの時間差をそれぞれ測定しこの測定
値の1/2を各前記伝送受信側の絶対遅延時間としこの
絶対遅延時間の時間差から2つの前記受信伝送路間の絶
対遅延差を算出する一連の手段と、2つの前記受信伝送
路信号のフレーム同期信号のフレーム位相差を検出する
手段と、前記絶対遅延差と前記フレーム位相差とから正
確な補正遅延差を算出する手段と、前記補正遅延差から
前記受信伝送路信号の遅延量をそれぞれ制御し位相を合
わせる手段と、同一位相となった前記受信伝送路信号を
外部の切替信号により一方を選択して切替える手段とを
備えている。
The transmission path signal switching system of the present invention is based on CCITT G70 of the basic recommendation concerning SDH.
No. 7, 708, and 709, the transmission line signals of the NNI frame structure are transmitted and received via the two 4-wire transmission lines in the redundant relationship, and two stations are provided on the receiving side of each of the A station and the B station opposite thereto. In a transmission path signal switching system in which a reception transmission path signal from the transmission path is received and the phases are matched, and the phases are alternately switched without interruption, the station A or the station B is for delay measurement in the SOH portion of the transmission path signal. The transmission transmission line signal in which the marker is inserted is transmitted to the two transmission lines at the same time.
The marker is extracted from each of the two reception transmission path signals, converted into a folding marker, inserted into the SOH portion of the transmission transmission path signal forming a pair, and folded, and the folding markers are respectively returned from the two reception transmission path signals. And measuring the time difference with the transmitted marker, and taking 1/2 of this measured value as the absolute delay time of each transmission / reception side, from the time difference of this absolute delay time, the absolute delay difference between the two reception transmission lines. A means for calculating a frame phase difference between the two frame synchronization signals of the reception transmission path signals, and a means for calculating an accurate corrected delay difference from the absolute delay difference and the frame phase difference. A means for controlling the delay amount of the reception transmission path signal from the corrected delay difference to adjust the phase, and the reception transmission path signal having the same phase as an external switching signal. Ri and means for switching to select one.

【0007】特に、前記補正遅延差を算出する手段は、
前記絶対遅延差をA、前記位相差をB、前記伝送路信号
のフレーム周期をC、また前記絶対遅延差の予測される
測定誤差をα(絶対値)、またA/Cの計算値の小数点
以上の0を含む整数をnとした時に補正遅延差は、C
(1+n)−A〈α、かつB〈αの時は、C(1+n)
+Bで算出し、また、C(1+n)−A〈α、かつB〉
αの時、およびC(1+n)−A〉αの時は、nC+B
で算出する方式でも良い。
In particular, the means for calculating the correction delay difference is
The absolute delay difference is A, the phase difference is B, the frame period of the transmission path signal is C, the predicted measurement error of the absolute delay difference is α (absolute value), and the decimal point of the calculated value of A / C. When the integer including 0 above is n, the correction delay difference is C
When (1 + n) -A <α and B <α, C (1 + n)
+ B, and C (1 + n) -A <α and B>
When α and C (1 + n) -A> α, nC + B
The method of calculating may be used.

【0008】[0008]

【実施例】次に本発明の一実施例について図面を参照し
説明する。図1は本実施例の切替部構成を示すブロック
図である。図2は図1における補正遅延差の算出方式を
説明するタイミングチャートである。図3は図1の適用
を含むシステムの構成を示すブロック図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the switching unit of this embodiment. FIG. 2 is a timing chart for explaining the method of calculating the correction delay difference in FIG. FIG. 3 is a block diagram showing the configuration of a system including the application of FIG.

【0009】図1において、図1は図3で示したA局の
SOH生成終端装置1の伝送路信号切替部を示すもので
あるが、B局のSOH生成終端装置2も同様な構成であ
る。従って以下の各部動作説明はA局についてのもので
あるがB局にも共通する。SOH生成終端部1からの送
信信号103は送信インタフェース11a、11bに入
力され、それぞれマーカ発生回路13からのマーカ10
5をSOHの予備ポジションであるZ1バイトに挿入
し、送信伝送路信号101a、101bとして伝送路5
a、5bの送信路へ送出する。
In FIG. 1, FIG. 1 shows the transmission line signal switching unit of the SOH generation termination device 1 of the station A shown in FIG. 3, but the SOH generation termination device 2 of the station B also has the same configuration. . Therefore, the following description of the operation of each section is for the A station, but is common to the B station. The transmission signal 103 from the SOH generation termination unit 1 is input to the transmission interfaces 11a and 11b, and the marker 10 from the marker generation circuit 13 is supplied to each.
5 is inserted into the Z1 byte which is the spare position of the SOH, and the transmission path 5 is used as the transmission transmission path signals 101a and 101b.
It is sent to the transmission paths a and 5b.

【0010】一方、伝送路5a、5bの受信路からの受
信伝送路信号102a、102bはそれぞれ受信インタ
フェース12a、12bに入力され、ここでNNIフレ
ームのSOHが終端される。
On the other hand, the reception transmission path signals 102a and 102b from the reception paths of the transmission paths 5a and 5b are input to the reception interfaces 12a and 12b, respectively, where the SOH of the NNI frame is terminated.

【0011】一般に、2つの異なる伝送路を経た伝送路
信号が入力された場合、線路長差があると遅延量が異な
る為にフレーム位相が異なる。即ち、受信伝送路信号1
02a、102bは位相が一致していないのが通常であ
る。受信インタフェース102a、102bでは先ずB
局側で挿入されたZ1バイトのマーカ106a、106
bを抽出し、それぞれ、B局側に折返すために送信イン
タフェース11a、11bに入力する。送信インタフェ
ース11a、11bはこのZ1バイトのマーカ信号を今
度はZ2バイトに挿入し送信する。
Generally, when a transmission line signal is input via two different transmission lines, if there is a difference in line length, the amount of delay will be different, and therefore the frame phase will be different. That is, the reception transmission path signal 1
Normally, 02a and 102b do not have the same phase. In the receiving interfaces 102a and 102b, first B
Z1 byte markers 106a and 106 inserted on the station side
b is extracted and input to the transmission interfaces 11a and 11b for returning to the B station side, respectively. The transmission interfaces 11a and 11b insert this Z1 byte marker signal into the Z2 byte and transmit it.

【0012】また、受信インタフェース11a、11b
は、B局側で折返された自局のZ2バイトのマーカ10
7a、107bを抽出し、絶対遅延差検出回路14にそ
れぞれ入力する。絶対遅延差検出回路14において、自
局送信のマーカ105a、105bとB局折返しのマー
カ107a、107bとのタイミングを比較し、その時
間差を各々測定し、各々結果の二分の一を片方向の絶対
遅延時間とし、更に両者の差を方伝送路5a、5bの受
信側片方の絶対遅延差とする。
Further, the reception interfaces 11a and 11b
Is the Z2 byte marker 10 of its own station returned from the B station.
7a and 107b are extracted and input to the absolute delay difference detection circuit 14, respectively. In the absolute delay difference detection circuit 14, the timings of the markers 105a and 105b of the own station transmission and the markers 107a and 107b of the B station return are compared, and the time differences are measured, respectively, and one half of each result is unidirectional. The delay time is set, and the difference between the two is set as the absolute delay difference on the receiving side of one of the transmission lines 5a and 5b.

【0013】この値は、Z1からZ2へ乗せ替えたこと
による誤差等を含むので、この誤差を補正するためにフ
レーム位相差検出回路15により、伝送路5a、5bの
フレーム位相差も検出する。これは受信インタフェース
12a、12bで終端されたフレーム同期信号108
a、108bから検出される。
Since this value includes an error and the like due to the transfer from Z1 to Z2, the frame phase difference detection circuit 15 also detects the frame phase difference of the transmission lines 5a and 5b in order to correct this error. This is the frame synchronization signal 108 terminated at the reception interfaces 12a and 12b.
a, 108b.

【0014】絶対遅延差検出回路14から出力された絶
対遅延差情報109と、フレーム位相差検出回路15か
ら出力されたフレーム位相差情報110とを入力する遅
延制御回路17は、この両情報から伝送路5a、5b間
の補正遅延差を求め、その結果により遅延回路16、1
8の遅延量を制御する。即ち遅延回路16、18に書き
込まれた受信データを遅延回路16、18から読出す時
に、切替先の位相が進んでいる場合には、切替先の遅延
量を増やし、切替先の位相が遅れている場合は、切替先
の遅延を減らすことで、2つの信号の読み出し位相が同
一となるように制御して2つの伝送路からくる受信信号
の位相を一致させる。位相が一致した受信信号はセレク
タ12において、外部からの制御信号により一方がセレ
クトされるが、この切替の時にデータに不連続や重複が
起きることはなく、また無瞬断で切替を行うことができ
る。
The delay control circuit 17, which receives the absolute delay difference information 109 output from the absolute delay difference detection circuit 14 and the frame phase difference information 110 output from the frame phase difference detection circuit 15, transmits the information from both. The correction delay difference between the paths 5a and 5b is obtained, and the delay circuit 16
8 delay amount is controlled. That is, when the received data written in the delay circuits 16 and 18 is read from the delay circuits 16 and 18, if the phase of the switching destination is advanced, the delay amount of the switching destination is increased and the phase of the switching destination is delayed. If so, the delay at the switching destination is reduced so that the read phases of the two signals are the same, and the phases of the received signals coming from the two transmission lines are matched. One of the received signals having the same phase is selected by the control signal from the outside in the selector 12, but there is no discontinuity or duplication of data at the time of this switching, and switching can be performed without interruption. it can.

【0015】次に、遅延制御回路17における補正遅延
差を求める方法について説明する。測定された絶対遅延
差は、先に説明したように若干の誤差が生じるが、一方
フレーム位相差は正確に検出できる。絶対遅延差はフレ
ーム位相差がフレーム周期を超えたかどうかを判断する
ためのもので、最終的な遅延差は既知であるフレーム周
期と正確に検出できるフレーム位相差とで算出する。
Next, a method of obtaining the corrected delay difference in the delay control circuit 17 will be described. The measured absolute delay difference has a slight error as described above, while the frame phase difference can be accurately detected. The absolute delay difference is for determining whether or not the frame phase difference exceeds the frame period, and the final delay difference is calculated by the known frame period and the frame phase difference that can be accurately detected.

【0016】即ち、図2に示すように(図2は絶対遅延
差が1フレーム周期以上になった例を示す)絶対遅延差
情報109の絶対遅延差をA、フレーム位相差情報11
0のフレーム位相差をB、伝送路信号のフレーム周期を
C、また絶対遅延差の予測される測定誤差をα(絶対
値)とした時に補正遅延差は、C(1+n)−A〈α
で、かつB〈αの時は、C(1+n)+Bで算出し、ま
た、C(1+n)−A〈αで、かつB〉αの時、および
C(1+n)−A〉αの時は、nC+Bで算出する。
That is, as shown in FIG. 2 (FIG. 2 shows an example in which the absolute delay difference is one frame period or more), the absolute delay difference of the absolute delay difference information 109 is A, and the frame phase difference information 11
When the frame phase difference of 0 is B, the frame period of the transmission path signal is C, and the predicted measurement error of the absolute delay difference is α (absolute value), the corrected delay difference is C (1 + n) -A <α
And when B <α, C (1 + n) + B is calculated, and when C (1 + n) −A <α and B> α and C (1 + n) −A> α , NC + B.

【0017】但し、nはA/Cの計算値の小数点以上の
0を含む整数部分として算出する。
However, n is calculated as an integer part including 0 above the decimal point of the calculated value of A / C.

【0018】[0018]

【発明の効果】以上説明したように本発明は2つの異な
る伝送路を経た受信信号の遅延量の違いから生ずる位相
差の検出を、送信側から送出したマーカを対向局で折返
すことにより伝送路の絶対遅延時間を測定し、同時にフ
レーム同期信号によりフレーム位相差を測定してこの両
者から補正遅延差を求めているので、正確で安定した位
相差検出ができる。従って完全な無瞬断切替ができると
いう効果がある。
As described above, according to the present invention, the detection of the phase difference caused by the difference in the delay amount of the received signal passing through two different transmission lines is transmitted by returning the marker sent from the transmitting side to the opposite station. Since the absolute delay time of the path is measured, and at the same time, the frame phase difference is measured by the frame synchronization signal and the corrected delay difference is obtained from the both, accurate and stable phase difference detection can be performed. Therefore, there is an effect that complete non-instantaneous switching can be performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.

【図2】図1における補正遅延差を求めるタイミングチ
ャート図である。
FIG. 2 is a timing chart diagram for obtaining a correction delay difference in FIG.

【図3】図1を用いたシステムを示すブロック図であ
る。
FIG. 3 is a block diagram showing a system using FIG.

【符号の説明】[Explanation of symbols]

1,2 SOH生成終端装置 3,4 VCパス生成終端装置 5a,5b 伝送路 11a,11b 送信インタフェース 12a,12b 受信インタフェース 13 送信マーカ発生部 14 絶対遅延差検出回路 15 フレーム位相差検出回路 16,18 遅延回路 17 遅延制御回路 19 セレクタ 1, 2 SOH generation termination device 3, 4 VC path generation termination device 5a, 5b Transmission line 11a, 11b Transmission interface 12a, 12b Reception interface 13 Transmission marker generation part 14 Absolute delay difference detection circuit 15 Frame phase difference detection circuit 16, 18 Delay circuit 17 Delay control circuit 19 Selector

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 SDHに関する基本勧告のCCITT
G707,708,709に規定するNNIフレーム構
成の伝送路信号を冗長関係にある2つの4線式の伝送路
を介し送受信するA局とこれに対向するB局とのそれぞ
れの受信側で2つの前記伝送路からの受信伝送路信号を
受信し位相を合わせてから無瞬断で交互に切替える伝送
路信号切替方式において、前記A局あるいはB局は、前
記伝送路信号のSOH部分に遅延測定用のマーカを挿入
した送信伝送路信号を2つの前記伝送路に同時に送信し
また2つの前記受信伝送路信号からそれぞれ前記マーカ
を抽出しこれを折返しマーカとして対となる前記送信伝
送路信号のSOH部分に挿入して折返しまた2つの前記
受信伝送路信号からそれぞれ前記折返しマーカを抽出し
送信した前記マーカとの時間差をそれぞれ測定しこの測
定値の1/2を各前記伝送路受信側の絶対遅延時間とし
この絶対遅延時間の時間差から2つの前記受信伝送路間
の絶対遅延差を算出する一連の手段と、2つの前記受信
伝送路信号のフレーム同期信号のフレーム位相差を検出
する手段と、前記絶対遅延差と前記フレーム位相差とか
ら正確な補正遅延差を算出する手段と、前記補正遅延差
から前記受信伝送路信号の遅延量をそれぞれ制御し位相
を合わせる手段と、同一位相となった前記受信伝送路信
号を外部の切替信号により一方を選択して切替える手段
とを備えることを特徴とする伝送路信号切替方式。
1. CCITT of basic recommendation on SDH
Two stations are respectively provided on the receiving side of the station A and the station B opposite to the station A, which transmits and receives the transmission path signals having the NNI frame structure defined in G707, 708, and 709 via the two 4-wire transmission paths in the redundant relationship. In a transmission path signal switching system in which a reception transmission path signal from the transmission path is received and the phases are matched, and the phases are alternately switched without interruption, the station A or the station B is for delay measurement in the SOH portion of the transmission path signal. The transmission transmission line signal in which the marker is inserted is simultaneously transmitted to the two transmission lines, and the markers are extracted from each of the two reception transmission line signals, and the SOH portion of the transmission transmission line signal that forms a pair is used as a folding marker. And the return marker is extracted from each of the two reception transmission path signals and the time difference from the transmitted marker is measured. A series of means for calculating an absolute delay time between the two reception transmission paths from the absolute delay time of the transmission path receiving side, and the frame position of the frame synchronization signal of the two reception transmission path signals. Means for detecting a phase difference, means for accurately calculating a corrected delay difference from the absolute delay difference and the frame phase difference, and means for controlling the delay amount of the reception transmission path signal from the corrected delay difference to match the phase And a means for selecting and switching one of the reception transmission path signals having the same phase by an external switching signal, and a switching means for switching the transmission path signal.
【請求項2】 前記補正遅延差を算出する手段は、前記
絶対遅延差をA、前記フレーム位相差をB、前記伝送路
信号のフレーム周期をC、前記絶対遅延差の予測される
測定誤差をα(絶対値)、またA/Cの値の小数点以上
の0を含む整数をnとした時に補正遅延差は、 C(1+n)−A〈α、かつB〈αの時は、C(1+
n)+Bで算出し、 また、C(1+n)−A〈α、かつB〉αの時、および
C(1+n)−A〉αの時は、nC+Bで算出すること
を特徴とする請求項1記載の伝送路信号切替方式。
2. The means for calculating the corrected delay difference comprises: the absolute delay difference A, the frame phase difference B, the frame period of the transmission path signal C, and a predicted measurement error of the absolute delay difference. When α (absolute value) or an integer including 0 of the decimal point of the A / C value is n, the correction delay difference is C (1 + n) -A <α, and when B <α, C (1+
n) + B, and when C (1 + n) -A <α and B> α, and when C (1 + n) -A> α, nC + B is calculated. Transmission line signal switching method described.
JP5330287A 1993-12-27 1993-12-27 Transmission line signal switching method Expired - Lifetime JP2771440B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5330287A JP2771440B2 (en) 1993-12-27 1993-12-27 Transmission line signal switching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5330287A JP2771440B2 (en) 1993-12-27 1993-12-27 Transmission line signal switching method

Publications (2)

Publication Number Publication Date
JPH07193560A true JPH07193560A (en) 1995-07-28
JP2771440B2 JP2771440B2 (en) 1998-07-02

Family

ID=18230969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5330287A Expired - Lifetime JP2771440B2 (en) 1993-12-27 1993-12-27 Transmission line signal switching method

Country Status (1)

Country Link
JP (1) JP2771440B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006148329A (en) * 2004-11-17 2006-06-08 Fujitsu Ltd Phase adjustment method and apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006148329A (en) * 2004-11-17 2006-06-08 Fujitsu Ltd Phase adjustment method and apparatus
JP4651364B2 (en) * 2004-11-17 2011-03-16 富士通株式会社 Phase adjustment method and apparatus

Also Published As

Publication number Publication date
JP2771440B2 (en) 1998-07-02

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