JPH07193477A - Delay circuit - Google Patents

Abstract

PURPOSE:To provide a delay circuit for controlling delay time from the outside without increasing the number of control signal lines. CONSTITUTION:The thickness of the gate oxide films of (n) pieces of MOS Tr1-Trn is made mutually different, and threshold voltage levels are made mutually different. A threshold voltage at a prescribed level is impressed from a common gate voltage input terminal 14 to the (n) pieces of MOS Trs. The time constant of a value corresponding to the combination of MOS Trs in the ON state among the (n) pieces of MOS Trs is provided by a time constant circuit installed at an input stage and composed of a resistor R0 and (n) pieces of capacitors C1-Cn. When an input signal is outputted through this time constant circuit, the desired delay time can be acquired.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit, and more particularly to a delay circuit for adjusting a delay time of a signal in an input portion and an output portion of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, as a method for controlling the propagation time of a signal in a logic circuit, for example, Japanese Patent Laid-Open No. 61-22461.
As described in Japanese Patent Laid-Open No. 6, a MOS transistor in which a time constant of a delay circuit is set to be conductive in order to change a delay time of a signal.
It is changed by controlling the number of FET transistors (hereinafter referred to as MOSTr).

A method of controlling the number of conducting MOSTrs will be described with reference to FIGS. 5 and 6. 7 and 8 show a delay circuit described in the above-mentioned Japanese Patent Laid-Open No. 61-224616.

FIG. 7 shows a structure in which a delay circuit having a time constant circuit is provided between the logic circuits A and B. That is, n Ms provided between the logic circuits A and B
A delay circuit is configured to include OSTr1 to OSTrn and a capacitor C0 provided between the signal line between the logic circuits A and B and the ground. Then, G1 to G of each MOSTr
n by controlling the voltage level to n
Several of Tr are turned on, and a delay circuit is constituted by a time constant circuit formed by this on resistance and the capacitance of the capacitor C0.

On the other hand, an application of the circuit of FIG. 7 is shown in FIG. In FIG. 8, each MOSTr
Control circuit 60 for applying a predetermined voltage to the gate terminals 1 to n
A delay circuit including is shown.

Here, the control circuit 60 is, for example, a counter circuit, and it is conceivable that a predetermined voltage is applied to the gate terminal of each MOSTr according to the count value as a result of performing the counting operation according to the control signal 61.
In FIG. 8, the same parts as those in FIG. 7 are indicated by the same reference numerals.

A control circuit 6 using a shift register
A known example in which 0 is constituted is disclosed in JP-A-62-231515.

[0008]

Among the conventional delay circuits described above, the delay circuit shown in FIG. 7 has a MOSTr for switching the time constant in order to control the delay time.
1, 2, ..., N gate terminals G1, G2, ..., Gn
In addition, a control signal for turning on and off the MOSTr must be individually applied. Therefore, the number of control signal lines must be the same as the number of MOSTrs, and there is a drawback that the number of control signal lines is significantly increased when the range of delay time to be changed and the fineness are increased. .

Further, in the circuit shown in FIG. 8, a control circuit such as a counter circuit and a decoder circuit for producing a control signal to be applied to each gate terminal of the MOSTr1, 2, ..., N for switching the time constant. Since 60 is provided, the number of control signals 61 of the control circuit required to change the delay time can be reduced. However, an additional mounting area occupied by the control circuit 60 is required, and
There is a drawback that extra power is consumed by the control circuit.

The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to externally control the delay time without increasing the number of control signal lines and without increasing the power consumption. It is to provide a delay circuit that can do so.

[0011]

SUMMARY OF THE INVENTION A delay circuit according to the present invention includes n switching elements (n is an integer of 2 or more, the same applies hereinafter) having different threshold voltage levels, and a predetermined level for the n switching elements. A common terminal for commonly applying a threshold voltage of, and a time constant circuit that realizes a time constant of a value corresponding to a combination of the switching elements in the ON state among the n switching elements, An input signal is output through the time constant circuit.

[0012]

The on / off control of n switching elements (MOSTr) having mutually different threshold voltage levels is performed by a common control voltage, and various time constants are controlled by a combination of the switching elements in the on state among the n switching elements. To do. By doing so, a delay circuit having only one control signal and low power consumption can be obtained.

[0013]

The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a delay circuit according to the present invention, and the same parts as those in FIGS. 7 and 8 are designated by the same reference numerals. In the figure, a delay circuit C according to an embodiment of the present invention is configured to include a gate voltage input terminal 14 commonly provided for applying a threshold voltage of a predetermined level to the gate terminals G1 to Gn of the MOS Tr1 to n. ing. The details will be described below.

In the figure, the delay circuit of this embodiment has a signal input terminal 10 and a signal output terminal 11, and a resistance element R0 is provided in series between the signal input terminal 10 and the signal output terminal 11. The resistance element R0 and the signal output terminal 11
, And n are connected to drains and sources, and drain terminals D1, D2, ..., Dn of n MOSTr1, 2, ..., N having different threshold voltages are connected.

The source terminals S1, S2, ... Sn of the MOSTr1, 2 ,.
Cn and resistance elements R1, R2, ..., Rn are connected in parallel, and the other ends of these capacitor elements and resistance elements are all connected to ground.

Further, the gate terminals G1, G2, ..., Gn of the MOSTr1, 2, ..., N are all connected to the common gate voltage input terminal 14 and also to the resistance element 13, and the resistance element 13 is connected. The other end of is connected to ground.

Here, each capacitor element 1, 2, ...,
If the capacitance of n is C1, C2, ..., Cn, MO
STr1, 2, ..., N gate terminals G1, G2, ...
The delay circuit has n time constants according to the voltage value applied to Gn. This operation will be described below.

Now, the threshold voltage Vth of each MOSTr1, 2, ..., N is Vth1 <Vth2 <... <Vthn, respectively.
It is assumed that Then, the gate voltage input terminal 14
, The voltage V supplied from the resistor element 13 appears in the resistance element 13, and this supply voltage is applied to the gate terminals G1, G2, ..., Gn of all the MOSTr1, 2 ,. n MOST
Threshold voltage Vthi and voltage Vth of MOSTri of r
And V have a relationship of V ≦ Vthi, i MOS
Tr becomes conductive. Therefore, the combined capacitance of the capacitor elements connected to each MOSTr is ΣCj (j = 1 to 1).
i), the resistance value of the resistance element R0 and the combined capacitance ΣC
A delay time proportional to the product of j (j = 1 to i) can be obtained.

Therefore, by supplying a voltage equal to or lower than the threshold voltage Vthn to the gate voltage input terminal 14 which is a common terminal, it is possible to change the delay time in n ways without increasing the number of signal lines. In addition, since the control circuit 60 as shown in FIG. 8 is not provided, the mounting area is not increased and the power consumed by the control circuit is not generated, and the number of delay time control signal lines is reduced. Can be configured to.

Next, the threshold voltage levels M are different from each other.
The configuration of OSTr1, 2, ..., N will be described. FIG. 2 shows a vertical sectional view of the MOSTr. MOSTr
In order to change the threshold voltage value, for example, the thickness d of the gate oxide film 22 in the figure may be changed. That is, the threshold voltage level can be increased as the thickness d of the gate oxide film is increased.

However, in this case, if the channel length L and the channel width W of the MOSTr are not changed, the solid line of the characteristic curve of the gate terminal input voltage VGS vs. drain and source current IDS of the MOSTr shown in FIG. As shown, the higher the threshold voltage level, the more ΔVGS / Δ
The on-resistance value indicated by IDS increases, and there is an effect that it becomes larger than the delay time obtained by the product of the combined electrostatic capacitance ΣCj (j = 1 to i) obtained by the resistance element R0 of FIG. 1 and the conductive MOSTr.

In this case, if the channel length L and the channel width W shown in FIG. 2 are reduced, and the channel area is reduced to increase the carrier concentration in the channel portion, it is indicated by a broken line H in FIG. MOS with high threshold voltage level
Even Tr can have the same on-resistance value as MOSTr having a low threshold voltage level. Therefore, the delay time is the resistance element R
It is proportional to the product of the resistance value of 0 and the combined capacitance ΣCj (j = 1 to i) given by the conducting MOSTr.

In FIG. 2, 23 is an n-type semiconductor in the drain portion, 24 is an n-type semiconductor in the source portion, 26 is a P-type semiconductor, and 20 and 21 are silicon oxide films.

From the above points, even if the capacitance of the capacitor element is increased to obtain the required delay time, the MO
The on-resistance value of the STr may be increased, and more flexible selection can be made with respect to easiness of manufacturing in the manufacturing stage.

FIG. 4 shows, as an application example of the circuit of FIG. 1, a circuit configuration in which a correction circuit is added for the case where the signal delay amount changes with temperature. Now, it is assumed that there is a circuit having a characteristic in which a certain temperature is set as a reference temperature, a signal delay amount is large at a temperature lower than the reference temperature, and a signal delay amount is small at a temperature higher than the reference temperature. In this case, a positive temperature coefficient thermistor, which is a temperature sensitive element 15 whose electric resistance decreases on the low temperature side and whose electric resistance increases on the high temperature side, may be connected between the gate voltage input terminal 14 and the ground shown in FIG. .

In such a structure, the DC voltage power source 16
, The signal delay time can be corrected to the same value as the delay time at the reference temperature.

Further, in the circuit having the temperature-delay characteristic opposite to the above example, the same effect can be obtained by using the negative characteristic thermistor for the temperature sensitive element 15.

It goes without saying that similar effects can be obtained with respect to the effects described above, regardless of whether they are composed of individual parts or integrated in a semiconductor integrated circuit.

If the capacitance value of each capacitor element is changed in advance, the variable range of the time constant, that is, the variable range of the delay time can be changed.

In short, in the delay circuits of the above-described embodiments, by increasing or decreasing the DC voltage applied via the common terminal, n MO transistors having different threshold voltages are provided.
MO with STr turned on
Depending on the combination of STr, the delay time is changed by controlling the magnitude of the capacitance of the capacitor element connected in parallel between the signal line of the delayed signal and the ground to change the time constant. There is.

Therefore, since the common terminal, that is, only one terminal is used to control the delay time of the signal, the semiconductor terminal is required to have a plurality of control terminals in the case of logically controlling the delay time. When used in an integrated circuit or the like, the number of signal terminals limited by the package to be mounted can be effectively used for the input / output signal lines used for the original function of the semiconductor integrated circuit.

Further, since the delay element is composed of a time constant circuit composed of passive elements such as a resistance element and a capacitor element, the power consumption of the delay circuit portion can be made sufficiently lower than that of the delay element composed of an active element. .

Further, within the preset variable delay time, even if the delay conditions of other circuits connected to the semiconductor integrated circuit including the delay circuit and transmitting / receiving a signal vary due to secular change, etc. The delay time can be adjusted by changing the DC voltage applied to the voltage input terminal.

Further, in a system in which the delay time of the circuit changes depending on the ambient temperature, if a temperature sensitive element having a positive characteristic or a negative characteristic whose resistance value changes depending on the temperature is added, the delay time can be easily corrected by the temperature. be able to.

In both of the embodiments described above, the desired time constant is realized by the product of one resistance element R0 and the combined electrostatic capacitance of a plurality of capacitor elements, but conversely one capacitor element is used. However, it is obvious that a plurality of series circuits of the resistance element and the MOS switching element may be provided and the product of the combined resistance value may realize the desired time constant. In this case, if the ON resistance of the MOS switching element is used, the resistance element itself can be omitted.

The configuration of such a circuit is shown in FIG.
In FIG. 5, the same parts as those in FIGS. Referring to FIG. 5, n M different threshold voltages are provided in parallel between the delayed signal input unit 10 and the delayed signal output unit 11.
OSTr1, 2, ..., N drain terminals D1, D2
..., Dn and source terminals S1, S2, ..., Sn are connected.

Further, one end of the capacitor element C0 is connected to the source terminals S1, S2, ..., Sn of the MOSTr1, 2, ..., N, and the other end is grounded.

Further, the gate terminals G1, G2, ..., Gn of the MOSTr1, 2, ..., N are all connected to the gate voltage input terminal 14 and at the same time connected to one end of the resistance element 13. The other end of the resistance element 13 is grounded.

Therefore, the delay circuit has n time constants according to the voltage value applied to the gate terminals G1, G2, ..., Gn of the MOSTr1, 2 ,.

To explain this operation, n MO
The threshold voltage Vth of STr1, 2, ..., N is Vth1 <
Vth2 << ... <Vthn, the voltage V supplied from the gate voltage input terminal 14 is the resistance element 1
3, this supply voltage is n MOSTr1, 2, ...
, N gate terminals G1, G2, ..., Gn, and when the threshold voltage Vthi of a certain i-th MOSTri is the same as the voltage supplied from the gate voltage input terminal 14, the i-th MOSTr is When turned on, the parallel combined value of the ON resistances of the i MOSTrs changes to 1 / i times the ON resistance of one MOSTr when the ON resistances of the transistors are the same.

Therefore, by supplying a voltage up to the threshold voltage Vthn of the n-th MOSTr to the gate voltage input terminal 14 which is one signal line, the delay time can be changed in n ways. The threshold voltage is set so as not to exceed the power supply voltage supplied to the circuit.

Also in this embodiment, the control circuit 60 including the counter and the decoder as shown in FIG. 8 is not provided, so that the mounting area is not increased and the power consumed by the control circuit is not generated. In addition, the number of delay time control signal lines is reduced.

Also for each MOSTr in this example, by using the transistor having the structure described in FIGS.
The threshold voltage of each device can be designed to be different as desired. When the on-resistance value of the MOSTr having a high threshold voltage is set to be the same as that of the MOSTr having a low threshold voltage, assuming that these on-resistances are R0n, the delay time is proportional to 1 / (nR0n), and the on-resistance is the threshold voltage. If the configuration depends on
It is proportional to 0ni / (ΣR0ni) (i = 1
~ N).

From the above points, the capacitance of the capacitor element CO may be increased or the ON resistance of the MOSTr may be increased in order to obtain the necessary delay time. It is possible to take flexible choices.

FIG. 6 is a circuit diagram of still another embodiment of the present invention, in which the same parts as those in FIGS. In this example, the temperature sensing element 15 shown in FIG. 4 is provided to the circuit of FIG. 5 to perform temperature compensating in a system in which the delay time of the circuit changes depending on the environmental temperature.

[0047]

As described above, the present invention applies the threshold voltage of a predetermined level to the n switching elements having different threshold voltage levels from the common terminal and is in the ON state. By realizing the time constant having the value corresponding to the combination of the above, there is an effect that the delay time can be controlled from the outside without increasing the number of control signal lines and increasing the power consumption.

As an effect of the delay circuit of the present invention, a plurality of MOSs having different threshold voltages can be obtained by changing the DC voltage applied via one gate voltage input terminal 7.
Type field effect transistor is turned on and off to control the magnitude of the pure resistance component inserted in series in the signal line of the delayed signal, and the capacitor element inserted in parallel in the signal line of the delayed signal. The delay time caused by the capacitance is varied.

Further, since only one gate voltage input terminal is used to control the delay time of the signal, the semiconductor is more difficult than the case where a plurality of control terminals are required when logically controlling the delay time. When used in an integrated circuit or the like, there is an effect that the number of signal terminals limited to the package to be mounted can be effectively used for the input / output signal line used for the original function of the semiconductor integrated circuit.

Further, if the delay time is within a preset variable delay time, even if the delay conditions of other circuits interfacing with the semiconductor integrated circuit including this delay adjusting circuit change due to aging, etc., it is applied to the gate voltage input terminal. It can be adjusted by changing the DC voltage to be applied. Furthermore, in a system where the circuit delay time changes depending on the ambient temperature, when used in combination with a positive or negative characteristic temperature sensitive element whose resistance value changes depending on temperature, the delay time can be easily corrected by temperature. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a delay circuit according to an embodiment of the present invention.

FIG. 2 is a vertical sectional view showing the structure of a MOSTr in the delay circuit of FIG.

FIG. 3 is a characteristic diagram showing gate input voltage-drain / source current characteristics of the MOSTr of FIG.

FIG. 4 is a circuit diagram showing a configuration of a delay circuit according to another embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a delay circuit according to still another embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a delay circuit according to still another embodiment of the present invention.

FIG. 7 is a circuit diagram showing an example of a conventional delay circuit.

FIG. 8 is a circuit diagram showing another example of a conventional delay circuit.

[Explanation of symbols]

 1-n MOSTr 14 Gate voltage input terminal 15 Thermal element C0, C1-Cn Capacitor element R0-Rn Resistance element

Claims (7)

[Claims] 1. N switching elements (n is an integer of 2 or more) having different threshold voltage levels, and a common terminal for commonly applying a predetermined threshold voltage to the n switching elements. , A time constant circuit that realizes a time constant of a value corresponding to a combination of switching elements in the ON state among the n switching elements, and outputs an input signal via the time constant circuit. And a delay circuit. 2. The time constant circuit is provided in correspondence with a resistor provided in an input stage and the n switching elements respectively, and is provided in the resistor when the corresponding switching element is in an ON state. N connected to realize a predetermined time constant
The delay circuit according to claim 1, further comprising: 3. The delay circuit according to claim 2, wherein the time constant circuit has n resistance elements provided in parallel corresponding to the n capacitors. 4. The time constant circuit, wherein the n switching elements are provided in parallel with each other between an input stage and an output stage, and a predetermined time together with a combined resistance value of conduction resistances of the switching elements in an ON state. 2. The delay circuit according to claim 1, wherein the output stage has a capacitor that realizes a constant. 5. The n switching elements are MOS
5. The delay circuit according to claim 1, wherein the delay circuits are transistors, and the gate insulating films of these n transistors have different thicknesses. 6. The delay circuit according to claim 5, wherein the channel areas of the MOS transistors are different from each other. 7. The delay circuit according to claim 1, further comprising means for adjusting a voltage value supplied to the common terminal according to a temperature change.