JPH07184165A - Method and device for decoding moving picture - Google Patents

Abstract

PURPOSE:To provide an output of a picture in an interlacing way with less memory capacity by dividing the result of decoding for each field and writing the result to different areas and setting a write and read address so as to write succeeding decoding result to an area from which the decoding result is read. CONSTITUTION:A code decoding circuit 1 decodes a received code 11 and outputs a decoding result 12 to a decoding circuit 2 and a table rewrite control circuit 3. The circuit 2 reads a reference picture 14 from a storage circuit 8 as required and decodes a picture based on the decoding result 12 and writes a decoding result to the circuit 8. The circuit 3 rewrites a memory address management table 4 based on the decoding result 12. A calculation circuit 5 uses information in a table 4 to calculate a memory address 16 and provides an output to the circuit 8 and provides the output of the memory address to a comparator circuit 6. The circuit 6 compares the memory address for write and read and provides an output of comparison result 18 to a signal generating circuit 17 and gives a decoding stop signal 19 to the circuit 2 to attain an interlace output for the decoding result 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving picture decoding apparatus for decoding a compressed code and performing interlaced scanning to display an image.

[0002]

2. Description of the Related Art A moving image has a very large amount of information, and it is essential to compress the information in order to reduce the cost when transmitting or recording. Although there are several compression methods, a compression method that utilizes correlation with past and future images, such as a method based on the ISO MPEG standard, has high efficiency and is considered promising.

By the way, in the currently popular television, interlaced output is performed in which an image in one frame is interlaced and displayed every other row. However, at the time of compression, for reasons such as good compression efficiency, it is often the case that encoding is performed with a frame structure without interlaced scanning. Therefore, it is often necessary to perform interlaced output after decoding an image encoded with a frame structure. In such a case, conventionally, the following several memories have been used in the moving picture decoding apparatus. (1) Two-frame memory for storing reference images In order to perform inter-frame prediction using reference images of two frames before and after temporally, a memory having a capacity for storing the reference images for these two frames is used. (2) Two-frame memory as frame / interlace conversion buffer Two bidirectional predictive moving images (hereinafter referred to as B-pictures) that perform inter-frame prediction using temporally two reference images At this time, conventionally, a memory having a configuration as shown in FIG. 8 has been used. This memory has two memory areas for each frame. B1 in area 1
Write the top and bottom halves of the picture. After that, while displaying the B1 picture written in the area 1, the area 2 is displayed.
Write the upper half and the lower half of the B2 picture.

The conventional memory shown in FIG. 9 is also 2
It has the capacity for frames. In this case, the image data of the upper half of the B1 picture is written in the area 1. next,
In parallel with the operation of writing the image data of the lower half of the B1 picture in the area 1, reading is performed to display the field 1 of the B1 picture written in the area 1. Further, in parallel with the operation of reading the field 2 of the B1 picture, the image data of the upper half of the B2 picture is written in the area 2. In parallel with the operation of writing the image data of the lower half of the B2 picture in the area 2, the field 1 of the B2 picture is read.

Conventionally, frame interlace conversion has been performed using a memory having a capacity equivalent to 2 frames. (3) Memory as a buffer for adjusting the transmission rate of compressed data When NTSC signals are coded according to CCIR Recommendation 601 which is a standard of coding system for color television signals for broadcasting, 1
Horizontal 720 pixels × vertical 480 pixels are required for each frame. If the image format is 4: 2: 0, a luminance signal is 8 bits and a color signal is 4 bits per pixel. Therefore, 720 x 480 x per frame
A capacity of (8 + 4) = 3.95 (Mbit) is required.
When four frame memories are used, such as the above (1) reference image storage memory or (2) frame / interlace conversion buffer memory, 3.95 × 4 = 1
A capacity of 5.8 (Mbit) is required.

According to the ISO MPEG2 standard, 1.7 is used as a buffer memory for adjusting the transmission rate of compressed data.
A capacity of 5 (Mbit) or more is required. As a result, the memory capacity needs to exceed 16 (Mbit).

[0007]

As described above, in the conventional case where an image having a frame structure is interlaced and output, B
If two pictures continue, a memory having a capacity of 16 (Mbit) or more is required, and the cost cannot be reduced.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a moving picture decoding method and apparatus capable of reducing the required memory capacity and cost.

[0009]

A moving picture decoding apparatus of the present invention is a moving picture decoding apparatus which receives a code of a compressed frame structure and decodes the code to perform interlaced output. A code decoding circuit for outputting a decoding result, an image decoding circuit for decoding using the decoding result output from the code decoding circuit and outputting a decoding result, and an area having a capacity equivalent to a quarter frame are provided. A storage circuit which has six and which writes or reads the decoding result output from the image decoding circuit, and the decoding result which is divided into upper and lower parts for each field and is written in the different areas of the storage circuit. And a means for setting an address so that the next decoding result is written in the area where the decoding result is read out of this area and outputting it to the memory circuit. To have.

In another moving picture decoding apparatus of the present invention, the means for setting an address when writing or reading to the storage circuit and outputting to the storage circuit is the first one of the areas of the storage circuit. An address is set so that the area for writing the image data in the lower half of the field and the area for writing the image data in the upper half of the second field 2 are exchanged for each frame, and output to the storage circuit.

In still another moving picture decoding apparatus of the present invention, the means for setting an address when writing or reading to the storage circuit and outputting to the storage circuit is the first one of the areas of the storage circuit. The address is set so that the area for writing the decoding result of the upper half of the field and the area for writing the image data of the lower half of the second field 2 are exchanged for each frame, and output to the storage circuit.

Further, in another moving picture decoding apparatus of the present invention, the means for setting an address when writing or reading to the storage circuit and outputting to the storage circuit, among the areas of the storage circuit, The case where the area for writing the decoding result of the lower half of the first field and the area for writing the decoding result of the upper half of the second field 2 are exchanged for each frame, and the case of decoding the upper half of the first field One of the cases where the area for writing the encrypted result and the area for writing the decoded result of the lower half of the second field 2 are exchanged for each frame is selected to set the address and output to the storage circuit.

Here, when writing and reading the decoding result in the same area of the memory circuit,
Compare the address when writing and the address when reading,
The image decoding circuit may include means for stopping the decoding when the difference between the addresses becomes equal to or less than a predetermined value.

In the moving picture decoding method of the present invention, the above-mentioned decoding is applied to the code, the decoding result is output, the decoding result is used for the decoding, and the decoding result is output. A step of writing or reading the result in a memory circuit, wherein the memory circuit has six areas each having a capacity corresponding to a quarter frame, and the decoding result is divided into upper and lower parts for each field, A step of setting an address so as to write the next decoding result in the area where the decoding result is read out of the area of the memory circuit, and writing or reading to the memory circuit There is.

According to another moving picture decoding method of the present invention, in the step of writing or reading the decoding result in a memory circuit, the memory circuit has four areas each having a capacity corresponding to a quarter frame. The decoding result is divided into upper and lower parts for each field, and the first part of the area of the memory circuit is divided.
Of the field of writing the decoding result in the upper half of the field and the area of writing the decoding result in the lower half of the second field 2 are exchanged for each frame, and writing or reading is performed in the storage circuit. It is characterized by doing.

Further, in another moving picture decoding method of the present invention, in the step of writing or reading the decoding result in the memory circuit, the decoding result of the lower half of the first field in the area of the memory circuit is written. The address is set so that the area and the area for writing the decoding result of the upper half of the second field 2 are exchanged for each frame, and writing or reading is performed in the storage circuit.

Alternatively, in another moving picture decoding method of the present invention, in the step of writing or reading the decoding result in the memory circuit, the decoding result of the upper half of the first field in the area of the memory circuit is obtained. A case where the area to be written and the lower half decoding area of the second field 2 are exchanged for each frame, and an area where the upper half decoding result of the first field is written and the second field 2 One of the cases of exchanging the lower half of the decoding result for each frame is selected, an address is set, and writing or reading is performed in the storage circuit.

Here, in the step of writing or reading the decryption result to or from the storage circuit, when writing or reading the decryption result to or from the same area of the storage circuit, a writing operation is performed. The address may be compared with the address at the time of reading, and when the difference between the addresses becomes a predetermined value or less, the image decoding circuit may stop the decoding.

[0019]

When the decoding result is written in or read from the memory circuit, the decoding result is divided into upper and lower two fields for each field.
By dividing and writing each in a different area and setting the write address and the read address so that the next decryption result is written in the area where the decryption result is read, the capacity equivalent to 2 frames, which was conventionally required Can be reduced to 1.5 frames.

Alternatively, when writing or reading the decoding result to or from the memory circuit, the decoding result is divided into upper and lower parts for each field, and the lower half of the first field in the area of the memory circuit is decoded. The capacity of the memory circuit is set to 1 by setting the address so that the area for writing the encrypted result and the area for writing the decoded result of the upper half of the second field 2 are exchanged for each frame, and outputting to the memory circuit. The number of frames can be reduced.

Here, when writing or reading the decoding result to or from the memory circuit, when writing or reading the decoding result to or from the same region of the memory circuit, the address at the time of writing and the reading address By comparing with the address, and when the difference of this address becomes less than the predetermined value, the image decoding circuit stops the decoding, and the other decoding result is overwritten and destroyed before the written decoding result is read. Can be prevented.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a moving picture decoding apparatus according to the first embodiment of the present invention.

The storage circuit 8 has a capacity equivalent to 1.5 frames, as will be described later. The storage circuit 8 has a writing circuit and a reading circuit built therein, and performs writing or reading based on a control signal given from a CPU (not shown).

The code decoding circuit 1 receives the code 11 and decodes it, and outputs the decoding result 12 to the image decoding circuit 2 and the table rewriting control circuit 3.

The image decoding circuit 2 reads the reference image 14 required for decoding from the storage circuit 8 as needed. Then, the image is decoded based on the decoding result 12 output from the code decoding circuit 1, and the decoding result 15 is written in the storage circuit 8.

The memory address management table 4 is stored in the storage circuit 8
Manages as a table the information necessary for calculating the memory address when writing or reading. This table needs to be rewritten every time the image in the memory address management table 4 changes, and the table rewriting control circuit 3 rewrites it based on the decoding result 12 output from the code decoding circuit 1 in a procedure described later.

The memory address calculation circuit 5 uses the information stored in the memory address management table 4 to calculate the memory address 16 for reading or writing, and outputs it to the storage circuit 8.

Further, the memory address calculation circuit 5 outputs the memory address 16 to the memory address comparison circuit 6. The memory address comparison circuit 6 compares the memory address at the time of writing with the memory address at the time of reading for displaying, and the comparison result 1
8 is output to the decoding stop signal generation circuit 7.

The decoding stop signal generating circuit 7 compares the comparison result 1
When the difference between the memory address 17 for writing and the memory address 17 for reading is reduced to a predetermined value, the decoding stop signal 19 is output to the image decoding circuit 2. The image decoding circuit 2 stops the decoding when it receives the decoding stop signal 19. This prevents the unread image data from being destroyed by overwriting, which will be described in detail later.

FIG. 2 shows the structure of the memory area of the memory circuit 8. As described above, the memory circuit 8 has a capacity equivalent to 1.5 frames, and has the areas 1 to 6 divided into six as shown in the drawing. Each of the areas 1 to 6 has a capacity equivalent to 1/4 frame.

In a frame-structured image, decoding is performed in order from top to bottom in the form in which the pixels of field 1 and field 2 are mixed every other row. Therefore, the decoding result 15 output from the image decoding circuit 2 is also in the field 1
And the pixels of the field 2 are written in the memory circuit 8 in a mixed form every other row. Next, when interlaced output is performed and displayed on the screen, first, the upper half to the lower half of the field 1 are sequentially displayed, and then the upper half to the lower half of the field 2 are sequentially displayed.

First, as shown in FIG. 2, the first sheet B
Pixel data for the upper half of field 1 of picture B1 is written in region 1, and pixel data for the upper half of field 2 of B picture B1 is written in region 2. In this way, data is written separately in different areas depending on the field.

Next, the pixel data of the lower half of the field 1 of the B picture B1 is written in the area 3, and the B picture B1
The pixel data of the lower half of the field 2 of is written in the area 4.

At the next stage, the pixel data of the upper half of field 1 of B picture B1 written in area 1 and the pixel data of the lower half of field 1 of B picture B1 written in area 3 are displayed. Be seen. In parallel with this display, the upper half of field 1 of B picture B2 is written in area 5, and the upper half of field 2 of B picture B2 is written in area 6.

The pixel data of the upper half of the field 1 of the B picture B1 in the region 1 whose display has been completed and the pixel data of the lower half of the field 1 of the B picture B1 in the region 3 are not used as reference images thereafter. , Other data may be overwritten. Therefore, the pixel data of the lower half of field 1 of B picture B2 is written in region 1, and the pixel data of the lower half of field 2 of B picture B2 is written in region 3.

Display of the pixel data of the upper half of the field 2 of the B picture B1 written in the area 2 in parallel with or after the writing, and
The pixel data of the lower half of the field 2 of the B picture B1 written in the area 4 is displayed. The pixel data of the areas 2 and 4 whose display has been completed may be overwritten. Therefore, the pixel data of the upper half of the next B picture B3 is written in this empty area.

As described above, in this embodiment, there are two B pictures.
When the number of frames is continuous, one frame of the first B picture and 0.5 frame of the second B picture are written. Then, 0.5 of the remaining second B picture
The writing of the pixel data for the frame is performed in the empty area where the pixel data of the field 1 of the first B picture is read. As a result, the capacity of 2 frames, which is conventionally required, can be reduced to the capacity of 1.5 frames.

Next, the procedure for the table rewrite control circuit 3 to rewrite the information stored in the memory address management table 4 will be described with reference to FIG.

First, if the previous image is not a B picture, the memory address management table is initialized. When the previous image is a B picture, the writing or reading area is changed as indicated by the arrow in FIG. (1) The memory read area when displaying the current image data is the same as the area where the previous image data was written. (2) The area for writing data in the upper half of field 1 of the current image is the area where the display of the upper half of field 2 of the previous image has ended. (3) The area where the image data of the lower half of field 1 of the current image is written is the same as the area where the data of the upper half of field 1 of the previous image is displayed.

As described above, as long as the B picture continues, the pixel data of the upper half or the lower half of the next B picture is written in the area where the pixel data is read out for display. As a result, the capacity of the memory is reduced as compared with the conventional case.

Further, conventionally, as shown in FIG. 8 or FIG. 10, the area where the pixel data is read out for display is
Every other line. Therefore, when other data is overwritten on the area of every other row, complicated control is required.

On the other hand, in this embodiment, the field 1 pixel data and the field 2 pixel data are written in separate regions. Therefore, the area in which the pixel data has been read out for display is continuous in units of ¼ frame. Therefore, the management of the memory address is easy.

As described above, according to this embodiment, it is possible to use a memory having a smaller capacity than before, and it is easy to manage the memory address, which contributes to cost reduction.

Next, a second embodiment of the present invention will be described. The configuration of the moving picture decoding apparatus according to this embodiment is shown in FIG.

The memory circuit 35 in this embodiment may have a capacity of one frame. A writing circuit and a reading circuit are built in the memory circuit 35, and a writing or reading operation is performed by receiving a control signal from a CPU (not shown).

The code decoding circuit 31 receives the code 41 and decodes it, and outputs the decoding result 43 to the image decoding circuit 34 and the memory address calculation circuit 32.

The image decoding circuit 34 reads a reference image required for decoding from the storage circuit 35 as needed, decodes the image based on the decoding result 43 output from the code decoding circuit 31, and outputs the decoding result. Write to the memory circuit 35.

The memory address calculation circuit 32 calculates the memory address required when the image decoding circuit 34 reads or writes. The memory address calculation circuit 32 calculates the memory address using the decoding result 43 provided from the code decoding circuit 31, and outputs it to the memory address exchange control circuit 33.

The memory address exchange control circuit 33 exchanges the area for writing the image data of the lower half of the field 1 and the image data of the upper half of the field 2 for each frame according to the frame synchronization signal 42 input from the outside. Is to do. The memory address exchange control circuit 33 controls the memory address output from the memory address calculation circuit 32 to exchange the area to be written for each frame,
The actual memory address is output to the storage circuit 35.

The memory circuit 35 performs writing according to the memory address given by the memory address exchange control circuit 33. Then, the storage circuit 35 reads the image data according to the memory address calculated by the memory address calculation circuit 32, and outputs it as an output signal 47 to the outside.

A specific circuit configuration of the memory address exchange control circuit 33 is shown in FIG. The comparator 101 compares the memory address 44 output from the memory address calculation circuit 32 with the data 122 indicating half the size of the field, and determines whether the memory address 44 is in the upper half of the field, or An up / down selection signal 124 indicating whether it is the lower half is output.

The upper / lower selection signal 124 and the field selection signal 121 are input to the exclusive OR gate 106, and when the two do not match, specifically, when the memory address is in the lower half of the field 1, or in the field 2. The signal 129 of logic "1" is output only in the upper half.

The signal 128 output from the flip-flop 108 is the inverter 109 and the changeover switch 1
Frame synchronization signal 1 input from the outside by 10
Each time 25 is input, the logic level switches from “1” to “0” or from “0” to “1”. As a result, the flip-flop 108 becomes the frame synchronization signal 125.
The signal 128 of logic "1" or "0" is alternately output in synchronism with.

The AND gate 107 is provided with the signal 128 output from the flip-flop 108 and the signal 129 output from the exclusive OR gate 106, and outputs the logic "1" only when both are the logic "1". The signal 130 is output.

The signal 130 output from the AND gate 107 is input to the changeover switches 104 and 105, respectively. The changeover switch 104 uses the signal 13
When 0 is at the logic "0" level, the up / down selection signal 124 is selected from the up / down selection signals 124 and 126 and output to the outside. When the signal 130 is at the logic "1" level, the up / down selection signal 126 is selected and output to the outside. Output to.

The change-over switch 105 selects the field selection signal 121 from the field selection signals 121 and 127 when the signal 130 is at the logic "0" level and outputs it to the outside. When the signal 130 is at the logic "1" level, the changeover switch 105 outputs the field. The selection signal 127 is selected and output to the outside.

With this memory address exchange control circuit 33,
Only when the memory address is the lower half of field 1 or the upper half of field 2, the inverted vertical selection signal 126 and field selection signal 127 are output, and the memory address is the upper half of field 1 for each frame time. Or the up / down selection signal 1 which is not inverted in the lower half of the field 2
24 and the field selection signal 121 are output.

When the up / down selection signal and the field selection signal are inverted, if the lower half of the field 1 before the inversion,
After inversion, it will be the upper half of field 2. If it was the lower half of field 1 before flipping, then field 2 after flipping
It becomes the upper half. In this way, the memory address is set so that the area for writing the image data in the lower half of the field 1 and the area for writing the image data in the upper half of the field 2 are exchanged for each frame.

Here, 2 of the signals indicating the memory address
By using the field selection signal and the up / down selection signal for one bit, it is possible to write the image signal in the four areas obtained by vertically dividing the decoding result into two fields.

Next, FIG. 6 shows the storage device 3 in this embodiment.
5 shows a configuration of a memory area included in 5 and an area for writing or reading an image signal. The frame / interlace conversion buffer in the storage device 35 has four independent areas 1, 2, 3 and 4 in units of 1/4 frame.

In an image having a frame structure, the decoding is sequentially performed from the top to the bottom in the form in which the pixels of the field 1 and the pixels of the field 2 are mixed every other row. The upper half of the field 1 and the upper half of the field 2 are written into the memory circuit 35 almost at the same time. Next, the lower half of field 1 and the lower half of field 2 are written almost simultaneously.

The display at the time of interlaced output is
Field 1 goes from top to bottom, then field 2 goes from top to bottom. That is, the upper half of field 1, the lower half of field 1, field 2
The image signals are read out in the order of the upper half and the lower half of field 2.

More specifically, referring to FIG. 6, the upper half of the field 1 and the upper half of the field 2 of the first B picture B1 are written as hatched. Here, the upper half of field 1 is written in area 1 and the upper half of field 2 is written in area 2 by the memory address exchange control circuit 33.

Next, the lower half of field 1 of B1 is written in area 3 and the lower half of field 2 is written in area 4.

Next, in order to display the image signals of the upper half and the lower half of field 1 of B1, reading is performed respectively. The lower half of the field 1 is read in parallel with the writing, but if the writing precedes the reading, the display can be performed without any trouble. The time for reading the lower half of field 1 is later than the time for reading the upper half of field 1. Therefore, the reading of the lower half of the field 1 is started after the writing of the lower half of the field 1 is advanced to some extent,
It is easy to control that writing precedes reading.

At the next stage of writing and reading the second picture B2, the area for writing the lower half of field 1 and the area for writing the upper half of field 2 are exchanged. This is achieved by inputting the frame synchronization signal 125 to the memory address exchange control circuit 33 and switching the logical levels of the up / down selection signal and the field selection signal and outputting them as described above. As a result, B2
The lower half of field 1 of B2 is written to area 2, and the upper half of field 2 of B2 is written to area 3.

First, the upper half of field 1 of B2 is written in area 1 and the upper half of field 2 is written in area 3. Here, since the image data written in the areas 1 and 3 are after the display of the field 1 of B1 is completed, there is no problem even if they are destroyed by overwriting.
If the writing area is not switched by the memory address exchange control circuit 33, the upper half of the field 2 of B2 is written in the area 2, and the upper half of the field 2 of B1 which has not been read at this stage. The image data will be destroyed and the display will not be performed correctly.

In parallel with this writing operation, in order to display the field 2 of B1, the image data of the upper half and the lower half of the field 2 are read.

Next, the lower half of field 1 and the lower half of field 2 of B2 are written. In this case also, the memory address exchange control circuit 33 causes the field 1
The lower half of field 2 is in area 2, the lower half of field 2 is area 4
Will be written in. Since the display of the image data written in the areas 2 and 4 has already been completed, there is no problem even if it is destroyed by overwriting.

Here, in the area 2, the image data is read in parallel with the writing of the lower half of the field 1 of B2. In this case as well, it is necessary to control so that writing precedes reading.

At the next stage, the frame synchronization signal is input to the memory address exchange control circuit 33 again, and the lower half of field 1 of the third picture B3 and the area for writing the upper half of field 2 are exchanged. That is, the lower half of field 1 of B3 is written in area 3, and the upper half of field 2 is written in area 2. Since the image data of the upper half and lower half of the field 1 of B2 written in the areas 1 and 2 have been read out, there is no problem even if they are overwritten. Such an operation is similarly performed for the third, fourth, ... Pictures.

As described above, the memory circuit 35 is used in this embodiment.
Even if the frame / interlace conversion buffer has a capacity of one frame, writing and reading can be performed without any trouble.

FIG. 7 shows another usage of the areas 1 to 4 of the memory circuit 35 in the moving picture decoding apparatus according to the third embodiment of the present invention. In the second embodiment, a picture Bi (i
Is always an integer, the reading for display is always performed from the field 1 and then to the field 2. On the other hand, the third embodiment corresponds to the case where the field 2 is displayed first.

In this embodiment, the configuration of the memory address exchange control circuit is different from that of the second embodiment shown in FIG. 5, and the output terminal of the exclusive OR gate 106 and the AND gate 10
Both ends of the inverter are connected to the input terminal 7 of the inverter 7. The memory address exchange control circuit according to the present embodiment outputs the selected field so that the area for writing the upper half of field 1 and the area for writing the lower half of field 2 are switched every time the frame synchronization signal 125 is input. The logic level of the signal and the up / down selection signal is switched.

Specifically, as shown in FIG. 7, B1
The upper half of field 1 is written in area 1 and the upper half of field 2 is written in area 2.

The lower half of field 1 of B1 is written in area 3 and the lower half of field 2 is written in area 4. In parallel with this, the upper half of field 2 of B1 and the lower half of field 2 of B1 are read. In area 4, B1
It is necessary to control so that the write operation of the lower half of the field 2 of 1 is performed before the read operation.

In the next stage, the upper half of field 1 is replaced with area 4, and the lower half of field 2 is replaced with area 1.

The upper half of field 2 of B2 is in area 2,
The upper half of field 1 is written in area 4, and in parallel, the upper half of field 1 of B1 written in area 1 and the lower half of field 1 of B1 written in area 3 are read out to display. Done.

The lower half of field 2 of B2 is written in area 1 and the lower half of field 1 is written in area 3, and the lower half of field 2 of areas 1 to B2 is read in parallel and the lower half of area 2 to B2 is read. The upper half of field 2 is read.

As described above, in the present embodiment, the field 1 is read after the field 2 of the picture Bi, but there is a problem that the image data before the end of display is destroyed as in the second embodiment. Works without.

As described above, the display is performed from the field 1 in the second embodiment, and the field 2 is performed in the third embodiment.
Display from.

Further, there are cases where the field 1 is displayed first and the field 2 is displayed first. For example, one frame may consist of three fields, as when a movie is broadcast on television. In such a case, after the Bi-th picture Bi, the field 1 of the Bi, the field 2 of the Bi, and the field 1 of the Bi are displayed again in this order, the next Bi + 1-th picture B is displayed.
i + 1 field 2, Bi + 1 field 1, further Bi + 2nd picture Bi + 2 field 2, Bi + 2 field 1, and so on.

In such a case, the memory address exchange control circuit may be constructed as follows. That is, in the circuit of FIG. 5, the output terminal of the exclusive OR gate 106 and the AND
An inverter and a changeover switch are connected in series between the gate 107 and the input terminal. The changeover switch is the changeover switching 10 shown in the drawing.
4 and 105, the output signal 130 from the AND gate 107 operates to switch the output. As a result, the memory address exchange control circuit in this case operates so that the output signal 129 of the exclusive OR 106 and the inverted signal of this output signal 129 are selected by the changeover switch.

The above-mentioned embodiments are all examples and do not limit the present invention. For example, in the first embodiment, the address when writing or reading is performed in the memory circuit is obtained by the table rewrite control circuit 3, the memory address management table 4, and the memory address calculation circuit 5 in the embodiment. However, the configuration is not necessarily limited to this.
The pixel data for 0.5 frames of the second B picture and the second B picture are written in different areas,
The pixel data for 0.5 frames of the remaining second B picture is written in the field 1 of the first B picture.
It is sufficient that the address is set so that the pixel data is read out and the pixel data is stored in an empty area.

[0086]

As described above, according to the present invention, when the decoding result is written or read in the memory circuit, the decoding result is divided into upper and lower parts for each field, and each is divided into different areas. By setting the writing address and the reading address so that the next decoding result is written in the area where the writing and decoding result is read, the capacity of 2 frames, which is conventionally required, is 1.5 frames. Therefore, the cost can be reduced.

Alternatively, according to another aspect of the present invention, when writing or reading the decoding result to or from the memory circuit, an area for writing the decoding result in the upper half of the first field and a lower half of the second field are used. By setting the address so that the area for writing the decoding result of 1 is exchanged for each frame, the capacity corresponding to one frame is sufficient, so that the cost can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a moving picture decoding apparatus according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an area of a memory and a use procedure in the video decoding device.

FIG. 3 is an explanatory diagram showing a procedure for rewriting a memory management table in the video decoding device.

FIG. 4 is a block diagram showing a configuration of a moving picture decoding apparatus according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a memory address exchange control circuit in the video decoding device.

FIG. 6 is an explanatory diagram showing an area of a memory and a use procedure in the moving picture decoding apparatus.

FIG. 7 is an explanatory diagram showing an area of a memory and a use procedure in a moving picture decoding apparatus according to a third embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a region of a memory and a use procedure in a conventional video decoding device.

FIG. 9 is an explanatory diagram showing an area and a use procedure of a memory in another conventional moving picture decoding apparatus.

[Explanation of symbols]

 1 Code Decoding Circuit 2 Image Decoding Circuit 3 Table Rewriting Control Circuit 4 Memory Address Management Table 5 Memory Address Calculation Circuit 6 Memory Address Comparison Circuit 7 Decoding Stop Signal Generation Circuit 8 Storage Circuit 11, 41 Code 12, 43 Decoding Result 14 See Image 15 Decoding result 16,44,45 Memory address 18 Comparison result 19 Decoding stop signal 20 Pixel data 31 Code decoding circuit 32 Memory address calculation circuit 33 Memory address exchange control circuit 34 Image decoding circuit 35 Memory 101 Comparator 102, 103,109 inverter 106 EX-OR gate 107 AND gate 110 flip-flop

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 7/13 Z

Claims (10)

[Claims] 1. A moving picture decoding apparatus which receives a code having a compressed frame structure, decodes the code, and outputs an interlace, and a code decoding circuit which receives the code, decodes the code, and outputs a decoding result, An image decoding circuit that performs decoding using the decoding result output from the code decoding circuit and outputs the decoding result, and six image storage areas each having a capacity corresponding to a quarter frame, and the image decoding circuit A memory circuit for writing or reading the decryption result output from the memory; and a memory circuit that divides the decryption result into upper and lower parts for each field and writes the areas in different regions of the memory circuit. A moving picture decoding apparatus, comprising: means for setting an address so as to write the next decoding result in the area where the decoding result is read and outputting it to the storage circuit. 2. A moving picture decoding apparatus which receives a code having a compressed frame structure, decodes the code, and outputs an interlace, and a code decoding circuit which receives and decodes the code and outputs a decoding result. An image decoding circuit which performs decoding using the decoding result output from the code decoding circuit and outputs the decoding result, and four image storage circuits each having a region having a capacity corresponding to a quarter frame, And a storage circuit for writing or reading the decoding result output from the above, and the decoding result is divided into upper and lower parts for each field and written into the different areas of the storage circuit. An address is set so that the area for writing the decoding result in the lower half of the first field and the area for writing the decoding result in the upper half of the second field 2 are exchanged for each frame. And a means for outputting to the storage circuit. 3. A moving picture decoding apparatus which receives a code having a compressed frame structure, decodes the code, and outputs an interlace, and a code decoding circuit which receives the code, decodes the code, and outputs a decoding result. An image decoding circuit which performs decoding using the decoding result output from the code decoding circuit and outputs the decoding result, and four image storage circuits each having a region having a capacity corresponding to a quarter frame, And a storage circuit for writing or reading the decoding result output from the above, and the decoding result is divided into upper and lower parts for each field and written into the different areas of the storage circuit. Addresses are set so that the upper half area of the first field for writing the decoding result and the lower half area of the second field 2 for writing the decoding result are exchanged for each frame. And a means for outputting to the storage circuit. 4. A moving picture decoding apparatus which receives a code of a compressed frame structure, decodes the code, and outputs an interlace, and a code decoding circuit which receives the code, decodes the code, and outputs a decoding result. An image decoding circuit which performs decoding using the decoding result output from the code decoding circuit and outputs the decoding result, and four image storage circuits each having a region having a capacity corresponding to a quarter frame, And a storage circuit for writing or reading the decoding result output from the above, and the decoding result is divided into upper and lower parts for each field and written into the different areas of the storage circuit. A case where the area for writing the decoding result in the lower half of the first field and an area for writing the decoding result in the upper half of the second field 2 are exchanged for each frame; Field for writing the decoding result in the upper half of the field and the area for writing the image data in the lower half of the second field 2 are exchanged for each frame, an address is set, and the storage is performed. And a means for outputting to a circuit. 5. When writing and reading the decoding result in the same area of the memory circuit, an address at the time of writing and an address at the time of reading are compared, and when the difference between the addresses becomes equal to or less than a predetermined value. 5. The moving picture decoding apparatus according to claim 1, further comprising means for stopping the decoding in the image decoding circuit. 6. A moving picture decoding method, wherein a code of a compressed frame structure is given and decoded, and interlaced output is performed, and a step of giving the code and decoding and outputting a decoding result, the decoding result. And the step of writing and reading the decoding result in a memory circuit, wherein the memory circuit has six areas each having a capacity corresponding to a quarter frame. Then, the decoding result is divided into upper and lower parts for each field, and an address is set so that the next decoding result is written in the area of the storage circuit where the decoding result is read. And a step of writing to or reading from the storage circuit. 7. A moving picture decoding method, wherein a code of a compressed frame structure is given and decoded, and interlaced output is performed. In the method of decoding, the code is given and decoded, and a decoding result is output. And the step of writing and reading the decoding result in a memory circuit, wherein the memory circuit has four areas each having a capacity corresponding to a quarter frame. Then, the decoding result is divided into upper and lower parts for each field, and the upper half of the first field in the area of the storage circuit and the lower half of the second field 2 are written in the upper half of the first field. A step of setting an address so that an area for writing image data is exchanged for each frame and writing or reading the address in the memory circuit. Method of. 8. A moving picture decoding method, wherein a code of a compressed frame structure is given and decoded, and interlaced output is performed. In the moving picture decoding method, the step of giving the code and decoding and outputting the decoding result, the decoding result. And the step of writing and reading the decoding result in a memory circuit, wherein the memory circuit has four areas each having a capacity corresponding to a quarter frame. Then, the decoding result is divided into upper and lower parts for each field, and the lower half of the first field in the area of the memory circuit and the upper half of the second field 2 into which the decoding result is written. A step of setting an address so that the area for writing the decoding result is exchanged for each frame and writing or reading the address in the memory circuit. Decoding method. 9. A moving picture decoding method, wherein a code of a compressed frame structure is given and decoded, and interlaced output is performed, and a step of giving the code and decoding and outputting a decoding result, the decoding result. And the step of writing and reading the decoding result in a memory circuit, wherein the memory circuit has four areas each having a capacity corresponding to a quarter frame. Then, the decoding result is divided into upper and lower parts for each field, and the upper half of the first field in the area of the storage circuit and the lower half of the second field 2 are written in the upper half of the first field. When the image data write area is exchanged for each frame, the upper half of the first field where the decoding result is written and the lower half of the second field 2 where Video decoding method characterized by comprising the steps of writing or reading in the storage circuit to set an address by selecting one of a case of exchanging the area for writing the image data for each frame. 10. When writing or reading the decryption result to or from the same area of the storage circuit in the step of writing or reading the decryption result to or from the storage circuit, the address at the time of writing 10. The video decoding according to claim 6, wherein the image decoding circuit stops the decoding when the difference between the addresses is equal to or less than a predetermined value. Method.