JPH07183297A - Wiring forming method - Google Patents

Abstract

PURPOSE:To prevent formation of a nodule and growth of hillock in a wiring film when an antireflection film required for heating a wafer to form a film is formed on the wiring film. CONSTITUTION:An Al-0.5%Cu film 9 in which Cu is added as adding element of non-nodule formability is formed over a contact hole 4 filled with W plug 8p, and an SiON antireflection film is further formed at 360 deg.C. At the time of forming the Al-0.5%Cu film by sputtering, the degree of vacuum of a chamber before Ar gas is introduced is set to the order of 10<-8>Pa or higher, and residual moisture in the film is reduced. Thus, the element Cu does not generate nodule even under heating condition different from Si which has been heretofore generally added, and hence a contact malfunction, an electromigration are prevented. The stress of the crystalline lattice is reduced due to a decrease in the residual moisture, and no hillock occurs even in cooling.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method applied to, for example, a semiconductor device manufacturing process, and particularly to a wiring on a lower layer side when forming an antireflection film which requires a predetermined wafer heating in a film forming process. The present invention relates to a method for suppressing the growth of additive element nodules and the formation of hillocks in a film.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor devices has accelerated, the minimum processing size thereof has been rapidly reduced. For example, it is currently being transferred to mass production line 1
The minimum processing size of 6MDRAM is about 0.5 μm,
The next-generation 64M DRAM is expected to be reduced to 0.35 μm or less, and the next-generation 256M DRAM is expected to be reduced to 0.25 μm or less. In the 0.35 μm to 0.25 μm (deep submicron) class fine processing, a far-ultraviolet light source such as KrF excimer laser light (wavelength 248 nm) is required as a light source for photolithography.

However, when an extremely high monochromatic light source such as an excimer laser beam is used, it is known that the standing wave effect becomes more remarkable than in the conventional g-line exposure or i-line exposure. ing. The standing wave effect is caused by interference between the multiple reflected lights in the resist film, or interference caused by addition of the reflected light from the surface of the resist film.
As a result, a light intensity distribution is generated in the film thickness direction of the resist film, or the absorbed light amount changes depending on the resist film thickness,
That is, a substantial change in sensitivity occurs. These cause, for example, the formation of wavy unevenness on the side wall surface of the resist pattern after development and the variation of the pattern size above and below the surface step of the wafer. 0.35 μm design
Under the rule, it is necessary to suppress this dimensional fluctuation within ± 5%, and for this purpose, it is required to suppress fluctuation of the absorbed light amount within the resist film within approximately ± 3%.

In order to satisfy this requirement, it is necessary to suppress the reflection of the resist film by the underlying material film and reduce the multiple reflected light in the resist film. From such a background, it is considered that the use of the antireflection film is almost indispensable in the fine processing after the excimer laser lithography. The antireflection film exhibits the best effect of suppressing standing waves when it is interposed between the base material film and the resist film, and at the same time, it also exhibits the effect of preventing halation.

Amorphous silicon, TiN, TiON, etc. have been widely used as the constituent material of the antireflection film, but in recent years, silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). At least one type of SiON (silicon oxynitride) -based material selected from
(Where n is the real part of the complex amplitude reflectance R and k is also the imaginary part coefficient), and is expected to be applied to excimer laser lithography. Particularly, SiON is, for example, SPIE Vol. 1927, Optical / Laser Microlithography VI (SPIE Vol.
1927, Optical / Laser Microlithography VI), (199
3) p. As reported in Nos. 263 to 274, it is possible to change the optical constants n and k in a wide range by changing the conditions at the time of film formation by plasma CVD, and it is possible to change the optical constants n and k depending on the type of the base material film. This has the advantage that the degree of freedom in setting antireflection conditions is great.

[0006]

By the way, a base material film having a high reflectance which requires an antireflection film in photolithography is, for example, a wiring film in the case of a semiconductor device. The material most widely used as a constituent material of this wiring film is an Al-based material, and typically, pure Al is added to S for the purpose of preventing the generation of Al spikes on the Si substrate.
An Al-1% Si alloy added with i, or an Al-1% Si-0.5% Cu alloy further added with Cu for the purpose of improving electromigration resistance.

Here, with respect to the Al-based wiring film containing Si, Si is deposited during the film formation by high temperature sputtering or in the heat treatment process after the film formation, and the reliability of the wiring is deteriorated by the generated Si nodules. There are known cases of doing this. The above S that is usually performed near 360 ° C
The step of forming the iON-based antireflection film may bring about the same effect as the heat treatment after the film formation. Hereinafter, the problems caused by the Si nodules will be described with reference to FIGS.
Description will be made with reference to FIGS. 1 to 13 and FIGS. 14 to 16.

For example, as shown in FIG.
_In a wafer in which an Al-1% Si film 22 is laminated on the _x interlayer insulating film 21, a SiON antireflection film 23 as shown in FIG. 9 is further formed on the Al-1% Si film 22 at 360 ° C., for example. When the film is formed, the Si nodules 24 may grow in the Al-1% Si film 22. This A
The 1-1% Si film 22 is patterned through a resist mask 25 as shown in FIG. 10 in the next step. The Al-based wiring pattern 22a formed at this time is formed.
If the Si nodules 24 are included in the above, the wiring width will be substantially reduced, and a local temperature rise due to energization will occur, resulting in deterioration of electromigration resistance. Furthermore, when the nodule diameter reaches 0.5 μm under the 0.35 μm rule, electrical connection by this Al-based wiring pattern 22a becomes impossible.

Alternatively, when the SiON antireflection film 23 is formed, the deposition of Si is caused by the SiO _x interlayer insulating film 21 and Al-1%.
When the Si nodule layer 26 as shown in FIG. 11 is formed over the entire interface with the Si film 22, the following problems occur during dry etching of the Al-1% Si film 22. That is, as shown in FIG. 12, the etching of the Al-1% Si film 22 using a normal chlorine-based gas is almost completed, and Si is entirely formed on the surface to be etched.
When the nodule layer 26 is exposed, excess Cl ^* at the time of over-etching attacks the lower portion of the side wall surface of the Al-based wiring pattern 22a. As a result, the notch 27 as shown in FIG. 13 is likely to occur.

Further, if Si nodules are formed at the opening positions of the via holes, contact failure will occur. That is, as shown in FIG. 14, Al-1% S
In a wafer in which the SiO _x interlayer insulating film 32 is laminated on the i film 31, a SiON antireflection film 33 as shown in FIG. 15 is further formed on the SiO _x interlayer insulating film 32 at, for example, 360 ° C. The Si nodules 34 may grow in the Al-1% Si film 31. This Si
The O _x interlayer insulating film 32 is dry-etched through the resist mask 35 as shown in FIG. 16 in the next step. When the Si nodule 34 is exposed at the bottom of the via hole 36 formed at this time, Contact resistance increases significantly. Further, since the SiO _x film is usually etched using a fluorine-based gas, accelerated etching of the Si nodules 34 by F ^* proceeds during overetching, and large voids 37 are formed in the Al-1% Si film 31. It is also a concern. This also causes a contact failure.

The formation of such Si nodules is Al-1%
A Ti film is provided as the base of the Si film, and an Al-1% Si film
What can be prevented by setting the film formation temperature to around 500 ° C
But, for example, Monthly Semiconductor World 1992
July issue p. 36-41 (published by Press Journal)
Has been. For example, as shown in FIG.
_xA Ti film 28 is previously formed on the interlayer insulating film 21,
Then, as shown in FIG.
Then, an Al-1% Si film 22 is formed. At this time, Ti
The film 28 reacts with Al to first form an Al-Ti alloy,
Al-Si-Ti ternary alloy film with Si taken in here
Change to 29. This is the mechanism for preventing nodules
Is.

However, as another problem, the Al-based wiring film has a problem that hillocks are formed when it is heated to 400 ° C. or higher in the film formation process or the heat treatment process after the film formation. The Al-1% Si film 22 described above also has a Si
When the ON antireflection film 23 is formed, hillocks 30 may occur as shown in FIG. This hillock 3
The height of 0 may reach up to around 0.5 μm, and the height of 0.
Under the 35 μm rule, it may hinder the flattening by the insulating film or cause a short circuit between wirings.

As a preventive measure against hillock 30, Al-1%
The Si film 22 is previously coated with a hillock prevention film such as TiN,
A method of mechanically suppressing the stress in the film can be considered, but there is a high possibility that problems such as an increase in the number of steps, an increase in cost due to this, and a deterioration in etching processability due to a complicated wiring structure may occur.

As described above, the antireflection film is expected to be indispensable in the future, but in order to put it into practical use, it is essential to take measures to prevent the formation of nodules and hillocks in the underlying wiring film. Therefore, an object of the present invention is to provide a wiring forming method capable of effectively preventing nodule formation and hillock formation without increasing the number of steps.

[0015]

The wiring forming method of the present invention is proposed to achieve the above object,
An antireflection film mainly composed of at least one silicon compound selected from silicon oxide, silicon nitride, and silicon oxynitride on a wiring film made of a pure metal material or a metal material containing a non-nodule-forming additive element Is formed.

The above silicon compounds are generally atmospheric pressure CVD.
Method, LPCVD method, plasma CVD method or the like. Therefore, its composition is not necessarily SiO.
₂ or Si ₃ N ₄ etc. need not be stoichiometric,
Further, it may contain a slight amount of hydrogen or water depending on the composition of the source gas at the time of film formation and the film forming conditions.

Here, the additive element is preferably an element that lowers the melting point of the pure metal material. This leads to improvement in reflowability when high-temperature sputtering is assumed as a method for forming the wiring film,
It works as an advantageous condition. The pure metal material may be Al, which is the most commonly used wiring material in the past, and in this case, Ti, Li, Cu, Ga, Ge, as a non-nodule forming additive element, At least one of Au can be used.

Alternatively, at least one selected from Cu, Ag, Au, W, and Mo may be used as the constituent material of the wiring film, instead of the Al-based material as described above. A Ti-based material layer may be laminated immediately above and / or immediately below these wiring films. Ti formed directly under the wiring film
As the system material film, a Ti film, a TiN film, a TiON film, a TiW film or the like which has been conventionally used for a barrier metal, an adhesion layer, an ohmic contact film or the like can be used. Of course, these films may be used not as a single-layer film but as a multi-layer film for obtaining barrier properties, adhesion, and ohmic properties in a composite manner. The concept of the Ti-based material film formed directly on the wiring film is basically the same.

Since the TiN film and the TiON film also function as an antireflection film when formed directly on the wiring film, the function of the main antireflection film of the silicon compound formed in the present invention is multiple. It is particularly desirable to optimize the optical constants and film thickness of each film so as not to be hindered by the interference effect.

Further, it is also effective to improve the film quality of the wiring film which is the base of the antireflection film. This is because the inside of the sputtering chamber is preliminarily set to 10 when the wiring film is formed.
This can be achieved by evacuating to a vacuum level of ^-8 Pa or higher and then introducing an inert gas into the chamber to sputter the target. In particular, when the wiring film is an Al-based wiring film, it can be an effective hillock prevention measure. When the degree of vacuum is 10 ⁻⁷ Pa or less, water (H ₂ O) mainly remaining in the sputtering chamber
There is a great possibility that a sufficient effect cannot be obtained due to the influence of.

[0021]

When silicon oxide, silicon nitride, or silicon oxynitride is used to form a film with excellent film quality as an antireflection film, the substrate must be heated during film formation. In the present invention, an antireflection film made of these silicon compounds is formed on the wiring film, but since the wiring film is made of a pure metal material or a metal material to which a non-nodule forming additive element is added, Nodules are not formed in the wiring film even during the formation of the antireflection film. Therefore, it is possible to prevent contact failure, generation of voids or notches in the wiring pattern, and the like.

Here, if the melting point of the wiring film is increased by using a pure metal material as compared with the conventional case, there is a possibility that the filling characteristics of the fine connection holes and the step coverage may be deteriorated particularly during the sputtering film formation. This means, for example, that pure Al is used instead of the conventional Al-1% Si alloy (melting point: about 580 ° C).
There is actually a problem when using 1 (melting point: 660 ° C.). However, this problem is solved by using an element that lowers the melting point of the pure metal material as an additional element. For example, if the pure metal material is Al, T as an additive element
By using at least one of i, Li, Ga, Ge, and Au, it is possible to prevent the formation of nodules and the melting point increase without impairing the film forming characteristics in high temperature sputtering.

Alternatively, as the pure metal material, Cu,
When at least one selected from Ag, Au, W, and Mo is used, at least the conventional problems associated with the physical properties of Al can be basically avoided. In the present invention, by laminating the Ti-based material film immediately above and / or immediately below the wiring film, it is possible to avoid the deterioration of the barrier property, the adhesion, and the ohmic property due to the use of the above-mentioned new wiring material. Is.

Further, by carrying out the sputtering film formation of the wiring film in a sputtering chamber which has been evacuated to a vacuum degree higher than 10 ^-8 Pa in advance, it is possible to mainly prevent the incorporation of residual water into the wiring film. it can. As a result, the lattice mismatch of the wiring film and the accumulation of stress in the crystal lattice due to the lattice mismatch are prevented. Particularly in the case of an Al-based wiring film, the reduction of this stress can prevent the formation of hillocks, which is considered to be a stress relaxation mode.

[0025]

EXAMPLES Specific examples of the present invention will be described below.

Example 1 This example is an example in which an Al-0.5% Cu film is formed as an upper layer wiring on a contact hole filled with a W plug via a barrier metal. This process will be described with reference to FIGS. First, as shown in FIG. 1, the SiO _x interlayer insulating film 3 is laminated on the single crystal silicon substrate 1, the impurity diffusion regions 2 are formed in advance, further the impurity diffusion regions 2 in this SiO _x interlayer insulating film 3 A contact hole 4 facing the above was opened.

Next, a barrier metal 7 having a two-layer structure composed of a Ti film 5 and a TiN film 6 is formed on the entire surface of the wafer by a sputtering method, and further, Blk-W is formed by a CVD method using a WF ₆ / H ₂ mixed gas. The film 8 was formed to a film thickness of about 400 nm and the wafer surface was flattened.

Next, the Blk-W film 8 and the barrier metal 7 are etched back until the upper surface of the SiO _x interlayer insulating film 3 is exposed, and the W plug 8 p is formed only inside the contact hole 4 as shown in FIG. (The subscript p indicates that it is a plug. The same shall apply hereinafter) and the barrier metal 7p is left.

Next, this wafer is set in the film forming chamber of the sputtering apparatus, which has been evacuated to a vacuum degree of 2 × 10 ^-8 Pa in advance, and the entire surface of Al-0.
A 5% Cu film 9 was formed to a film thickness of about 500 nm. An example of film forming conditions is shown below. Ar flow rate 40 SCCM Gas pressure 0.47 Pa RF power 22.5 W (13.56 MHz) Wafer stage temperature 300 ° C. The Al-0.5% Cu film 9 formed here is a conventional general-purpose film. Unlike the Al-based wiring film, it does not contain Si,
The melting point is about 630 ° C. by containing 5% Cu, which is lower than that of pure Al (melting point: 660 ° C.). This A
The l-0.5% Cu film 9 was formed with good coverage even under wafer heating at about 300 ° C.

Conventionally, one of the purposes of adding Si to the Al-based wiring film has been to suppress the alloying reaction between Al and Si when making direct contact with the Si substrate. However, in this embodiment, since the contact with the impurity diffusion region 2 is made through the W plug 8p, no inconvenience caused by not adding Si does not occur.

Subsequently, as an example, plasma CVD was performed under the following conditions to form a SiON antireflection film 10 on the Al-0.5% Cu film 9. SiH ₄ flow rate 50 SCCM N ₂ O flow rate 50 SCCM Gas pressure 332.5 Pa RF power 190 W (13.56 MHz) Wafer stage temperature 360 ° C. Electrode distance 1 cm In this plasma CVD process, a film has already been formed. A
The 1-0.5% Cu film 9 is also heated to 360 ° C. However, Cu contained in the Al-Cu film 9 did not form nodules unlike Si. In addition, since the residual moisture in the Al-0.5% Cu film 9 was reduced by high vacuum exhaust before film formation, hillocks did not grow in the cooling process after the plasma CVD.

Thereafter, KrF excimer laser lithography is performed using this SiON antireflection film 10,
A good resist pattern 11 was formed while effectively reducing halation and standing wave effects. Further, using the resist pattern 11 as a mask, the SiON antireflection film 10 and the Al-0.5% Cu film 9 are formed by using, for example, BCl.
Etching was performed using a ₃ / Cl ₂ mixed gas.

By the above process, as shown in FIG. 4, an Al-based wiring having good contact performance could be formed without forming nodules or hillocks. In addition, instead of the Al-0.5% Cu film 9,
Similar results were obtained when using a 1-2% Ge film, an Al-1% Ga film, an Al-1% Au film, or the like.

Embodiment 2 This embodiment is an example in which a Ti / Cu laminated wiring film is used as the constituent material of the upper layer wiring instead of the Al type wiring film. This process will be described with reference to FIGS.
The reference numerals in these drawings are partially common to those in FIGS. 1 to 4 described above. First, as shown in FIG. 5, a Ti film 12 having a thickness of about 30 nm and a thickness of about 30 nm are formed on the wafer on which the Blk-W film 8 has been etched back as in the first embodiment.
The Cu film 13 having a thickness of 0 nm was sequentially formed by the sputtering method.

[Ti Film 12 Film Forming Conditions] Ar Flow Rate 100 SCCM Gas Pressure 0.47 Pa RF Power 4 kW (13.56 MHz) Wafer Stage Temperature 150 ° C. [Cu Film 13 Film Forming Conditions] Ar Flow Rate 100 SCCM Gas pressure 0.47 Pa RF power 4 kW (13.56 MHz) Wafer stage temperature 150 ° C. Here, the Ti film 12 achieves ohmic contact between the W plug 8 p and the Cu film 13. It is provided.

Next, plasma CVD was performed, for example, under the same conditions as in Example 1 to form a SiON antireflection film 14 on the Cu film 13 as shown in FIG. This plasma C
In the process of VD, the Cu film 13 already formed is 36
Although it was heated to 0 ° C., since it was originally a pure metal film, there was no concern about nodule formation, and unlike the Al-based wiring film, no hillock growth was observed.

Subsequently, when KrF excimer laser lithography was performed, a resist pattern 15 having high dimensional accuracy and good anisotropic shape was formed by the effect of the SiON antireflection film 14. Using this as a mask, the SiON antireflection film 14 was etched using c-C ₄ F ₈ gas as an example. Next, prior to etching the Cu film 13, the resist pattern 15 was once ashed. This is 30 when the Cu film 13 is etched.
This is because the resist pattern 15 cannot withstand wafer heating at about 0 ° C. Here, using the newly exposed SiON antireflection film 14 as a mask, for example, SiCl ₄ / N _{2 is used.}
The Cu film 13 was etched using a mixed gas.

The Cu-based wiring having good contact performance could be formed by the above process.
Incidentally, instead of the Cu film 13, an Ag film, an Au film, a W film,
Alternatively, the same result was obtained when the Mo film was used.

The present invention has been described above based on the two embodiments, but the present invention is not limited to these embodiments. For example, although SiON is used as the constituent material of the antireflection film in the above-described embodiments, SiO or SiN is used.
Basically, the same result can be obtained by using. In addition, it goes without saying that the structure of the sample wafer, the sputtering conditions, the plasma CVD conditions, the composition of the etching gas, etc. can be changed as appropriate.

[0040]

As is clear from the above description, according to the present invention, even when an antireflection film which requires wafer heating during film formation is used, the covering property of the wiring film, the contact performance and the throughput are impaired. Therefore, the problems of nodule formation and hillock growth in the wiring film can be solved. As a result, the performance deterioration of the wiring film is prevented, and the fine processing of the wiring film is supported by highly accurate photolithography using the antireflection film.

Therefore, the present invention greatly contributes to higher performance and higher integration of semiconductor devices through higher reliability in wiring formation.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a state in which a contact hole is covered with a barrier metal and a Blk-W film in a process example in which the present invention is applied to the formation of an Al-based upper layer wiring via a W plug.

FIG. 2 is a schematic cross-sectional view showing a state in which the Blk-W film and the barrier metal of FIG. 1 are etched back to form a W plug.

3 is a schematic cross-sectional view showing a state in which an Al-0.5% Cu film and a SiON antireflection film are formed on the W plug of FIG.

4 is a SiON antireflection film and Al-0.5 of FIG.
FIG. 6 is a schematic cross-sectional view showing a state in which a% Cu film is patterned.

FIG. 5 is a view showing an example of a process in which the present invention is applied to the formation of a Cu-based upper layer wiring via a W plug, in which Ti is deposited on the W plug.
It is a typical sectional view showing the state where a film, a Cu film, and a SiON antireflection film were laminated one by one.

6 is a schematic cross-sectional view showing a state in which the SiON antireflection film of FIG. 5 is patterned.

FIG. 7 is a diagram illustrating Cu using the SiON antireflection film of FIG. 6 as a mask.
It is a typical sectional view showing the state where a film was etched.

FIG. 8: In the conventional Al-based wiring formation process, S
FIG. 3 is a schematic cross-sectional view showing a state where an Al-1% Si film is formed on an iO _x interlayer insulating film.

9 is a schematic cross-sectional view showing a state in which granular Si nodules are formed when forming a SiON antireflection film on the Al-1% Si film of FIG.

FIG. 10 is a pattern of the Al-1% Si film of FIG.
It is a typical sectional view showing the state where Si nodule was taken in in an electrode pattern.

11 is a schematic cross-sectional view showing a state in which a layered Si nodule layer is formed when a SiON antireflection film is formed on the Al-1% Si film of FIG.

12 is a schematic cross-sectional view showing a state in which the Al-1% Si film of FIG. 11 is etched and the Si nodule layer is exposed.

13 is a schematic cross-sectional view showing a state in which an undercut occurs in the Al-1% Si film of FIG. 12 during overetching.

FIG. 14 is a schematic cross-sectional view showing a state in which a SiO _x interlayer insulating film is laminated on an Al-1% Si film in a conventional contact hole forming process.

15 is a schematic cross-sectional view showing a state in which granular Si nodules are formed when the SiON antireflection film is formed on the Al-1% Si film of FIG.

FIG. 16 shows a contact made to the SiO _x interlayer insulating film of FIG.
It is a typical sectional view showing a state where a hole is opened and a void is generated at the bottom of the opening.

FIG. 17 shows SiO _x in a conventional nodule prevention measure.
FIG. 4 is a schematic cross-sectional view showing a state in which a Ti film is formed on the interlayer insulating film.

18 is a schematic cross-sectional view showing a state in which an Al-Si-Ti ternary alloy film is formed when an Al-1% Si film is formed on the Ti film in FIG.

FIG. 19 is a schematic cross-sectional view showing a state in which hillocks are generated in the Al-1% Si film.

[Explanation of symbols]

3 ... SiO _x interlayer insulating film 4 ... contact hole 7 ... barrier metal 8p ... W plug 9 ··· Al-0.5% Cu film 10, 14 ... SiON antireflection film 12 ... Ti film 13 ... Cu film

Claims (7)

[Claims] 1. A main component of at least one silicon compound selected from silicon oxide, silicon nitride, and silicon oxynitride on a wiring film made of a pure metal material or a metal material obtained by adding a non-nodule-forming additive element to the pure metal material. A method for forming a wiring, which comprises forming an antireflection film. 2. The wiring forming method according to claim 1, wherein the additive element is an element that lowers the melting point of the pure metal material. 3. The wiring forming method according to claim 1, wherein the pure metal material is Al. 4. The additive element is Ti, Li, Cu, G
4. The wiring forming method according to claim 3, wherein the wiring is at least one element selected from a, Ge, and Au. 5. The pure metal material is Cu, Ag, Au,
The wiring forming method according to claim 1, wherein the wiring is at least one selected from W and Mo. 6. The wiring forming method according to claim 1, wherein a Ti-based material film is laminated immediately above and / or immediately below the wiring film. 7. The sputtering film, wherein the wiring film is evacuated to a vacuum level of 10 ⁻⁸ Pa or higher.
The film is formed by introducing an inert gas into the chamber and sputtering a target.
7. The wiring forming method according to claim 6.