JPH07182889A - Mask rom - Google Patents

Abstract

PURPOSE:To read out the data with less error for the fluctuation in a temperature and a source voltage by constituting so as to incorporate a dummy cell simultaneously precharged when a memory cell is precharged and in which a voltage generating at a reading time becomes always the voltage corresponding to a value of (1). CONSTITUTION:The memory cell to be accessed is selected by an X decoder 130 and a Y decoder 120 after a precharge signal PC is added. When the accessed memory cell is the memory cell 112a in which (1) is written, the memory cell is in an off state, and no drain potential of an FET 140 is changed. On the other hand, the dummy memory cell 200 is turned OFF always, and the voltage is outputted from an amplifier 220, and is divided by a voltage divider 222, and a reference voltage Vref is generated. Thus, at the time of reading out the data by comparing the drain potential of the FET 140 with the reference voltage Vref, the fluctuation in the drain potential of the FETs 140, 214 are canceled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM error compensation technique with respect to temperature fluctuations and power supply voltage fluctuations.

[0002]

2. Description of the Related Art As a conventional mask ROM, there is one disclosed in Japanese Patent Laid-Open No. 4-36098.
FIG. 2 shows an essential part of an example of a conventional mask ROM.

Mask ROM memory cell array 110
Is a memory cell 112 using an FET as shown in the figure.
It is configured by arranging a and b in a matrix. In the memory cells 112a and 112b, the drain and the source are sequentially connected in the column direction, and the gates are connected in the row direction. The memory cell 112a is an enhancement type FET, and has data of "1" written therein. The memory cell 112b is a depletion type FET.
In the ON state, the data of "0" is written.

FETs 140 and 142 are provided for every two columns of the memory cell array 110. FET
The source of 140 is connected to the power source, and the FET
The source of 142 is grounded. When there is a negative logic precharge signal PC, the FET 140 is turned on, the FET 142 is turned off, and the memory cell array 11 is turned on.
A current flows in each column of 0 to perform precharge. At the time of subsequent reading, the X decoder 130 is for selecting the column, and the F decoder responds to the address signal from the outside in response to the F signal.
The ET 140 and the column having the memory cell to be accessed are energized. The Y decoder 130 selects a row in which a memory cell to be accessed is located, and sets the gate of the row to low level and the other to high level. This turns on the memory cells in that row and turns off the other memory cells.

If "1" is written in the memory cell to be accessed, the memory cell is in an off state (current is almost zero or small), and charges are held in the stray capacitance of the wiring in the column direction. , The drain potential of the FET 140 in that column does not change. "0" for the memory cell to be accessed
Is written, the memory cell is in the ON state and the drain potential of the FET 140 in that column is almost at the ground level.

A sense amplifier 150 is connected to the drain of each FET 140.
Outputs low if the source potential is higher than a predetermined threshold level, and outputs high if the source potential is low. An FET 160 is connected to the output of each sense amplifier 150, and a FET 170 that is turned on when there is a precharge signal PC ′ is connected between the drain of the FET 160 and the positive power supply.

If "1" is written in the memory cell to be accessed, the drain potential of the FET 160 becomes high, and if "0" is written, the drain potential of the FET 160 becomes low. This is D flip-flop 1
It is taken in by 80 and output.

[0008]

In the above configuration, the memory cell in which "1" is written is in the off state at the time of precharging at low speed, at high temperature, or when the power supply voltage fluctuates. The current leaks and the drain potential of the FET 140 becomes low during reading. Therefore, the threshold level of the sense amplifier 150 may not be reached, and the data of "1" may be mistakenly read as the data of "0".

Therefore, an object of the present invention is to obtain a mask ROM which operates stably in a wide temperature range and voltage range.

[0010]

In order to solve the above-mentioned problems, the mask ROM of the present invention has a plurality of FETs forming memory cells arranged in a matrix, and the drain-source of each FET arranged in the column direction. Have a memory cell array in which the gates of the FETs arranged in the row direction are connected in common, and precharging is performed for all columns from the column direction of the memory cell array, Then, by applying address information to the gate, the voltage is generated in advance in the memory cell depending on whether the voltage generated on the wiring of the column having the memory cell to be accessed is the first value or the second value smaller than the first value. In a mask ROM that discriminates and reads the stored data, the voltage generated at the time of reading is always A dummy cell having a voltage corresponding to a value of 1, a voltage divider that divides a voltage generated in the dummy cell to generate a reference voltage when reading the memory cell, a voltage that occurs when reading the memory cell, and a reference voltage. And a sense amplifier for comparing and determining the data written in the memory cell.

[0011]

In the mask ROM of the present invention, the voltage generated in the memory cell at the time of reading has a magnitude (1 and 0) depending on the data written in advance. At this time, the dummy cell is also read, and the voltage generated in the tammy cell is always high (1). Then, a reference voltage is generated from the voltage generated in this dummy cell and compared with this to determine the data written in the memory cell.

Here, if there is a temperature change or a power supply voltage change, the voltage generated in the memory cell at the time of reading changes. However, since the voltage generated in the dummy cell also changes and the reference voltage also changes, even if the voltage generated in the memory cell changes, the change is canceled, so that data with few errors can be read.

[0013]

Embodiments of the present invention will be described with reference to the drawings.
Descriptions of the same or equivalent elements as those of the above-described conventional example will be simplified or omitted.

FIG. 1 shows the configuration of the essential parts of an embodiment of the present invention. This mask ROM has memory cells 200 and memory cells 112b, 112b,
It is characterized by having FETs 214 and 216, and having an amplifier 220, a voltage divider 222 and a sense amplifier 240.

The other structure is similar to that of the conventional example described above, and has a memory cell array 110 in which memory cells 112a and 112b are arranged in a matrix, and precharge is performed for every two columns of the memory cell array 110. FET to do
140, 142, an X decoder 130 for selecting columns, and a Y decoder 130 for selecting rows are provided. The memory cells 112a and 112b are of an enhancement type and a depletion type by ion implantation according to the written data "1" and "0".

The memory cell 200 is an enhancement type FET, the gate of which is grounded and is in an off state. A memory cell 212b, which is a depletion type FET formed by implantation, is connected in series to the memory cell 200. FETs 214 and 216 are for precharging these memory cells. The precharge operation is similar to that of the above-mentioned conventional example, and the precharge signal P
C turns on the FET 214 and turns off 216. In this way, a current is passed from the positive power supply, and charges are stored in the wiring capacitance, and then reading is performed.

The amplifier 220 and the voltage divider 222 have a voltage (FE) generated when reading a dummy memory cell.
Drain potential of T140) to reference voltage V _ref
Is generated. Each sense amplifier 240 compares the drain potential of the FET 140 generated during reading with the reference voltage V _ref and becomes high when the former is large, and becomes low when the latter is large. Each sense amplifier 2
The FET 160 is connected to the output of 40, and the FE is connected between the drain of the FET 160 and the positive power source.
T170 is connected. The FETs 160 and 170 and the D flip-flop 180 are the same as those in the above-described conventional technique, and the output of the sense amplifier 240 is inverted and taken into the D flip-flop 180 and output.

The data written in the memory cell array 110 can be accessed by the X decoder 1 as in the conventional example described above.
A column to be read is selected at 30, and the column is read. The row having a memory cell to be accessed by the Y decoder 120 is set to low level and the other rows are set to high level. If the data “1” written in the memory cell is, the electric charge is held in the floating capacitance of the wiring in the column direction and the source potential of the FET 140 does not change. If the data “0” is the FET 14,
The source potential of 0 becomes the ground level. At the same time as this operation,
Reading of the dummy memory cell is performed. The FET 214 is turned on and the transistor 216 is turned off by the precharge signal PC, and electric charge is accumulated in the floating capacitance. Since the memory cell 200 is always OFF, the voltage is output from the amplifier 220 without being discharged during reading. This voltage is divided by the voltage divider 222, and the FET 214
A reference voltage V _ref is generated according to the drain potential of the.

Here, when the low speed, the high temperature, or the power supply voltage fluctuates, the accessed memory cell is "1".
In the memory cell 112a in which is written, the current leaks and the drain potential of the FET 140 decreases although the memory cell 112a is in the off state. Similarly F
Since the drain potential of ET214 decreases, the reference voltage V _ref also decreases relatively. Therefore, even if there is such a change, whether or not "1" is written in the memory cell can be determined by the drain potential of the FET 140 being higher or lower than the reference voltage V _ref . That is, due to the leakage of the memory cell 112a, the FET
Even if the source potential of 214 changes, the change is canceled by the change of the reference voltage V _ref . Therefore, the data "1" is not erroneously read as "0", and the data with few errors can be read.

The sense amplifier 2 correctly determined in this way
The output of 40 is inverted, taken into the D flip-flop 180, and output.

The present invention is not limited to the above-mentioned embodiment, but various modifications are possible.

For example, although the memory cell 200 is connected to the ground side of the memory cells 212b connected in series, it may be connected between them. Further, a wiring pattern having a similar stray capacitance may be used instead of the memory cell 212b which is always on.

[0023]

As described above, according to the present invention, even if the voltage generated in the memory cell changes during reading due to the temperature change and the power supply voltage change, the voltage generated in the dummy cell also changes. Since the reference voltage also changes, even if the voltage generated in the memory cell changes, the change is canceled, so that data with few errors can be read and the mask ROM operates stably over a wide temperature range and voltage range. Can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment.

FIG. 2 is a configuration diagram of a conventional example.

[Explanation of symbols]

110 ... Memory cell array, 212b, 200 ... Memory cell, 240 ... Sense amplifier.

Claims (1)

[Claims] 1. A plurality of FETs forming a memory cell are arranged in a matrix, and the drains and sources of the FETs arranged in the column direction are sequentially connected, and the FEs arranged in the row direction.
The gates of T have memory cell arrays connected in common, and are precharged in the column direction of the memory cell array, and then address information is applied to the gates to generate on the wiring of the column in which the memory cell is to be accessed. In a mask ROM for discriminating and reading out data written in advance in the memory cell depending on whether the voltage is a first value or a second value smaller than the first value, a precharge is performed at the same time when the memory cell is precharged. A dummy cell whose voltage generated at the time of reading is always the voltage corresponding to the first value; a voltage divider which divides the voltage generated at the dummy cell to generate a reference voltage at the time of reading the memory cell; Of the data written in the memory cell by comparing the voltage generated at the time of reading with the reference voltage. Mask ROM that includes a sense amplifier to determine the data.