JPH07182858A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To set a normal refresh period at the period roughly matching with a refresh time with which almost memory cells are provided as capability and longer than heretofore. CONSTITUTION:A refresh controller 15 receives respective periodic signals of a first timer circuit 21 outputting a refresh period, a second timer circuit 22 outputting the periodic signal shorter than a value dividing the refresh period by the number of the whole word lines executing once refresh operation and a third timer circuit 23 outputting the divided period of the refresh period. An address of a cell array block or a word line incorporating a cell whose refresh time is not in time for the refresh period is stored in a storage circuit 25. This device is provided with a refresh counter 16 making the refresh period of the first timer circuit 21 a trigger, operating in synchronism with the period of the second timer circuit 22 and making the periodic signal of the third timer circuit 23 the trigger and executing the refresh operation based on the information in the storage circuit 25 and the refresh controller 15 controlling the counter 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to refreshing a dynamic RAM, and more particularly to a semiconductor memory device having a self-refresh mode in which a refresh operation (memory cell rewriting operation) is autonomously and periodically executed during battery backup. Regarding

[0002]

2. Description of the Related Art A dynamic RAM uses a capacitor as a storage element. This capacitor loses the amount of electric charge over time and loses retained data. So DRA
In M, a refresh operation is performed at an arbitrary time to restore data. Particularly recently, for example, a DRA having a self-refresh mode in which a refresh operation is autonomously and periodically executed during battery backup.
There is M.

FIG. 4 is a circuit block diagram of a conventional DRAM having a self refresh operation, and FIG. 5 is a waveform diagram showing the timing of the refresh operation of FIG. The "/" at the beginning of the signal display means an inverted signal of that signal, as in the case where a bar is added above the drawing.

The memory cell array 1 comprises memory cells each composed of a transfer transistor and a capacitor arranged in a matrix of word lines and bit lines (not shown). The row decoder 2 drives the word line with the address signal from the row address buffer 3. The column decoder 4 drives the bit line with the address signal from the column address buffer 5.

The first clock generator 6 receives the / RAS signal and generates a row address input trigger. The row address buffer 3 latches an externally input row address by this input trigger.

The second clock generator 7 receives the / CAS signal and generates a column address input trigger. The column address buffer 5 latches the column address input from the outside by this input trigger.

The sense amplifier / I / O gate 8 amplifies a signal on a bit line in the memory cell array 1 to output the data to the outside via the data line and the output buffer 9, and inputs the data from the outside to the input buffer. 10. Take in the memory cell array 1 through the data line. The operation timing of the input buffer 10 is controlled by the write enable signal / WE and the second clock generator 7, and the operation timing of the output buffer 9 is controlled by the output enable signal / OE and the second clock generator 7.

The refresh timer circuit 11 generates a cycle T equivalent to a time obtained by dividing the determined refresh cycle by the number of word lines in the memory cell array. The refresh controller 12 is an external signal for refresh operation.
When / REF is applied, the operation of the refresh counter 13 is controlled in synchronization with the cycle generated by the refresh timer circuit 11. In the refresh counter 13, a signal for sequentially designating an address at which a refresh operation is to be executed is supplied to the row address buffer 3 in synchronization with the above cycle, word lines are sequentially raised in the memory cell array 1, and data is read to the bit lines. Restored.

DR having the self-refresh operation
In the AM, the number of simultaneously operated memory arrays or the number of simultaneously selected word lines is limited by allowable power consumption and required refresh time.

The refresh time is the time after the memory cell is refreshed until the next refresh is required. Defective cells having an extremely short refresh time are screened by an initial test (die sort) or the like. After this screening, the refresh cycle should be set short with some allowance so as to cover all the remaining cells.

By the way, the self-refresh mode is
It is often applied to low power consumption products such as battery backup. Therefore, the refresh cycle tends to be longer than that of a general-purpose DRAM in order to reduce current consumption.
Therefore, in the test, the refresh cycle is lengthened. Therefore, a large number of products are determined to be defective only because of a small number of refresh leak cells, that is, cells having retention defects, and the product yield is lower than that of general-purpose products.

[0012]

The product to which the refresh mode is applied is the DRA for realizing low power consumption.
The refresh cycle of M is long, and there is not much margin in the refresh characteristic of the cell. Therefore, a cell that causes a retention failure occurs between the refresh time screened in the initial test (die sort) and the cycle time of the refresh operation.
They are handled as defective products that do not meet the refresh time standard. That is, there are many products that are determined to be defective only because of the cells that have retention defects, and the product yield is low.

The present invention has been made in consideration of the above circumstances. An object of the present invention is to set a refresh cycle for realizing low power consumption and to refresh a cell in which retention failure has occurred. An object is to provide a semiconductor memory device that operates.

[0014]

A semiconductor memory device according to the present invention includes a memory cell array composed of a plurality of dynamic memory cells arranged in rows and columns, and memory cells connected to the memory cells in the same row. A word line, each bit line connected to the memory cells in the same column, a word line drive circuit connected to one end of the word line, and a buffer for selectively driving the word line drive circuit according to an address signal. A circuit, a refresh counter for generating a word line address to be refreshed in the buffer circuit, a periodic signal generating means for generating a plurality of periodic signals, a refresh cycle by the periodic signal generating means,
An operation cycle of the refresh counter is set, and the refresh counter is operated by using the refresh cycle signal as a trigger to intensively refresh the entire memory cells in the memory cell array, and the memory cells whose refresh time is not in time for the refresh cycle are connected. A refresh control circuit for refreshing only the word line again via the refresh counter within the refresh cycle is provided.

[0015]

The entire cycle of the refresh operation and the operation cycle of the refresh counter are determined by the cycle signal generating means, and the refresh cycle signal is used as a trigger to synchronize with the operation cycle of the refresh counter (for example, a short cycle of write / read operation). The refresh counter operates. As a result, the refresh operation is intensively completed by the first half of the refresh cycle.

Therefore, most of the refresh cycle is in the precharged state (standby). The refresh operation is selectively executed again in order to relieve the memory cells having a short refresh time within the remaining refresh cycle. As a result, it is not necessary to shorten the entire refresh cycle only for the memory cell having the retention failure (short refresh time).

[0017]

1 is a circuit block diagram of a DRAM having a self-refresh operation according to an embodiment of the present invention, and FIG. 2 is a waveform diagram showing the timing of the refresh operation of FIG. The "/" at the beginning of the signal display means an inverted signal of that signal, as in the case where a bar is added above the drawing.

The memory cell array 1 comprises memory cells MC each composed of a transfer transistor and a capacitor arranged in a matrix of word lines WL and bit lines BL. The row decoder 2 drives the word line with the address signal from the row address buffer 3. The column decoder 4 drives the bit line with the address signal from the column address buffer 5.

The first clock generator 6 receives the / RAS signal and generates a row address input trigger. The row address buffer 3 latches an externally input row address by this input trigger.

The second clock generator 7 receives the / CAS signal and generates a column address input trigger. The column address buffer 5 latches the column address input from the outside by this input trigger.

The sense amplifier / I / O gate 8 amplifies the signal of the bit line in the memory cell array 1 to output the data to the outside via the data line and the output buffer 9 or to input the data from the outside to the input buffer. 10. Take in the memory cell array 1 through the data line. The operation timing of the input buffer 10 is controlled by the write enable signal / WE and the second clock generator 7, and the operation timing of the output buffer 9 is controlled by the output enable signal / OE and the second clock generator 7.

The refresh controller 15 is supplied with the periodic signals generated by the first timer circuit 21, the second timer circuit 22, and the third timer circuit 23. First
The timer circuit 21 generates the same cycle signal as the refresh cycle. The second timer circuit 22 generates a periodic signal shorter than a value obtained by dividing the above-mentioned determined refresh period by the total number of word lines executing one refresh operation. This short cycle signal has a short cycle of, for example, a normal write / read operation of the memory cell. In the third timer circuit 23, a cycle obtained by dividing the refresh cycle in the first timer circuit 21 is generated. This periodic signal has a half cycle of the refresh periodic signal, for example.

When a refresh operation signal / REF is applied from the outside, the refresh controller 15 controls the operation of the refresh counter 16 and the like according to the timer circuits 21 to 23.

The refresh operation of the circuit of FIG. 1 will be described with reference to FIG. When the self-refresh operation mode is set by the signal / REF, the first timer circuit 21 that generates a refresh cycle first operates the second timer circuit 22 having a short cycle, and the refresh controller 15 signals this cycle as a refresh master clock. .

The refresh controller 15 supplies a short cycle from the second timer circuit 22 to the refresh counter 16 and the first clock generator 6 by using the refresh cycle signal as a trigger. As a result, the row decoder 2 is selectively driven through the row address buffer 3, each word line is sequentially raised, and the refresh operation is intensively executed on the corresponding memory cells in the memory cell array, thereby The data is restored once.

As a result, the refresh operation of all the word lines is instantly completed, and most of the time until the refresh operation trigger signal generated in the first timer circuit 21 is applied next time is in the precharge state, that is, the standby state. It becomes a state.

For example, the refresh cycle is 128 ms,
When the total number of word lines to be refreshed in the memory cell array for performing one refresh operation is 4096 and the write / read cycle time is 130 ns, the time required for the refresh operation of all word lines is 130 × 4.
It becomes about 532 μs at 096, and most of the refresh cycle is in the standby state.

Further, the periodic signal of half the refresh period in the third timer circuit 23 becomes a trigger signal for starting the refresh operation in the standby state during the normal refresh operation. The word line to be refreshed in this case includes a cell whose refresh characteristic is deteriorated. That is, a memory cell having a data holding time shorter than the cycle generated by the first timer circuit 21 and longer than the cycle generated by the third timer circuit 23 is relieved by this refresh.

The memory circuit 25 stores the address of the memory cell array block including the cell whose refresh characteristic is deteriorated. In this case, the refresh counter 16 sets the register value to the start address of the row address of this block, increments only the number of word lines arranged in the cell array, generates the row address, and outputs only the desired word line group. Start up and perform refresh operation.

If the number of blocks stored in the memory circuit 25 is plural, the process is repeated for that number of blocks.
When the refresh operation is completed for the number of times of that block,
The register value of the refresh counter returns to the initial value,
Wait for the next refresh operation.

By increasing the number of frequency divisions of the refresh cycle, several kinds of refresh cycles can be generated. By storing the worst refresh time of the cells included in each memory cell array in the storage circuit 25 in advance, the optimum refresh cycle for each cell array can be selected.

That is, the refresh characteristic of each cell is tested by the initial test (die sort) in the DRAM device. As a result, if a cell whose refresh characteristic is deteriorated is included, the cell array block number and the refresh characteristic are converted into data, and the wiring in the memory circuit 25 is cut based on the data, and the desired block and refresh time are set. Memorize The wiring can be cut by means of fusing with a laser beam or destruction by applying a high electric field.

According to the configuration of the above embodiment, the refresh operation for all word lines uses the same signal as the refresh cycle as the trigger signal for the refresh operation and sets the refresh cycle to 1
The refresh counter is operated in synchronization with a cycle shorter than the value divided by the total number of word lines for executing the refresh operation once, the word line is activated, and the cell data is restored. By thus completing the refresh operation intensively, most of the refresh cycle is in the precharged state.

Then, with the cycle obtained by dividing the refresh cycle as a trigger signal, the refresh operation is performed by interruption during the refresh operation of all word lines. At this time, only the cell array block including the cell having the deteriorated refresh characteristic is refreshed. This allows
Even if there is a cell in which the refresh characteristic is deteriorated, retention failure does not occur.

In addition to the current during the refresh operation for all cells, the current for interrupt refresh operation increases, but the number of refresh times is smaller than that for all word lines, and the average current consumption does not increase significantly. Moreover, since the cells whose refresh characteristics have deteriorated are relieved, the refresh cycle can be made longer overall.

In the above embodiment, the memory circuit 25 stores the address of the cell array block including the cell having the deteriorated refresh characteristic. However, the word line address including the cell having the deteriorated refresh characteristic is shown. Can be stored.

That is, the cell with the deteriorated refresh characteristic is detected in advance by the test, and the memory circuit 25 stores the word line address to which the memory cell with the deteriorated refresh characteristic is connected.

In this case, the refresh counter 16 is set to the register value of the stored row address of the word line, and only the desired word line is raised to perform the refresh operation. If there are a plurality of stored word lines, the operation is repeated by the number of word lines. When the refresh operation is completed the number of times for the word line, the refresh counter value returns to the initial value and waits for the next refresh operation.

When a memory cell whose refresh characteristic is deteriorated extends over several consecutive word lines, the memory circuit 25 stores the start address and the end address of the word line in question, and the refresh counter 16 operates the word. Set the start address and end address of the line to the register value, increment from the start address to the end address,
Only the desired word line is raised to perform the refresh operation.

If there are a plurality of word line groups stored in the memory circuit 25, the same number of word line groups is repeated. When the refresh operation is completed by the number of word line groups, the register value of the refresh counter returns to the initial value and waits for the next refresh operation.

According to the DRAM as described above, the interrupt refresh operation performed in the precharged state in most of the refresh cycle by intensively completing the refresh operation causes the word line including the cell whose refresh characteristic is deteriorated. Only do. Therefore, the number of word lines is significantly smaller than the total number of word lines. That is, there is almost no increase in the current of the interrupt refresh operation, which occurs separately from the current during the refresh operation of all cells, and the increase of the average current consumption is significantly small.

According to the configuration of the above embodiment, the refresh operation of all word lines is intensively performed, and most of the refresh cycles are in the precharged state. Then, with the cycle obtained by dividing the refresh cycle as a trigger signal, the refresh operation is performed by interruption between all word line refresh operations. At this time, only the word line including the cell having the deteriorated refresh characteristic is refreshed.
As a result, the retention failure does not occur even if there is a cell in which the refresh characteristic is deteriorated.

In addition to the current during the refresh operation for all cells, the current for interrupt refresh operation increases, but the refresh frequency is smaller than that for all word lines, and the average current consumption does not increase significantly. Moreover, since the cells whose refresh characteristics have deteriorated are relieved, the refresh cycle can be made longer overall.

FIG. 3 is a distribution diagram showing the refresh characteristics of the DRAM. Cells with an extremely short refresh time are screened by an initial test (die sort) or the like. Dashed line 31 indicates the cut point of the initial test. Normal memory cells have a uniform refresh time and have a normal distribution. It can be said that the peak 32 is the average ability as a device.

However, among the memory cells which are considered to be normal, there are some cells having a short refresh time, which is indicated by a point 33. Conventionally, it was general to set a refresh cycle 34 that also covers the memory cell shown at point 33.

Therefore, when it is desired to set a longer refresh cycle in order to adapt to a low power consumption product, the configuration of the present invention makes it possible to set a regular refresh cycle at point 35 in the same device. . For a small number of cells whose refresh time is shorter than this, it is sufficient to apply a short refresh cycle and selectively execute the refresh operation again within the refresh cycle 35. By taking the entire refresh period longer, the low quiescent current is relatively reduced.

[0047]

As described above, according to the present invention, it is possible to set a longer cycle than the conventional one as a regular refresh cycle, which is almost matched with the refresh time that most of the memory cells have.

With the refresh cycle signal as a trigger, the refresh counter operates in synchronization with a short cycle, and the refresh operation is completely completed by the first half of the refresh cycle. Most of the refresh cycle is in a precharged state (standby), during which a small number of memory cells having a short refresh time can be selectively refreshed again. As a result, the refresh characteristic can be guaranteed while maintaining low power consumption, and a semiconductor memory device suitable for a low power consumption product can be provided.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a DRAM having a self-refresh operation which is an embodiment of the present invention.

FIG. 2 is a waveform diagram showing the timing of the refresh operation of FIG.

FIG. 3 is a distribution chart showing refresh characteristics of DRAM.

FIG. 4 is a block diagram of a conventional self-fresh mode DRAM.

FIG. 5 is a waveform diagram of a refresh operation of a conventional self-fresh mode DRAM.

[Explanation of symbols]

1 ... Memory cell array, 2 ... Row decoder, 3 ... Row address buffer, 4 ... Column decoder, 5 ... Column address buffer, 6 ... First clock generator, 7 ... Second clock generator, 8 ... Sense amplifier / I / O gate , 9 ... Output buffer, 10 ... Input buffer, 15 ... Refresh controller, 16 ... Refresh counter, 21
... first timer circuit, 22 ... second timer circuit, 23 ... third timer circuit, 25 ... memory circuit.

Claims (4)

[Claims] 1. A memory cell array composed of a plurality of dynamic memory cells arranged in rows and columns, respective word lines connected to the memory cells in the same row, and connected to the memory cells in the same column. Each of the bit lines, a word line drive circuit connected to one end of the word line, a buffer circuit for selectively driving the word line drive circuit according to an address signal, and a word line address to be refreshed by the buffer. A refresh counter for generating in the circuit, a periodic signal generating means for generating a plurality of periodic signals, a refresh cycle and an operation cycle of the refresh counter are set by the periodic signal generating means, and the refresh cycle signal is used as a trigger for refreshing. Operate the counter to centrally collect all memory cells in the memory cell array. A semiconductor memory device comprising: a refresh control circuit for refreshing and refreshing only a word line connected to a memory cell whose refresh time is not in time for the refresh cycle through the refresh counter again within the refresh cycle. . 2. A memory cell array composed of a plurality of dynamic memory cells arranged in rows and columns, respective word lines connected to the memory cells in the same row, and connected to the memory cells in the same column. Each of the bit lines, a word line drive circuit connected to one end of the word line, a buffer circuit for selectively driving the word line drive circuit according to an address signal, and a word line address to be refreshed by the buffer. A refresh counter for generating the circuit, a first timer circuit for setting a refresh cycle, and a cycle shorter than a value obtained by dividing the refresh cycle by the total number of word lines executing one refresh operation are set. A second timer circuit, a second timer circuit having a period shorter than that generated by the first timer circuit, and a second timer circuit
The third that generates a cycle longer than that generated by the timer circuit
In the memory cell array, the timer circuit and the first timer circuit are used as triggers to activate the refresh counter to activate each word line in synchronization with the periodic signal generated by the second timer circuit. A first refresh function for refreshing a corresponding memory cell, and the refresh counter is activated by using a periodic signal generated by the third timer circuit as a trigger during precharge during one period generated by the first timer circuit. A refresh function having a second refresh function in which a smaller number of word lines than all the word lines are sequentially activated in synchronization with the periodic signal generated by the second timer circuit to refresh the corresponding memory cells in the memory cell array. A semiconductor memory device comprising a control circuit. 3. A memory unit for storing one or more arbitrary word line addresses in the memory cell array, wherein the second refresh function in the refresh control circuit is executed by a word line address generated from the memory unit. The semiconductor memory device according to claim 2, wherein the semiconductor memory device comprises: 4. A memory cell having a data holding time, which is at least shorter than the cycle generated by the first timer circuit and longer than the cycle generated by the third timer circuit, in the word line corresponding to the address stored in the storage means. 4. The semiconductor memory device according to claim 3, wherein is connected to.