JPH07181885A - Controller - Google Patents

Abstract

PURPOSE:To automatically set the address of the control unit which is controlled by a main control unit. CONSTITUTION:Base sections 21 to 27 have slots 31 to 37 and are connected in multi-stages by a composite signal line 29. The slots 31 to 37 are connected with a CPU unit 39 and input output units 41 to 45. Logic circuits 47 to 51 are formed in the sections 23 to 27 of the units 41 to 45. The unit 39 successively outputs address signals and address definition signals. When the units 41 to 45 receive the address signals and the address definition signals, they set address by themselves and output gate signals which indicate the address setting to logic circuits 47 to 51. The subject logic circuits 47 to 51 make through the following stages when the address definition signals and the gate signals are assembled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device, in which a plurality of base portions are connected in multiple stages by a composite signal line, and a main control unit and controlled units controlled thereby are sequentially connected to the base portions. The present invention relates to an improvement of a control device mounted as described above, and more specifically to a control device capable of automatically setting addresses of these controlled units.

[0002]

2. Description of the Related Art Conventionally, a control device of this type is shown in FIG.
, A plurality of slots 1, 3, 5, 7, ... Connected to each other by a composite signal line (not shown) are arranged in a base unit 9, and a power supply unit 11, a CPU unit 13 as a main control unit and a controlled unit are controlled. I / O units 15, 17 ...
~ 7 ... It has a configuration in which it is attached so as to be connected to. In the figure, reference numerals 19a to 19d indicate units 11 to 1
Connection terminals provided in slots 1 to 7 for connecting to 7 ...

Such a control device includes a power supply unit 11
From the CPU unit 13 to each of the input / output units 15 to 17 while the power is being supplied from the CPU unit to the other units 13 to 17 ...
... is controlled by addressing, and the CPU unit 13 judges or calculates the operating procedure or the operating amount based on the measured temperature input from the input / output units 15, 17 ,. The operation procedure and the operation amount are output to a control target (not shown) to control the temperature of the control target by sequence control or program control.

In such a control device, a plurality of slots 1 to 7 are provided in advance with a margin, and the user is provided with input / output units 15 to 17 having various functions according to the purpose. There are many examples in which the number can be increased or decreased. Therefore, even if the number of input / output units 15-17 ... Is increased or decreased, in order to address the target input / output units 15-17 ... When mounting 17 ... in the individual slots 5-7 ..
Unique input / output address allocation is required.

Therefore, conventionally, each of the input / output units 15 to 1
7: An address assignment terminal and a DIP switch (all not shown) are provided on the internal circuit board, etc., and an address jumper wire is used between the terminals in consideration of the type of each input / output unit 15 to 17 ... By short-circuiting or operating the DIP switch, the address of each input / output unit 15 to 17 ... Was set. For example, digital input / output units are "1" to "5" and analog input / output units are "6".
~ The user was careful to set the address number such as "9" so that it would not be duplicated with other units and that the unit type and functional group would not be mistaken.

[0006]

However, in the configuration in which the address assignment of each of the input / output units 15 to 17 ... Is performed by the address jumper wire or the DIP switch of each unit as described above, many users are required. Since an address has to be set for each unit, the assignment work is complicated, erroneous settings are likely to occur, and the control device may not operate as intended.

Further, in recent control devices, from the viewpoint of emphasizing the system expandability on the user side, in place of the structure in which a plurality of slots are arranged in the base unit, each unit has a slot to be connected. A configuration is provided in which a separate and independent base portion is supported by a rail member or the like so that it can be increased or decreased, and a user attaches an input / output unit to an arbitrary base portion according to the application. Also in the configuration, labor saving of the address assignment of the input / output unit is desired.

Therefore, the present inventor has paid attention to the individual base portions connecting the respective units, and has completed a control device in which the address setting is labor-saving. The present invention has been made under such circumstances, and it is possible to automatically set the address of the controlled unit controlled by the main control unit.
An object of the present invention is to provide a control device that simplifies the operation of the user.

[0009]

In order to solve such a problem, the present invention connects a plurality of individually independent base parts in multiple stages with a composite signal line, and connects a main control unit to a certain base part. At the same time, a controlled unit controlled by the main control unit is connected to the other base section, and an address signal section for sequentially outputting address signals and an address confirmation signal when outputting this address signal are output to the main control unit. An address confirmation signal section is provided, and when the address signal and the address confirmation signal are received in the controlled unit via the composite signal line under an address unset state, the contents of the address signal are self-set and the set state is set. Is formed so as to output a gate signal indicating that the address determination signal and gate Form a logic circuit for transmitting the address determination signal to the next stage of the base portion when the signal are aligned.

Further, according to the present invention, the logic circuit is formed so that the gate signal is applied when the controlled unit is not connected to the base portion, and the gate signal is set to the non-output state under the address unset state. It is advisable to form the controlled unit so that Further, according to the present invention, the logic circuit is formed so that the gate signal is applied from the power supply through the pull-up resistor, and when connected to the base portion, the power supply current is absorbed through the pull-up resistor. The controlled unit can be formed so that the gate signal is in the non-output state.

[0011]

According to the present invention having such means, when the main control unit outputs the address signal and the address confirmation signal through the composite signal line, the address signal and the address confirmation signal are received under the address unset state. The controlled unit self-sets the content of the address signal and outputs a gate signal indicating the setting state, and the logic circuit of the base unit to which the controlled unit is connected advances to the next stage by the address confirmation signal and the gate signal. The address confirmation signal is ready for transmission. Therefore, when the main control unit sequentially outputs the address signal, the addresses are automatically set sequentially from the controlled unit near the main control unit.

Further, the logic circuit is formed so that the gate signal is applied in the state where the controlled unit is not connected, and the controlled unit is controlled so that the gate signal is not output in the unaddressed state. In the formed structure, the address confirmation signal is transmitted also to the base portion after the base portion to which the controlled unit is not connected. Further, in the configuration in which the logic circuit is formed so as to form the applied state of the gate signal from the power supply through the pull-up resistor and the controlled unit is formed so as to absorb the power supply current, the gate signal The formation and switching arrangement is simplified.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing an embodiment of a control device according to the present invention. In FIG. 1, a plurality of independently formed base portions 21, 23, 25, 27, ... Are connected to each other by a composite signal line 29 and have slots 31, 33, 35, 37. A CPU unit 39 as a main control unit and input / output units 41, 43, 45 as controlled units are connected to the individual slots 31 to 37.

1, the CPU unit 39 and the input / output units 41 to 45 ...
... are shown separated from the slots 31 to 37, and the base portions 21 to 27 ... are four and the input / output unit 4 is shown.
1 to 45 ... are shown three, but the present invention is not limited to these numbers, and the illustration of the power supply unit which is not an essential part of the present invention is omitted. Further, the control device as an actual product arranges and supports the base portions 21 to 27 so as to fit on, for example, a rail portion not shown, and electrically controls the base portions 21 to 27 by means of connectors provided on the base portions 21 to 27. It is better to connect them mechanically and mechanically. In such a configuration, the composite signal line 29 corresponds to a connection terminal such as the connector.

The composite signal line 29 connecting the base portions 21 to 27 ... Includes power supply lines for supplying power to the units 39 to 45 and data signal lines such as serial transmission for transmitting data signals, which will be described later. It has an address signal line and an address confirmation signal line for switching. Each base portion 21-27
...... supplies power from the composite signal line 29 to the units 39 to 45 through the slots 31 to 37, and inputs the signals between the connected units 39 to 45 and the composite signal line 29. It is to output.

In particular, logic circuits 47, 49, 51 which are serially inserted in the address confirmation signal line are formed in the base portions 23-27, ... To which the input / output units 41-45. , When the address confirmation signal and the gate signal described later are aligned, the 2-input AND (A
ND) circuit function, which will be described in detail later.

The CPU unit 39 controls the addresses of the input / output units 41 to 45 by designating them.
For example, the operation procedure and the operation amount are judged or calculated based on the measured temperature input from the input / output units 41 to 45.
It transmits / receives measurement data and setting data to / from an external device such as a host computer, and sends setting data to an input / output unit. The address signals of these input / output units 41 to 45 ... It has an address signal section 53 that sequentially outputs through the line 29, and an address confirmation signal section 55 that outputs an address confirmation signal through the composite signal line 29 when the address signal section 47 outputs an address signal. Details will be described later.

The input / output units 41 to 45 ... Process and calculate the measured temperature input from the outside, and calculate data such as measured data and manipulated variables based on the measured data.
Output to the outside or output the operation result to the outside as the manipulated variable, and when the address confirmation signal is received through the slots 31 to 37, if the input / output units 41 to 45 .. It has a function of self-setting the content of the address signal and outputting a gate signal indicating the address setting to the base portions 23 to 27 ....

Next, the details of the control device of the present invention will be described with reference to FIG. In addition, in FIG.
1, 23, CPU unit 39 and input / output unit 4
Although only one is shown, the configurations of the other base portions 25, 27 ... And the input / output units 43, 45. Figure 2
At the C connected to the slot 31 of the base portion 21 at
The PU unit 39 has a control unit 57, a data signal unit 59, an address signal unit 53, and an address confirmation signal unit 55 connected to the control unit 57.

The data signal unit 59 is a timing adjustment interface for transmitting and receiving a data signal between the data signal line 61 in the composite signal line 29 and the control unit 57. The address signal unit 53 is a timing adjustment interface that outputs an address setting start signal and an address signal to the address signal line 63 in the composite signal line 29 under the control of the control unit 57. Address confirmation signal section 55
When the address signal is output, the address confirmation signal line 65 in the composite signal line 29 is also under the control of the control unit 57.
Is a timing adjustment interface for outputting an address confirmation signal, and is connected to one input end of the logic circuit 47 of the slot 33 closest to the slot 31 (see FIG. 3).

The control unit 57 includes a CPU for performing main control of the CPU unit 39, a ROM containing a program to be executed by the CPU unit 39, a RAM for temporarily storing data of the execution process, and the like. Although it is included, illustration is omitted. The control unit 57 controls the data signal line 6
1, the operation amount and the like are calculated based on, for example, the measured temperature from the input / output unit 41 input via the data signal unit 59.
In addition to the basic judgment calculation function as a control device such as the function of outputting to the data signal line 61 via the data signal section 59, directly outputting to the outside separately, and further inputting various operations, It has such a function.

That is, the address setting start signal is output via the address signal section 53, and then the address signals are output in a predetermined order, and at the same time, the address confirmation signal section 5 is output.
5, while the address confirmation signal is output via 5, while the address confirmation signal is input from the input / output unit 41 via the data signal section 59 as described later, an address signal indicating the next address content is output to confirm the address. This is a function to repeat this in sequence until no signal is input. In addition,
The timing at which the control unit 57 outputs the address setting start signal via the address signal unit 53 may be when the power is turned on or when the operation key is operated during operation or at any other time.

Further, although the data signal line 61, the address signal line 63, and the address confirmation signal line 65 are one in FIG. 2, they are actually formed by a plurality of signal lines. Input / output unit 4 connected to slot 33 of base portion 23
1 is a data communication unit 6 connected to the address signal line 63
7, a control unit 69 connected to this, and a signal processing unit 71 connected to this. The data communication unit 67 operates under the control of the control unit 69, and when the data signal with an address is transmitted from the CPU unit 39, if the address number registered in the input / output unit 41 is the same, It has a function of receiving a data signal and outputting an address confirmation signal to the data signal line 61 when the address allocation is confirmed as described later.

The control unit 69 has a CPU, a ROM (not shown) storing an operation program for the CPU, and the like, and has a function different from that of the CPU unit 39. Exchange data signals between
It has a function of calculating a manipulated variable based on, for example, the measured temperature data that has been fetched and transmitting and controlling it as display data to the CPU unit 39, and other basic functions as an input / output unit. The control unit 69 has a function of storing the address number of the input / output unit 41 and outputting an address confirmation signal via the data communication unit 67 when the address allocation is confirmed.

The signal processing section 71 operates under the control of the control section 69 and clears the address number in the control section 69 when an address setting start signal for transmitting the address signal line 63 is inputted from the terminal A. When the address signal is input from the terminal A under the address unset state where the self address is not set, if the address confirmation signal is input from the terminal B, the address number is stored in the control unit 69. In addition, the signal processing unit 71 uses the gate signal line 7
When the C terminal is connected to the other input terminal of the logic circuit 47 via 3, the output level of the C terminal is maintained at the L level when the address number in the control unit 69 is cleared, while the address allocation processing is performed. , C terminals have the function of changing and maintaining the output level at H level. When connected to the base portion 23, the signal processing portion 71 is formed so as to change the output level of the C terminal to the L level by absorbing the power supply current as described later.

As shown in FIG. 3, the logic circuit 47 includes a 2-input AND circuit 75 connected to the address confirmation signal line 65 and the gate signal line 73, and its gate signal line 73.
It has a pull-up resistor R inserted between the power supply V and the power supply V, and the output side of the AND circuit 75 is connected to one input end of the logic circuit 49 of the base section 25 of the next stage (see FIG. 1). ). Therefore, if the input / output unit 41 is not mounted in the slot 33 of the base portion 23, the power supply voltage is applied to the other input end of the logic circuit 47 by the action of the pull-up resistor R and the H level is set. If the signal processing unit 71 is formed so as to absorb the current from the power source through the gate signal line, when the input / output unit 41 is mounted in the slot 33 of the base unit 23, the logic circuit 47 is formed.
The other input end of is at L level.

Next, the operation of the above-described control device of the present invention will be described with reference to the flow chart. As shown in FIG. 2, the CPU unit 39 is connected to the slot 31 of the base portion 21, and the input / output unit 41 is connected to the slot 33 of the base portion 23.
While connecting the input / output units 43, 45 ... Similarly, although not shown, when the program is started, the address setting start signal is sent from the address signal section 53 of the CPU unit 39 in step 401 as shown in FIG. Is output, prompting each of the input / output units 41 to 45 ... to prepare for address setting.

Then, for example, the input / output units 41 to 45
.., the address setting start signal is input in step 501 of FIG. 5, the address number in the control section 69 is cleared in the following step 502, and the C terminal of the signal processing section 71 is held at the L level in step 503. Put the address confirmation signal into the standby state. Therefore, as shown in FIG. 2, the other input end of the logic circuit 47 of the base portion 23 to which the input / output unit 41 is attached becomes L level, and the circuit connection to the next stage is cut off.

In this state, when, for example, the address signal "1" is output from the address signal section 53 in step 402 of FIG. 4, the address confirmation signal section 5 is output in the next step 403.
An address confirmation signal is output from 5. Then, on the input / output unit 41 side, as shown in FIG.
The address confirmation signal is received in step 1, and it is determined in step 602 whether the address setting is completed. If the address setting is completed and the answer is YES, the operation is ended.
03, the contents of the address signal are input from the A terminal of the signal processing unit 71 and allocated (registered) to the control unit 69.

In the following step 604, C of the signal processing unit 71
The terminal is switched from the L level to the H level and held, and in step 605, the data communication section 67 transmits an address confirmation signal to the data signal section 59 of the CPU unit 29, and the processing is terminated. On the other hand, the CPU unit 39 constantly monitors whether or not the address confirmation signal is received in step 404 of FIG. 4, and if the address confirmation signal is received and YES is determined, the address number is incremented by "1" in step 406. A new address signal “2” is created, and step 407
And outputs the updated address signal in step 403
And repeat this.

In this iterative process, the input / output unit 41 for which the address setting is completed does not react to the address confirmation signal, and the signal processing unit 7 is operated at step 604 of FIG.
Since the C terminal of 1 is switched to the H level and held, when the address confirmation signal is output to the logic circuit 47, the address confirmation signal passes through the logic circuit 47 and is transmitted to the base unit 25 of the next stage, The next-stage input / output unit 43 undergoes address allocation processing in the same procedure as the input / output unit 41, and the input / output unit 41 closer to the CPU unit 29 is processed.
Addresses are assigned in order from.

If the time during this period is about 10 I / O units and 100 ms at the latest, the address allocation is completed. All input / output units 41 to 45 ...
When the address setting of ... Is completed, step 404 in FIG.
Is NO, and in the following step 405, steps 404 and 405 are repeated until a predetermined time has elapsed, and when the time is up, the process ends.

As described above, in the control device of the present invention, the CPU
The unit 39 is provided with an address signal section 53 for sequentially outputting addresses and an address confirmation signal section 55 for outputting an address confirmation signal. The input / output units 41 to 45 ... When the address signals are self-set, the gate signals indicating the address settings can be output so that the base parts 21 to 27 ... Connected to the input / output units 41 to 45. When the gate signals are aligned, the logic circuits 47 to 51 for passing the address confirmation signal through to the base portions 21 to 27 of the next stage are formed.
Only by sequentially outputting the address signal and the address confirmation signal from the U unit 39, the addresses are automatically and sequentially set from the input / output units 41 to 45 ... Near the CPU unit 39.

Moreover, the logic circuits 47 to 5 of the base portions 21 to 27 ... to which the input / output units 41 to 45 ... Are connected.
A power source voltage V is applied to 1 ... via a pull-up resistor R, and the signal processing units 71 of the input / output units 41 to 45. The output unit 41 to 45 ... is the base unit 2
1 to 27 ... The input end is automatically set to the L level on the other side of the logic circuit 47, and an address confirmation signal passes through the logic circuit 47 in accordance with the address allocation of the input / output units 41 to 45. However, be sure to use CPU unit 3
Addresses are assigned from the one closer to 9.

Further, when the input / output units 41 to 45 ... Are removed from the base portions 21 to 27 ..
The other input end of 7 automatically becomes the H level, the address confirmation signal always passes through the logic circuit 47, the address is assigned from the input / output units 41 to 45 of the next stage, and the input / output units 41 to 45 ... Address can be set regardless of whether it is installed or not. That is, the input / output units 41 to 45 ...
... Remaining input / output units 41 to 45 even when removed
The address can be set for ..., and the system has high flexibility.

Further, when the unit removed after the address setting is mounted or the configuration is changed by adding a unit, the control unit 57 again sends the address signal unit 53.
If an address setting start signal is output via the to automatically set the address, the address is set in the changed configuration. Moreover, since the other input end of the logic circuit 47 is automatically set to the H level, it suffices to connect it from the power supply through the pull-up resistor R, so that the configuration is extremely simple.

Further, according to the present invention, the addresses are sequentially set to the input / output units 41 to 45 ... With the address confirmation signal, but the output timing of the address confirmation signal with respect to the output of the address signal is arbitrary. That is, it is possible to output the address confirmation signal after the output of the address signal, or to output the address signal during the output of the address confirmation signal.
Or the input / output units 41 to 45 ...

Further, in the above-described embodiment, the base portion 2
1 to 27 ... Slots 31 to 37 .. are used as connectors to connect the CPU unit 39 and the input / output unit 4
1 to 45 ... are connected, but it is not always necessary to provide the slots 31 to 37 ... to the base parts 21 to 27 .. .

[0039]

As described above, according to the present invention, in the controlled unit which outputs the address signal and the address confirmation signal from the main control unit and receives the address signal and the address confirmation signal under the unaddressed state, The contents of the address signal are self-set and a gate signal indicating the set state is output, and the logic circuit of the base unit connecting the controlled unit to which the address is set uses the address confirmation signal and the gate signal to the next stage. Since the address confirmation signal can be transmitted, if the main control unit outputs the address signal and the address confirmation signal sequentially, the addresses of the controlled units are set in sequence close to the main control unit, and the addresses of the controlled units are automatically set. It is possible to Therefore, the user does not need to operate the address jumper wire, the DIP switch, or the like for a large number of units to assign addresses, and there is an advantage that erroneous settings are eliminated and the operation is simplified. Further, since it is possible to make the configuration of the base portion connected to each controlled unit common, it is difficult to make an assembly error and the like, and the manufacturing efficiency is good. Further, if the logic circuit is formed so that the gate signal is in the applied state when the controlled unit is not connected, and the controlled unit is formed so that the gate signal is not output in the address unset state, The address confirmation signal is surely transmitted to the base unit and the base unit to which the controlled unit is not connected, and the address can be set to the mounted controlled unit regardless of whether or not the controlled unit is connected.
Furthermore, if a logic circuit is formed using a pull-up resistor to form an applied state of a gate signal and a controlled unit is formed so as to absorb a power supply current via the pull-up resistor, regardless of the connection of the controlled unit. There is an advantage that the configuration is not complicated because an address is set in the controlled unit.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a control device according to the present invention.

FIG. 2 is a principal block diagram showing a specific configuration of the control device according to FIG.

FIG. 3 is a circuit diagram showing an example of a logic circuit shown in FIG.

FIG. 4 is a flowchart illustrating the operation of the main control unit in the control device of the present invention.

FIG. 5 is a flowchart for explaining the operation of the controlled unit in the control device of the present invention.

FIG. 6 is a flowchart illustrating the operation of a controlled unit in the control device of the present invention.

FIG. 7 is a schematic perspective view showing a conventional control device.

[Explanation of symbols]

1, 3, 5, 7, 31, 33, 35, 37 Slot 9 Base unit 11 Power supply unit 13, 39 CPU unit (main control unit) 15, 17, 41, 43, 45 Input / output unit (controlled unit) 19a -19d Connection terminal 21, 23, 25, 27 Base part 29 Composite signal line 47, 49, 51 Logic circuit 53 Address signal part 55 Address confirmation signal part 57, 69 Control part 59 Data signal part 61 Data signal line 63 Address signal line 65 address confirmation signal line 67 data communication section 71 signal processing section 73 gate signal line 75 AND circuit (AND) R resistance

Claims (3)

[Claims] 1. A plurality of independent base units are connected in multiple stages by a composite signal line, a main control unit is connected to the base unit, and a controlled unit controlled by the main control unit is connected to another base unit. In the control device, the main control unit has an address signal section that sequentially outputs an address signal and an address confirmation signal section that outputs an address confirmation signal when outputting the address signal, and the controlled unit is When the address signal and the address confirmation signal are received through the composite signal line under an unset state, the contents of the address signal are self-set and a gate signal indicating the set state is outputable. The base unit to which the controlled unit is connected is controlled by the controlled unit of the next stage when the address confirmation signal and the gate signal are aligned. A control device having a logic circuit for transmitting the address confirmation signal to the base unit for connection. 2. The logic circuit is formed to apply the gate signal when the controlled unit is not connected to the base portion, and the controlled unit does not output the gate signal when an address is not set. The control device according to claim 1, wherein the control device is formed to be in a state. 3. The logic circuit is formed in a state in which the gate signal is applied from a power source through a pull-up resistor, and the controlled unit is connected to the base portion to supply a power source current through the pull-up resistor. The gate signal is formed so as to be in a non-output state by suction.
The control device described.