JPH071772B2 - Method of forming integrated circuit connection part - Google Patents
Method of forming integrated circuit connection partInfo
- Publication number
- JPH071772B2 JPH071772B2 JP60137688A JP13768885A JPH071772B2 JP H071772 B2 JPH071772 B2 JP H071772B2 JP 60137688 A JP60137688 A JP 60137688A JP 13768885 A JP13768885 A JP 13768885A JP H071772 B2 JPH071772 B2 JP H071772B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- electrode pad
- connection
- solder
- solder bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
- H01L2223/6622—Coaxial feed-throughs in active or passive substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05551—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
- H01L2224/13028—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路の接続技術に関する。本発明は、さら
に詳しく述べると、フリップチップ方式を使用して、例
えばIC,LSI,超LSI等の集積回路チップをプリント配線基
板のような接続基板を接続する際に有用な集積回路接続
部を形成する方法に関する。本発明の集積回路接続部を
使用して集積回路チップと基板（カード）を接続する
と、特に高速の信号あるいは大電流の信号をチップ及び
カード間で有効にやりとりすることができる。TECHNICAL FIELD The present invention relates to an integrated circuit connection technique. More specifically, the present invention provides an integrated circuit connecting portion useful when connecting a connecting board such as a printed wiring board to an integrated circuit chip such as IC, LSI, VLSI using the flip chip method. Relates to a method of forming. When the integrated circuit chip and the substrate (card) are connected using the integrated circuit connecting portion of the present invention, particularly high-speed signals or high-current signals can be effectively exchanged between the chip and the card.
本発明者らの研究グループでは、集積回路チップを接続
基板に接続する場合、信号伝送線の接続端子をグランド
面の接続端子が取り込む面でフリップチップ方式により
接続するのが有利であるという知見を得、別に特許出願
をした（特開昭 - 号公報）。ところで、この接
続方法を実現する場合、接続基板上に形成されるべき集
積回路接続部の形成が問題としてあった。例えば、フリ
ップチップ方式における接続部形成方法として従来から
用いられている方法に、接続基板（カード）又は集積回
路チップの入出力端子部に真空蒸着によりハンダバンプ
を形成する方法があるというものの、この方法の実施に
必要な装置は高額であり、また、工程が複雑であり、し
たがって、量産性に劣るという欠点がある。また、ハン
ダペーストを用いて集積回路接続部を印刷する方法が提
案されているけれども、これでは、大サイズのパターン
はともかく、今本発明が得ようとしている200μｍ以下
の小サイズのパターンは実質的に形成不可能であるとい
う欠点がある。The research group of the present inventors has found that when connecting an integrated circuit chip to a connection substrate, it is advantageous to connect the connection terminal of the signal transmission line by a flip chip method in the plane taken in by the connection terminal of the ground plane. I obtained a patent application separately (Japanese Patent Laid-Open Publication No. Sho). By the way, in the case of realizing this connection method, formation of an integrated circuit connection portion to be formed on the connection substrate has been a problem. For example, a method that has been conventionally used as a method of forming a connection portion in the flip chip method is a method of forming solder bumps on a connection substrate (card) or an input / output terminal portion of an integrated circuit chip by vacuum evaporation. There is a drawback in that the apparatus required for carrying out (1) is expensive, the process is complicated, and therefore the mass productivity is poor. Although a method of printing an integrated circuit connecting portion using a solder paste has been proposed, this method is not limited to a large-sized pattern, but a small-sized pattern of 200 μm or less, which the present invention is about to obtain, is practically used. It has the drawback that it cannot be formed.
本発明の目的は、上記した従来の技術の欠点にかんがみ
て、高速信号伝送可能なチップ接続あるいは大電流の信
号を流す端子から他の端子への漏れ電流の影響を小さく
することができるチップ接続を実現するための、信号伝
送線の接続端子をグランド面の接続端子が取り囲む形
の、言わば同軸構造の集積回路接続部を形成する方法を
提供することにある。すなわち、これが今本発明が解決
しようとする問題点である。In view of the above-mentioned drawbacks of the conventional technology, an object of the present invention is to provide a chip connection capable of high-speed signal transmission or a chip connection capable of reducing the influence of a leakage current from a terminal for flowing a high-current signal to another terminal. It is an object of the present invention to provide a method for forming an integrated circuit connecting portion having a so-called coaxial structure, in which the connecting terminal of the signal transmission line is surrounded by the connecting terminal of the ground plane. That is, this is a problem to be solved by the present invention.
本発明者らは、このたび、同軸構造の接続部と同一形状
（平面形状）の電極パッドをもった接続基板と、それに
位置合わせ下に密着させた同じく前記接続部と同一形状
の貫通孔をもったマスクとから形成された断面形状が凹
形の溝にハンダバンプ形成材料を隙間なく充填して溶着
により下地電極パッドと一体化することにより、所望の
同軸構造の集積回路接続部を形成し得るということを見
い出した。The inventors of the present invention have recently established a connection board having an electrode pad having the same shape (planar shape) as the connection section of the coaxial structure, and a through hole having the same shape as the connection section, which is closely adhered to the connection board under alignment. It is possible to form an integrated circuit connecting portion having a desired coaxial structure by filling a solder bump forming material into a groove having a concave cross-section formed with a mask having a solder and forming it with a base electrode pad by welding. I found out that.
本発明による集積回路接続部形成方法は、すなわち、集
積回路チップの信号伝送線及びグランド面の接続端子が
接続されるべき接続基板の表面上に所定の形状の金属薄
膜を被着して電極パッドと同一形状の貫通孔を有するマ
スク、好ましくはメタルマスクを前記接続基板の表面と
密着させ、その際、前記電極パッド及び貫通孔を位置合
わせし、前記貫通孔の全体にハンダバンプ形成材料を充
填し、そして前記ハンダバンプ形成材料を加熱溶融する
ことによって所定の形状のハンダバンプを形成するとと
もにそのバンプを下地電極パッドに溶着させることを特
徴とする。The method for forming an integrated circuit connecting portion according to the present invention is to form an electrode pad by depositing a metal thin film having a predetermined shape on the surface of a connection substrate to which the signal transmission lines of the integrated circuit chip and the connection terminals of the ground surface are to be connected. A mask having a through hole of the same shape as that of the above, preferably a metal mask, is brought into close contact with the surface of the connection substrate, at that time, the electrode pad and the through hole are aligned, and the whole of the through hole is filled with a solder bump forming material. Then, the solder bump forming material is heated and melted to form a solder bump having a predetermined shape, and the bump is welded to the base electrode pad.
本発明の実施において、集積回路接続部を同軸構造の形
状となすために、例えば、信号伝送線の接続端子を中央
に配し、それと同心的に環状のグランド面接続端子を配
することができる。また、必要に応じて、グランド面接
続端子の形状を環状から矩形に変更することができる。In the implementation of the present invention, in order to form the integrated circuit connecting portion in the shape of the coaxial structure, for example, the connection terminal of the signal transmission line can be arranged in the center and the annular ground plane connection terminal can be arranged concentrically therewith. . In addition, the shape of the ground surface connection terminal can be changed from a ring shape to a rectangle shape as necessary.
本発明を実施する場合、先ず最初に、接続基板（カー
ド）の接続部分にチップの電極パッドに対応する形状の
金属薄膜、例えばCu,Au,Pd,Pd-Ag,Crなど，を蒸着、ス
パッタ等により被着して電極パッド（ハンダパッドとも
云う）を形成する。When carrying out the present invention, first, a metal thin film having a shape corresponding to the electrode pad of the chip, for example, Cu, Au, Pd, Pd-Ag, Cr, etc. is vapor-deposited and sputtered on the connection portion of the connection substrate (card). And the like to form electrode pads (also referred to as solder pads).
電極パッドの形成後、そのパッドと平面形状を同じくす
る貫通孔をもったマスク、特に例えばMoのような金属か
らなるメタルマスクをカードに密着させる。この密着の
際、電極パッドとマスクの貫通孔を正しく位置合わせす
る。After forming the electrode pad, a mask having a through hole having the same planar shape as the pad, particularly a metal mask made of a metal such as Mo, is brought into close contact with the card. During this contact, the electrode pad and the through hole of the mask are properly aligned.
次いで、マスクの貫通孔の全体に、すなわち、カードの
電極パッドとカードに密着させたマスクとから形成され
た凹形の溝にハンダバンプ形成材料、例えばPb-Sn,In-B
i,In-Bi-Sn,In-Snなどのハンダまたはハンダ合金材料を
好ましくは直径約50〜100μｍのボール又は粒径約２〜1
0μｍの粉末の形で隙間なく並べるかもしくは充填し、
これを加熱溶融させる。加熱溶融の温度は、用いられる
ハンダバンプ形成材料の溶融温度によって左右されると
いうものの、一般的には約50〜300℃の温度が用いられ
る。例えば、In系のハンダ合金を使用する場合には約60
℃の温度が好ましく、一方、Sn系のハンダ合金を使用す
る場合には約200℃を上回る温度が好ましい。Then, a solder bump forming material, such as Pb-Sn, In-B, is formed on the entire through-hole of the mask, that is, in a concave groove formed by the electrode pad of the card and the mask in close contact with the card.
A solder or solder alloy material such as i, In-Bi-Sn, In-Sn is preferably used as a ball having a diameter of about 50 to 100 μm or a particle size of about 2-1.
Line up or fill in the form of 0 μm powder without gaps,
This is heated and melted. Although the temperature of heating and melting depends on the melting temperature of the solder bump forming material used, a temperature of about 50 to 300 ° C. is generally used. For example, when using an In-based solder alloy, approximately 60
Temperatures of ° C are preferred, while temperatures above about 200 ° C are preferred when using Sn based solder alloys.
上記のようにしてハンダバンプ形成材料を加熱溶融させ
ると、所定の形成、例えばバンプ状、球状又は類似の形
成のハンダバンプがマスクの貫通孔内に形成され、同時
に、そのバンプと下地電極パッドとが強力に接合せしめ
られる。When the solder bump forming material is heated and melted as described above, a solder bump having a predetermined shape, for example, a bump shape, a spherical shape, or a similar shape is formed in the through hole of the mask, and at the same time, the bump and the base electrode pad are strong. Be bonded to.
カード上のマスクを除去した後、形成された集積回路接
続部に整合する電極パッドをもったチップとカードとを
該接続部のハンダバンプを介してフリップチップ接合す
る。After removing the mask on the card, a chip having an electrode pad matching the formed integrated circuit connecting portion and the card are flip-chip bonded via solder bumps of the connecting portion.
本発明による集積回路接続部の形成方法は例えば次のよ
うにして実施することができる。The method for forming the integrated circuit connection portion according to the present invention can be implemented, for example, as follows.
第１図は、本発明方法を有利に適用することのできる集
積回路チップの好ましい一例を示した略示図である。チ
ップ１は、図示される通り、信号伝送線のための電極パ
ッド２と、それを取り囲んで形成されたグランド面のた
めの電極パッド３とからなる複合電極パッドの複数個を
有する。本願明細書では、このような複合電極パッドの
ことを、特に、同軸構造をもった電極パッドあるいは接
続部と呼ぶ。電極パッド３は、中央にある信号伝送線の
電極パッド２がチップ内配線に接続される配線を通すた
めに部分的に開いている。第２図は、第１図に示した集
積回路チップの線分II-IIにそった断面図である。FIG. 1 is a schematic diagram showing a preferred example of an integrated circuit chip to which the method of the present invention can be advantageously applied. As shown in the figure, the chip 1 has a plurality of composite electrode pads each including an electrode pad 2 for a signal transmission line and an electrode pad 3 for surrounding a ground surface. In the specification of the present application, such a composite electrode pad is particularly referred to as an electrode pad or a connecting portion having a coaxial structure. The electrode pad 3 is partially opened so that the electrode pad 2 of the signal transmission line in the center can pass through the wiring connected to the in-chip wiring. FIG. 2 is a cross-sectional view of the integrated circuit chip shown in FIG. 1 along the line segment II-II.
本発明方法は、例えば、第3a図〜第3e図に断面で示され
る一連の工程を経て実施することができる： 先ず最初に、第２図に断面で示される構造をもった集積
回路チップを接続するための接続基板（カード）を用意
する。カード４は、第3a図に示されるように、内部配線
５を有する。The method according to the invention can be carried out, for example, through a series of steps shown in cross section in FIGS. 3a to 3e: First, an integrated circuit chip having the structure shown in cross section in FIG. Prepare a connection board (card) for connection. The card 4 has internal wiring 5 as shown in FIG. 3a.
次いで、第3b図に示されるように、カード４の表面上に
電極パッド６を被着する。この電極パッド又はハンダパ
ッド６の形状はそれにフリップチップ接合されるべき集
積回路チップ１の電極パッド２及び３の形状に一致す
る。Then, as shown in FIG. 3b, the electrode pad 6 is deposited on the surface of the card 4. The shape of this electrode pad or solder pad 6 corresponds to the shape of the electrode pads 2 and 3 of the integrated circuit chip 1 to be flip-chip bonded thereto.
次いで、第3c図に示されるように、カード４に被着した
電極パッド６に対応する部分が貫通孔となっているメタ
ルマスク７をカード４に密着させ、貫通孔によって形成
された凹形の溝に所定のサイズのハンダ合金ボール８を
緻密に整列させる。Then, as shown in FIG. 3c, a metal mask 7 having a through hole at a portion corresponding to the electrode pad 6 attached to the card 4 is closely attached to the card 4 to form a concave shape formed by the through hole. The solder alloy balls 8 of a predetermined size are closely aligned in the groove.
引き続いて約60〜250℃の温度でハンダ合金ボール８を
加熱溶融させる（第3d図）。ハンダボール８が一体とな
って図示される通りのハンダバンプ18が形成される。こ
のようにして形成された集積回路接続部のマスク７除去
後の状態を断面図で示すと、第3e図に示される通りであ
る。なお、形成可能な接続部パターン（ハンダバンプ）
の幅は使用するハンダボールの粒径に応じて約50〜100
μｍである。Subsequently, the solder alloy balls 8 are heated and melted at a temperature of about 60 to 250 ° C. (FIG. 3d). Solder balls 8 are integrally formed to form solder bumps 18 as shown in the figure. A cross-sectional view of the thus-formed integrated circuit connecting portion after the mask 7 is removed is as shown in FIG. 3e. Formable connection pattern (solder bump)
The width is about 50-100 depending on the particle size of the solder balls used
μm.
最後に、第５図に示されるように、通常のフリップチッ
プ方式を使用して、形成されたカード４の接続部（６＋
18）に第２図の集積回路チップ１の電極パッド２及び３
を接続する。Finally, as shown in FIG. 5, the connection part (6+) of the formed card 4 is formed by using the normal flip chip method.
18) shows the electrode pads 2 and 3 of the integrated circuit chip 1 of FIG.
Connect.
さらに、上記した接続部形成方法の一部を変更して、第
4a図〜第4c図に断面で示されるようにして実施すること
も可能である。すなわち、この変更方法では、ハンダボ
ールの代りにハンダ合金粉末９を使用しており（第4a
図）、これを第4b図に示されるように加熱溶融させて最
後にハンダバンプ19を得ている（第4c図）。なお、図示
の方法のハンダ合金粉末に代えて市販のハンダペースト
をマスク17の貫通孔を充填しても同様な結果を得ること
ができる。Furthermore, by changing a part of the above-mentioned connecting portion forming method,
It can also be carried out as shown in cross section in Figures 4a to 4c. That is, in this modification method, the solder alloy powder 9 is used instead of the solder ball (4a
(Fig. 4), this is heated and melted as shown in Fig. 4b to finally obtain the solder bump 19 (Fig. 4c). Similar results can be obtained by filling the through holes of the mask 17 with a commercially available solder paste instead of the solder alloy powder of the illustrated method.
本発明によれば、例えば第１図に示されるような同軸構
造の集積回路接続部に微細パターンで、しかも容易にか
つ大量に形成することができる。また、このような接続
部の形成が可能となる結果、高速信号あるいは大電流の
信号を集積回路チップと接続基板（カード）との間でや
りとりすることが保証される。According to the present invention, for example, it is possible to easily and in large quantities form a fine pattern on an integrated circuit connecting portion having a coaxial structure as shown in FIG. Further, as a result of enabling the formation of such a connection portion, it is guaranteed that a high-speed signal or a high-current signal is exchanged between the integrated circuit chip and the connection substrate (card).
第１図は、本発明において用いることのできる集積回路
チップの一例を示した略示図、 第２図は、第１図に示した集積回路チップの線分II-II
にそった部分断面図、 第3a図〜第3e図は、それぞれ、本発明方法の好ましい一
例を順を追って示した断面図、 第4a図〜第4c図は、それぞれ、第3c図〜第3e図の方法の
変形例を示した断面図、そして 第５図は、本願発明方法により形成された接続部を用い
たフリップチップ接続の一例を示した断面図である。 図中、１は集積回路チップ、２は信号伝送線の電極パッ
ド、３はグランド面の電極パッド、４は接続基板（カー
ド）、６は電極パッド、７及び17はマスク、８はハンダ
合金ボール、そして９はハンダ合金粉末である。FIG. 1 is a schematic diagram showing an example of an integrated circuit chip that can be used in the present invention, and FIG. 2 is a line segment II-II of the integrated circuit chip shown in FIG.
3a to 3e are sectional views sequentially showing a preferred example of the method of the present invention, and FIGS. 4a to 4c are respectively 3c to 3e. FIG. 5 is a cross-sectional view showing a modified example of the method shown in FIG. 5, and FIG. 5 is a cross-sectional view showing an example of flip-chip connection using a connection portion formed by the method of the present invention. In the figure, 1 is an integrated circuit chip, 2 is an electrode pad of a signal transmission line, 3 is an electrode pad on the ground plane, 4 is a connection substrate (card), 6 is an electrode pad, 7 and 17 are masks, 8 is a solder alloy ball. , And 9 are solder alloy powders.
Claims (3)
の接続端子をグランド面の接続端子が取り囲む形でフリ
ップチップ方式により接続する際の集積回路接続部を形
成する方法であって、 集積回路チップの信号伝送線及びグランド面の接続端子
が接続されるべき接続基板の表面上に所定の形状の金属
薄膜を被着して電極パッドとなし、 前記電極パッドと同一形状の貫通孔を有するマスクを前
記接続基板の表面と密着させ、その際、前記電極パッド
及び貫通孔を位置合わせし、 前記貫通孔の全体にハンダバンプ形成材料を充填し、そ
して 前記ハンダバンプ形成材料を加熱溶融することによって
所定の形状のハンダバンプを形成するとともにそのバン
プを下地電極パッドに溶着させることを特徴とする、集
積回路接続部を形成する方法。1. A method of forming an integrated circuit connecting portion for connecting a connection terminal of a signal transmission line to a connection substrate by a flip chip method in a manner of surrounding a connection terminal of a signal transmission line on a connection substrate, the method comprising: A metal thin film having a predetermined shape is deposited on the surface of the connection substrate to which the signal transmission line of the circuit chip and the connection terminal on the ground surface are connected to form an electrode pad, and a through hole having the same shape as the electrode pad is formed. A mask is brought into close contact with the surface of the connection substrate, at that time, the electrode pads and the through holes are aligned, a solder bump forming material is filled in the whole of the through holes, and the solder bump forming material is heated and melted to a predetermined size. A method for forming an integrated circuit connecting portion, which comprises forming a solder bump having the shape of 1) and welding the bump to a base electrode pad.
ールである、特許請求の範囲第１項に記載の方法。2. The method according to claim 1, wherein the solder bump forming material is a solder alloy ball.
末である、特許請求の範囲第１項に記載の方法。3. The method according to claim 1, wherein the solder bump forming material is a solder alloy powder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60137688A JPH071772B2 (en) | 1985-06-26 | 1985-06-26 | Method of forming integrated circuit connection part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60137688A JPH071772B2 (en) | 1985-06-26 | 1985-06-26 | Method of forming integrated circuit connection part |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61296728A JPS61296728A (en) | 1986-12-27 |
| JPH071772B2 true JPH071772B2 (en) | 1995-01-11 |
Family
ID=15204480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60137688A Expired - Fee Related JPH071772B2 (en) | 1985-06-26 | 1985-06-26 | Method of forming integrated circuit connection part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH071772B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63304636A (en) * | 1987-06-05 | 1988-12-12 | Hitachi Ltd | Solder carrier and manufacture thereof, and method of mounting semiconductor device using same |
| US6461953B1 (en) | 1998-08-10 | 2002-10-08 | Fujitsu Limited | Solder bump forming method, electronic component mounting method, and electronic component mounting structure |
| JP4006173B2 (en) | 2000-08-25 | 2007-11-14 | 三星エスディアイ株式会社 | Metal mask structure and manufacturing method thereof |
-
1985
- 1985-06-26 JP JP60137688A patent/JPH071772B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61296728A (en) | 1986-12-27 |
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