JPH07177137A - Frame phase synchronization circuit - Google Patents

Abstract

PURPOSE:To realize a frame phase synchronization circuit whose memory capacity is small, in which two address generating sections are not required for addresses of the memory and the occurrence of slip is prevented. CONSTITUTION:A memory 7 whose capacity is one frame is used for the circuit. Furthermore, a transmission signal from an input system is phase-shifted variably and the resulting signal is given to the memory. The circuit is provided with 1st variable phase shift means 1, 3 whose phase shift enable range depends on a phase fluctuation of an input system clock with respect to a received system clock and with 2nd variable phase shift means 2, 4 variably phase- shifting the input system frame pulse and giving the result to a write address generating section 6 whose phase shift range is decided similarly to the case with the 1st variable phase shift means, and also with a phase shift quantity control means 5 which detects the relation between the write phase and the read phase with respect to the memory to decide the common phase shift quantity of the 1st and 2nd variable phase shift means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame phase synchronizing circuit (frame aligner).

[0002]

2. Description of the Related Art In a communication network, when the same prescribed frame format transmission line signal is transmitted between systems of different clock systems, it is possible to switch clocks and synchronize with the frame phase of the destination system. This is necessary, and a frame phase synchronizing circuit is provided to perform such processing.

Usually, the frame format of a transmission path signal is composed of a communication network operation management information section (overhead) and a main signal section (payload). On the transmission line,
The payload phase is arbitrary with respect to the frame format phase. For example, when transferring a transmission path signal from the transmission path clock system to the in-station clock system, construct an overhead of a frame format that is phase-synchronized with the in-station clock system, and set the payload phase specified by the in-station device to
Change the phase of the payload. In order to change the phase of the payload, in the frame phase synchronizing circuit, the payload part is written in the memory (elastic store memory) in the phase of the transmission path clock system and read from the memory in the phase of the local clock system.

When the write phase and the read phase of the memory approach within the minimum phase difference required for the phase fluctuation between the two clock systems and the frame phase synchronization conversion, the write phase and the read phase of the memory. There is a possibility that multiple slips will occur that will reverse. For example, if the write phase exceeds the read phase, the next data is written before the data once written to the memory is read, and if the read phase exceeds the write phase, the written data is delayed. The data is read twice, and the past data is read when the latter half is read.

In order to avoid such frequent occurrence of slip, in the prior art, the phase difference between the write phase and the read phase for the memory is monitored, and when both phases approach each other, one phase is checked. I was doing a forced change. That is, by causing the slip once, the slip is stabilized thereafter and the frequent occurrence of the slip is prevented. As a concrete method of such a prevention method, generally, a memory having a capacity of 2 frames is applied, the period of the write phase and the read phase is set to 2 frames, and one of the write phase and the read phase is applied. 2), two phases having different phases by one frame are prepared, and when the writing phase and the reading phase are close to each other, the writing phase or the reading phase having the two phases is switched to one having a different phase by one frame.

[0006]

However, according to the above-mentioned conventional method, in order to prevent frequent occurrence of slip, a memory having a capacity of 2 frames must be applied. Recently, the amount of data per frame tends to increase, and the increase in the memory capacity actually increases the number of memory integrated circuits and their peripheral circuits, resulting in a large circuit size. It is complicated.

Further, since one of the write phase and the read phase is provided with two phases that differ by only one frame, the entire apparatus is large and complicated in this respect as well.

Furthermore, when one of the phases is forcibly switched to a different phase by one frame, one slip always occurs. At this time, the amount of data loss and the amount of additional data due to slipping are a large amount of data corresponding to one frame, which greatly reduces the transmission quality.

The present invention has been made in consideration of the above points, and it is possible to reduce the memory capacity of the entire circuit and to eliminate the need for a configuration in which one access phase differs by one frame. It is an object of the present invention to provide a frame phase synchronization circuit that can almost completely eliminate the occurrence.

[0010]

In order to solve such a problem, according to the present invention, transmission from an input system is performed according to a write address generated by a write address generating unit based on an input system frame pulse and an input system clock. The signal is written to the elastic store memory, and the transmission signal stored in the elastic store memory is read and input according to the read address generated by the read address generator based on the capture system frame pulse and the capture system clock. A frame phase synchronization circuit for performing frame synchronization and clock transfer of the system and the capture system is as follows.

That is, as the elastic store memory, one having a capacity of one frame is applied, and the transmission signal from the input system is variably phase-shifted and given to the elastic store memory. The first variable phase shift means, in which the phase shiftable range is determined according to the amount of phase variation with respect to the clock, and the phase shiftable range in which the input system frame pulse is variably phase-shifted and given to the write address generation section. The second variable phase shift means defined similarly to the first variable phase shift means, and the relationship between the write phase and the read phase for the elastic store memory are detected to detect the first and second variable phase shift means. And a phase shift amount control means for determining a common phase shift amount of the means.

Here, each of the first and second variable phase shift means is composed of a shift register for serial-parallel conversion and a selector for selecting one output from the parallel output of the shift register. Is a preferred embodiment.

Further, each of the first and second variable phase shift means forms an even number of signals which differ from the input signal by an integer multiple of a predetermined phase difference, and an even number of shift registers from the shift register. It is another preferable aspect that it is configured by a selector that selects one of the phase-shifted input signal and the phase-shifted input signal.

[0014]

According to the present invention, the transmission signal from the input system is written into the elastic store memory in accordance with the write address formed by the write address generating unit based on the input system frame pulse and the input system clock, and at the same time, the capture system is used. A frame in which the transmission signal stored in the elastic store memory is read according to the read address generated by the read address generator based on the frame pulse and the acquisition system clock, and frame synchronization and clock transfer between the input system and the acquisition system are performed. A phase-locked circuit is assumed.

The reason why the memory capacity is increased in the conventional circuit is that the phase variation amount of the input system clock with respect to the acquisition system clock is not used for controlling the phase difference between the write phase and the read phase. This led to the present invention.

That is, in the present invention, the elastic store memory having a capacity of one frame is applied, but the phase shiftable range is determined according to the amount of phase fluctuation of the input system clock with respect to the system clock. The first and second variable phase shift means for shifting the input system transmission signal and the frame pulse are provided, and the capacity is controlled by the variable phase shift control by the phase shift amount control means even if the write phase and the read phase are close to each other. Prevented slip even with a small memory.

The first and second variable phase shift means can be easily and easily constituted by a shift register for serial-parallel conversion and a selector for selecting one output from the parallel outputs of the shift register.

Further, the first and second variable phase shift means include a shift register that forms an even number of signals that differ by an integer multiple of a predetermined phase difference from the input signal, and an even number of shift registers from the shift register. It can also be easily and simply configured by a selector that selects one of the input signals that have been phased and the input signal that has not been phase-shifted.

[0019]

【Example】

(A) First Embodiment Hereinafter, a first embodiment of the frame phase synchronizing circuit (frame aligner) according to the present invention will be described in detail with reference to the drawings.
Here, FIG. 1 is a block diagram showing the configuration of the first embodiment.

In the first embodiment, the transmission signal input system is the transmission line system, and the transmission signal acquisition system is the intra-station device system.

In FIG. 1, the frame phase synchronizing circuit according to the first embodiment is provided with two shift registers 1 and 2, two selectors 3 and 4, a shift amount control section 5, a write address generation section (write operation). The address counter) 6, the frame memory 7, and the read address generator (read address counter) 8 are included.

A transmission line input signal and a transmission line clock are given to the shift register 1, and the shift register 1 takes in the transmission line input signal based on the transmission line clock and sequentially shifts the transmission line input signals taken in the past. Let On the other hand, the shift register 2 has a transmission line frame pulse (1 bit in 1 frame is significant and the other bits are insignificant)
And the transmission line clock, the shift register 2
The transmission path frame pulse is captured based on the transmission path clock, and the transmission path frame pulses captured in the past are sequentially shifted.

The transmission path input signal may be a bit data string or a data string in units of a plurality of bits such as octets.

Here, the number of stages (2n + 1 stages) of each shift register 1, 2 is determined by the amount of phase fluctuation between the transmission line clock system and the intra-station clock system. That is, the amount of phase fluctuation of the transmission path clock due to wander (long cycle phase fluctuation), jitter (short cycle phase fluctuation), etc. (maximum allowable value, average value, etc.) when the internal clock is used as a reference
Is converted into the number of clock bits to be n bits, the shift registers 1 and 2 are selected in 2n + 1 stages.

The shift register 1 outputs 2n + 1 transmission path input signal data stored internally to the selector 3 in parallel every time a transmission path clock is applied. On the other hand, the shift register 2 outputs 2 bits each time the transmission path clock is applied.
The internally stored transmission path frame pulse is output to the selector 4 as an n + 1-bit parallel signal. Further, the bit value of the (n + 1) th stage of the shift register 2 (which is a transmission path frame pulse shifted by a reference shift amount as described later) is supplied to the shift amount control unit 5. There is.

In addition to this bit value, the shift amount control unit 5 is supplied with the transmission path clock and the read address output from the read address generation unit 8. Shift amount control unit 5
Captures the relationship between the write phase and the read phase in the frame memory 7 from the bit value from the shift register 2 (representing whether it is the head of a frame) and the read address, and selects two selectors 3 and 4. A common selection control signal (which becomes a shift amount control signal as described later) and outputs it to the two selectors 3 and 4. The method of forming this selection control signal will be described in detail later.

The selector 3 has a 2n input in parallel.
From the +1 transmission path input signal data, one transmission path input signal data indicated by the selection control signal is selected and output to the data input terminal of the frame memory 7. Selector 4
From the 2n + 1-bit transmission line frame pulse input in parallel, 1 bit designated by the selection control signal is selected and output to the write address generation unit 6.

Therefore, the shift register 1 and the selector 3
Functions as a variable phase shift means for the transmission line input signal, the shift amount (shift amount) of which is controlled by the shift amount control unit 5. Also, the shift register 2 and the selector 4 are
The shift amount control unit 5 controls the amount of phase shift (shift amount), and functions as a variable phase shift unit for the transmission path frame pulse.

When the bit data string (transmission path frame pulse) from the selector 4 is significant (when the start position of the frame is indicated), the write address generator 6 sets the initial value as the write address. After setting (0), the write address is incremented by 1 every time the transmission path clock is applied, and the formed write address is output to the write address input terminal of the frame memory 7.

The transmission line clock is input as a write clock to the write clock input terminal of the frame memory 7. The frame memory 7 has a capacity capable of storing the transmission path input signal data for one frame, and the transmission path input signal data input at that time in the area designated by the write address at that time based on the write clock. Write in.

On the other hand, the read address generator 8 is supplied with the intra-office frame pulse and the intra-office clock. The read address generator 8 sets an initial value (0) as a read address when the intra-office frame pulse is significant (when indicating the start position of the frame), and thereafter, the intra-station clock is given. The read address is incremented by 1 each time, and the formed read address is output to the read address input terminal of the frame memory 7. The read address is also given to the shift amount control section 5, as described above.

The internal clock is input to the read clock input terminal of the frame memory 7 as a read clock.
Based on the read clock, the frame memory 7 outputs the transmission path input signal data stored in the area designated by the read address at that time as an in-station input signal.

Also in this first embodiment, the transmission path input signal data is written in the memory (frame memory 7) and read from the memory, so that the data is transferred from the transmission path clock to the in-station clock and at the transmission destination in the station. It is synchronized with the frame phase of the device.

However, the structure for preventing frequent occurrence of slips due to the approach of the write phase and the read phase is different from the conventional one. That is, as described above, the variable phase shift means including the shift register 1 and the selector 3, the variable phase shift means including the shift register 2 and the selector 4, and the shift amount control unit for controlling the amount of phase shift (shift amount). The writing phase is shifted by 5.

The operation of the write phase shift structure, which is a characteristic structure of the frame phase synchronizing circuit of the first embodiment, will be described in detail below. The description of such an operation will be given focusing on the control method of the shift amount control unit 5. The operation of the frame phase synchronization circuit at the time of initial setting and the operation of the frame phase synchronization circuit in the steady state will be described in this order.

At the time of initial setting, the shift amount control section 5 first detects how different the writing phase and the reading phase with respect to the frame memory 7 are at that time. That is, when the bit value of the (n + 1) th stage (center) from the shift register 2 is the frame pulse bit,
The read address p from the read address generator 8 is detected. This value p represents the phase difference between the leading read address and the leading write address when the shift amount is the reference shift amount (n + 1 clock periods).

Here, the address range of the frame memory 7 is 0 to m, and the address generation units 6 and 8 are at timings when the transmission path frame pulse and the intra-office frame pulse are significant.
Generates 0 as an address, and prohibits writing when the leading write address (0) falls within this range when the read address is within addresses m-r to m, 0-r. And

The shift amount control section 5 determines the common shift amount Q of the input transmission path input signal and transmission path frame pulse based on the detected read address value p, and accordingly the selected input of the selectors 3 and 4. Determine the terminals as follows.

(1) In the case of r <p <m−r (when the head write address at the reference shift amount is outside the write prohibited range) In this case, the shift amount Q is set to n + 1. That is,
The values of the central stage (n + 1 stages) of the shift registers 1 and 2 are selected by the selectors 3 and 4. By doing so, when the read address is a value p outside the write-inhibited range, a significant transmission path frame pulse is input to the write address generation unit 6, and the write address becomes 0 at this timing. Become.

(2) In the case of 0≤p≤r (when the head write address at the reference shift amount is within the write prohibited range and the head write address occurs immediately after the head read address occurs) , The shift amount Q is (n + 1) + (r−p +
1) Set to + α. By doing so, when the read address is the value r + 1 + α outside the write prohibited range, a significant transmission path frame pulse is input to the write address generation unit 6, and the write address becomes 0 at this timing. Become. Here, α gives an offset (margin) of the leading write address from the write-prohibited range, and may be 0 or more, preferably about 10 in practice.

(3) In the case of m-r≤p≤m (when the head write address at the reference shift amount is within the write prohibited range and the head read address occurs immediately after the head write address occurs) In this case, the shift amount Q is (n + 1)-(p-m + r
+1) -β. By doing so, when the read address is a value m-r-1-β outside the write-prohibited range, a significant transmission path frame pulse is input to the write address generation unit 6, and the write address is generated. Becomes 0 at this timing. Here, β gives an offset (margin) of the leading write address from the write-prohibited range, may be 0 or more, and is preferably about 10 in practice.

As described above, at the time of initial setting, if the start write address is outside the write-prohibited range on the assumption that the reference shift amount (n + 1 clock periods) is applied, that shift amount is adopted. If the start write address is within the write-prohibited range on the assumption that the reference shift amount is applied, the shift amount is selected so that the start write-address is outside the write-prohibited range.

FIG. 2 is a timing chart of each part at the time of initial setting, showing the above-mentioned case (2) in which the offset α is 0.

That is, the read address value p when the transmission path frame pulse shown in FIG. 2B shifted by the reference shift amount becomes significant, as shown in FIG. If it is within the range, the shift amount control unit 5 initializes the value (n + 1) + (r-p + 1) as the shift amount Q. As shown in FIG. 2C, this shift amount is larger than the reference shift amount by r−p + 1, and the significant timing of the shifted transmission path frame pulse (timing of the leading write address) is the write prohibited range. Outside, the transmission path input signal data D1, D2, D3, ... Synchronized with the shifted transmission path frame pulse are input to the frame memory 7 as shown in FIG. 2 (d).

In the steady state after the above initial setting operation is completed, the shift amount control section 5 operates as follows.
Shift amount of transmission line input signal and transmission line frame pulse,
Therefore, the writing phase for the frame memory 7 is controlled.

In the first embodiment, the shift amount control unit 5 executes the same shift amount control ((1) to (3)) as in the initial setting even in such a steady state operation.

That is, when the leading write address at the reference shift amount (n + 1 clock cycles) is outside the write-inhibited range, in other words, n from the shift register 2 is reached.
If the read address at the timing when the + 1st stage transmission path frame pulse becomes significant is outside the write-prohibited range,
The reference shift amount is selected as the shift amount Q.

If the head write address at the reference shift amount is within the write prohibited range and the head write address occurs immediately after the head read address occurs, the shift amount Q is (n + 1) + ( r−p + 1) + α so that the leading write address is generated when the read address is the value r + 1 + α which is outside the write prohibited range.

Further, when the leading write address at the reference shift amount is within the write prohibited range and the leading read address occurs immediately after the leading write address occurs, the shift amount Q
Is set to (n + 1)-(p-m + r + 1) -β so that the head write address is generated when the read address is the value m-r-1-β outside the write-prohibited range.

FIG. 3 is a timing chart of each part when the transmission line clock system has a phase fluctuation that tends to lead the internal system clock system. Note that, in FIG. 3, the timing chart of three consecutive s-th, s + 1-th, and s + 2-th frames is shown with the read address time axis being the same for the three frames. That is, FIGS. 3B and 3C relate to the time axis one frame before FIGS. 3D to 3F, and FIGS. 3D to 3F are shown in FIGS. )
Regarding the time axis one frame before.

Here, the reference shift amount (n + 1 clock cycle) is selected as the shift amount up to the s-1th frame, and the significant timing of the transmission line frame pulse of the (n + 1) th stage is also written in the sth frame. It is assumed that the error occurs outside the inclusion prohibition range (FIG. 3B). In this case, the shift amount control unit 5 continues to select the reference shift amount as the shift amount Q, and the transmission path frame pulse (phase shifted by the reference shift amount from the transmission path frame pulse input from the selector 4 ( Although not shown, the same as in FIG. 3B is output,
The transmission line input signal synchronized with this is input to the frame memory 7 (FIG. 3C).

The phase variation of the transmission line clock causes the s-th
In the +1 frame, it is assumed that the significant timing of the n + 1th stage transmission path frame pulse occurs within the write-inhibited range and the read address p2 at that time is 0 ≦ p2 ≦ r (FIG. 3 (d)). In this case, the shift amount control unit 5
The shift amount Q is changed from the reference shift amount n + 1 to (n + 1) + (r
-P + 1) + α (shown as α = 0 in FIG. 3). The shift amount Q is changed from the clock cycle next to the timing when the transmission path frame pulse at the (n + 1) th stage becomes significant. Therefore, from the selector 4,
As shown in FIG. 3E, a significant transmission path frame pulse is generated before and after the switching, and as shown in FIG. The transmission line input signal is input, and after the second significant timing, the transmission line input signal of the frame is input. An invalid transmission line input signal is written in the frame memory 7 between such two significant timings, but the correct transmission line input signal is overwritten after the second significant timing, and the correct intra-station input is made from the frame memory 7. The signal is read (though there is a possibility that an incorrect signal may be read due to the change in the shift amount).

After the (s + 1) th frame to the (s + 2) th frame, it is assumed that the transmission path clock has no phase fluctuation with respect to the in-station device clock. In this case, the significant timing of the n + 1th stage transmission path frame pulse is as shown in FIG.
As shown in (g), the timing becomes the same as that of the (s + 1) th frame with respect to the write-inhibited range, and the shift amount control unit 5 maintains the same shift amount. As a result, the significant timing of the transmission path frame pulse from the selector 4 also becomes the same as the timing immediately before, as shown in FIG. 3 (h), and the transmission path input signal to the frame memory 7 also changes to that shown in FIG. 3 (i). As shown, there will be no missing or added sequences.

FIG. 4 shows a timing chart of each part in the case where the transmission line clock system has a phase fluctuation that tends to be delayed from the in-station device clock system. Also in FIG. 4, the timing chart of three consecutive s-th, s + 1-th, and s + 2-th frames is shown assuming that the read address time axes are the same for the three frames.

Here, the reference shift amount (n + 1 clock cycle) is selected as the shift amount up to the s-1th frame, and the significant timing of the transmission line frame pulse of the (n + 1) th stage is also written in the sth frame. It is assumed that the error occurs outside the prohibited range (FIG. 4B). In this case, the shift amount control unit 5 continues to select the reference shift amount as the shift amount Q, and the transmission path frame pulse (phase shifted by the reference shift amount from the transmission path frame pulse input from the selector 4 ( Although not shown, the same as in FIG. 4B is output,
A transmission line input signal synchronized with this is input to the frame memory 7 (FIG. 4 (c)).

The phase fluctuation of the transmission line clock causes the s-th
In the +1 frame, it is assumed that the significant timing of the n + 1th stage transmission path frame pulse occurs within the write-prohibited range and the read address p2 at that time is m−r ≦ p4 ≦ m (FIG. 4 (d)). In this case, the shift amount control unit 5
Shifts the shift amount Q from the reference shift amount n + 1 to (n + 1) −
(P−m + r + 1) −β (shown as β = 0 in FIG. 4)
Change to. The shift amount Q is changed from the clock cycle next to the timing when the transmission path frame pulse at the (n + 1) th stage becomes significant. Therefore, selector 4
4E, a significant transmission path frame pulse is generated only before the switching, as shown in FIG. 4E, and as shown in FIG. 4F, the shift amount is changed in the frame memory 7 immediately after the switching. The transmission line input signal of the future is input by that much (thus, some transmission line input signals are lost).

After the s + 1th frame to the s + 2th frame, it is assumed that the transmission path clock has no phase fluctuation with respect to the in-station device clock. In this case, the significant timing of the n + 1th stage transmission path frame pulse is as shown in FIG.
As shown in (g), although it is within the write-prohibited range as in the (s + 1) th frame, the shift amount control unit 5 maintains the same shift amount because the timing is the same as that of the write-prohibited range. As a result, the significant timing of the transmission path frame pulse from the selector 4 is outside the write prohibited range as shown in FIG. 4 (h), and the transmission path input signal to the frame memory 7 is shown in FIG. 4 (i). As such, there will be no omissions or additions, which will be continuous.

Therefore, according to the first embodiment, the memory required for the frame phase synchronization processing may have a capacity of one frame, and the structure can be made smaller and simpler than the conventional one. Although a shift register is required, even if the transmission path input signal is in units of 8 bits, the required capacity is actually about 1/10 of one frame capacity.
The above effects can be obtained. In practice, this frame phase synchronization circuit is realized alone or together with other devices on one integrated circuit, but the area occupied by the device on the integrated circuit can be made small.

Further, according to the first embodiment, since the shift register having the number of stages considering the amount of phase fluctuation is provided, the writing phase and the reading phase are reversed even if the writing phase is changed ( Slip is unlikely to occur. When the shift amount (phase shift amount) is changed, the data of the transmission path input signal may be dropped or added, but unlike the conventional case, about one frame of data is not dropped or added, The communication quality can be improved as compared with the conventional one.

Further, according to the first embodiment, the operation of the shift amount control unit 5 can be made the same in both the initial setting and the steady state, and the configuration of the shift amount control unit 5 can be simplified. By the way, conventionally, it is necessary to determine which of the write addresses by the two write address generators is appropriate in the initial setting, and in the steady state, the relationship between the selected write address and the read address is monitored. Therefore, separate configurations are required for the initial setting and the steady state.

(B) Second Embodiment Next, a second embodiment of the frame phase synchronizing circuit (frame aligner) according to the present invention will be described in detail with reference to the drawings.
Here, FIG. 5 is a block diagram showing the configuration of the second embodiment. Also in this second embodiment, it is assumed that the transmission signal input system is the transmission path system and the transmission signal acquisition system is the intra-station device system.

In the following description of the second embodiment,
Although some of the same reference numerals as those in the first embodiment are used as the reference numerals other than the configuration, such as the states and the numbers, they do not mean the same ones. However, the configuration will be described using the same reference numerals as those of the first embodiment and corresponding portions.

In FIG. 5, the frame phase synchronizing circuit of the second embodiment also has two shift registers 1 and 2, two selectors 3 and 4, a shift amount control section 5, as in the first embodiment. Write address generator (write address counter)
6, a frame memory 7, and a read address generator (read address counter) 8.

That is, also in the frame phase synchronizing circuit of the second embodiment, the transmission line input signal data is written in the frame memory 7 and read out from the frame memory 7 to transfer the data from the transmission line clock to the in-station clock. At the same time, it synchronizes with the frame phase of the in-office device of the transmission destination. Further, in order to prevent frequent occurrence of slips due to the approach of the write phase and the read phase, the variable phase shift means including the shift register 1 and the selector 3, the variable phase shift means including the shift register 2 and the selector 4, and the shift thereof. The write phase is shifted by the shift amount control unit 5 that controls the phase amount (shift amount).

However, the components for shifting the write phase, that is, the shift registers 1 and 2, the selectors 3 and 4, and the shift amount controller 5 are slightly different from those in the first embodiment. Therefore, the following description will be focused on the differences from the first embodiment, and the description of the write address generation unit 6, frame memory 7, and read address generation unit 8 that are the same as in the first embodiment will be omitted. .

The shift register 1 of the second embodiment also takes in the transmission line input signal based on the transmission line clock, and sequentially shifts the transmission line input signals previously fetched, while the shift register 2 also. The transmission path frame pulse is fetched based on the transmission path clock, and the transmission path frame pulses fetched in the past are sequentially shifted.

However, each of the shift registers 1 and 2 of the second embodiment has a stage number of 2n (n is the number of clock bits, which is the amount of phase fluctuation of the transmission path clock due to the wander when the in-station clock is used as a reference). Converted value)
The output signal from the n-th stage is given to the corresponding selectors 3 and 4 as the second input signal (2), and 2n
The output signal from the stage is given to the corresponding selectors 3 and 4 as the third input signal (3).

Each of the selectors 3 and 4 of the second embodiment selects from three input signals according to a selection control signal common to both selectors.

As described above, the selector 3 transmits to the selector 3 the transmission line input signal (hereinafter,
An n-stage transmission line input signal) and a 2n-stage shifted transmission line input signal (hereinafter, referred to as 2n-stage transmission line input signal) are given as second and third selection input signals (2) and (3). At the same time, the transmission line input signal input to the shift register 1 (hereinafter, referred to as 0-stage transmission line input signal if necessary) is given as the first selection input signal (1), and the shift amount control unit 5 outputs it. In accordance with the selection control signal of, the selection input signal (1), (2) or (3) is selected and output to the data input terminal of the frame memory 7.

On the other hand, in the selector 4, as described above, the transmission path frame pulse shifted from the shift register 2 by n stages (hereinafter referred to as n-stage transmission path frame pulse), 2n.
The transmission line frame pulse that has been stage-shifted (hereinafter referred to as 2n-stage transmission line frame pulse) is given as the second and third selection input signals (2) and (3) and is input to the shift register 2. Road frame pulse (hereinafter,
The 0-stage transmission path frame pulse is the first if necessary)
Selected input signal (1), (2) or (3) according to the selection control signal from the shift amount control section 5 to generate a write address. It is output to the unit 6 as a reset signal.

Therefore, also in the second embodiment, although the number of stages of the amount of phase shift that can be taken is small, the shift register 1 and the selector 3 constitute variable phase shift means of the transmission line input signal, and the shift register 2 and The selector 4 constitutes a variable phase shifter for the transmission path frame pulse.

In the shift amount control section 5 of the second embodiment, the n-stage transmission line frame output from the shift register 2 is used as a signal for determining the phase shift amount of the transmission line input signal and the transmission line frame pulse. The pulse and the 2n-stage transmission line frame pulse, the 0-stage transmission line frame pulse input to the shift register 2, and the intra-station frame pulse are input.
The shift amount control unit 5 has a phase difference relationship between these three transmission path frame pulses each having a phase difference corresponding to n stages of the shift register 2 and the intra-office frame pulse (in other words, the writing phase of the frame memory 7 and Read phase relationship)
As described later, the phase shift amounts of the transmission path input signal and the transmission path frame pulse are determined, and the transmission path input signal and the transmission path frame pulse related to the determined phase shift amount are selected by the selectors 3 and 4. Thus, the selection control signal is formed.

The control method of the shift amount control section 5 of the second embodiment will be described below with reference to FIGS. 6 and 7. FIG. 6 is a timing chart showing the phase relationship of four types of frame pulses input to the shift amount control unit 5. FIG. 7 is a state transition diagram showing transition of control states of the shift amount control unit 5.

The shift amount control unit 5 reviews the selection control signal supplied to the selectors 3 and 4 at the timing of the significant pulse period (period of logic "H" in FIG. 6) of each frame pulse.

The shift amount control section 5, when the intra-office frame pulse shown in FIG.
This significant pulse period x is one of the following time regions A defined by three transmission path frame pulses having different phases,
The control state is appropriately changed depending on whether it is in B or C. The time domain A is shown in FIG. 6 from the leading edge of the significant pulse period Y of the 0-stage transmission line frame pulse shown in FIG.
It is a period until the leading edge of the significant pulse period X of the n-stage transmission path frame pulse shown in (b). The time domain B is shown in FIG. 6C from the leading edge of the significant pulse period X of the n-stage transmission line frame pulse shown in FIG. 6B.
Significant pulse period Z of 2n-stage transmission line frame pulse shown in
It is the period until the leading edge of. Time domain C
From the leading edge of the significant pulse period Z of the 2n-stage transmission line frame pulse shown in FIG.
It is a period up to the leading edge of the significant pulse period Y of the 0-stage transmission path frame pulse shown in FIG.

Further, the shift amount control section 5 is shown in FIG.
When any of the transmission path frame pulses shown in (c) becomes a significant pulse period Y, X, or Z, the significant pulse period Y, X, or Z is any one of the following time regions a determined by the intra-office frame pulse: Alternatively, the control state is appropriately changed depending on whether it is in b. The time domain a is a period with some significant periods added before and after the significant pulse period x of the intra-office frame pulse shown in FIG. 6D, and this time domain a is based on the transmission line frame pulse. This is a write prohibited area that prohibits setting the write address to the initial value (0). For example, the time region a relating to the significant pulse period of the next in-station frame pulse is determined based on the significant pulse period of the previous in-station frame pulse. The time domain b is a period other than the time domain a within the time domain determined by the intra-office frame pulse shown in FIG. 6D, and this time domain b is
This is an area that allows the write address to be set to the initial value (0) based on the transmission path frame pulse.

In the case of the second embodiment, as described above,
There are three types of phase candidates for the transmission path input signal and the transmission path frame pulse (transmission path input signal and transmission path frame pulse for 0, n, and 2n stages). As shown in FIG. 7, five types S0, S01,
S02, S1 and S2 are prepared. The state SI
Indicates an indefinite state immediately after power-on of the device including the frame phase synchronization circuit.

The shift amount control section 5 transmits n stages of intermediate phases among the three types of phase candidates so that it can cope with both the lead phase change and the lag phase change of the transmission path frame pulse with respect to the intra-office frame pulse. The channel input signal and the n-stage transmission path frame pulse are basically selected by the selectors 3 and 4. However, there are three types of control states S0, S01 and S for controlling the n-stage transmission line input signal and the n-stage transmission line frame pulse by the selectors 3 and 4 as described above.
It is divided into 02.

The control state S0 is a control state in which the n-stage transmission line input signal and the n-stage transmission line frame pulse are selected in a state where the phase difference between the n-stage transmission line frame pulse and the intra-office frame pulse is sufficiently large. . The control state S01 is n
The intra-office frame pulse becomes significant after a slight delay from the significant time of the stage transmission path frame pulse, but the phase difference is such that the selection of the n stage transmission path input signal and the n stage transmission path frame pulse is still acceptable. It is in a certain state. The control state S02 is a state in which the n-stage transmission path frame pulse becomes significant with a slight delay from the significant point of the intra-office frame pulse, but the phase difference is the selection of the n-stage transmission path input signal and the n-stage transmission path frame pulse. Is still acceptable.

The control state S1 is a control state in which the 0th stage transmission line input signal and the 0th stage transmission line frame pulse are selected. The control state S2 is 2n stage transmission line input signal and 2n
This is a control state in which the stage transmission path frame pulse is selected.

As shown in the state transition diagram of FIG. 7, the shift amount control unit 5 is in the control state (thus, the selection state of the transmission line input signal and the transmission line frame pulse given to the frame memory 7 and the write address generation unit 6). Transition.

Even if the state SI is just after the apparatus is started, the control operation is already performed and any one of the control states S0, S01, S02,
Regardless of S1 or S2, a reset signal RS not shown
When T is given, the basic control state S0 is set.

In this basic control state S0, the control state is switched based on only in which time region A, B, C the significant pulse period x of the intra-office frame pulse is.

When the significant pulse period x of the intra-office frame pulse is in the time region C, the phase difference between the n-stage transmission path frame pulse and the intra-office frame pulse continues to be sufficiently large, so this control state Continue S0. When the significant pulse period x of the intra-office frame pulse is in the time region B, it is necessary to be careful that the intra-office frame pulse becomes significant with a slight delay from the n-stage transmission path frame pulse. A transition is made to the control state S01 for attention, in which selection of the input signal and the n-stage transmission path frame pulse can be continued. When the significant pulse period x of the intra-station frame pulse is in the time region A, it is necessary to take care that the n-stage transmission line frame pulse becomes significant after a slight delay from the intra-station frame pulse. The state transits to the control state S02 for attention, in which the selection of the input signal and the n-stage transmission path frame pulse can be continued.

In the control state S01, the control state is switched based on which time region A, B, C the significant pulse period x of the intra-office frame pulse is, and the significance of the currently selected n-stage transmission line frame pulse is set. The control state is switched based on which time region a or b the pulse period X is in.

When the significant pulse period x of the intra-office frame pulse is in the time region C, the state in which the phase difference between the n-stage transmission path frame pulse and the intra-office frame pulse is sufficiently large has been restored, so the control state S0 is entered. To do. When the significant pulse period x of the intra-station frame pulse is in the time region B and when the significant pulse period X of the n-stage transmission line frame pulse is in the time region b, the n-stage transmission line frame pulse and the intra-station frame pulse are Since the phase difference of is the same as the previous state, the control state S01 is continued. When the significant pulse period x of the intra-station frame pulse is in the time domain A,
Since the n-stage transmission line frame pulse becomes significant after a slight delay from the intra-office frame pulse, and another caution is required, it is possible to continue selecting the n-stage transmission line input signal and the n-stage transmission line frame pulse. Transition to another control state S02 for use with. Significant pulse period X of n-stage transmission line frame pulse
Is in the time domain a, the phase difference between the currently selected n-stage transmission path frame pulse and the intra-office frame pulse is almost zero.
Therefore, if this state is continued and slips frequently occur, the control state S1 for selecting the 0th stage transmission line input signal and the 0th stage transmission line frame pulse that can secure the phase difference even if the phase change so far is taken into consideration. Transition to. In this case,
One slip occurs.

Also in the control state S02, the control state is switched based on which time region A, B, or C the significant pulse period x of the intra-office frame pulse is, and the significance of the n-stage transmission path frame pulse currently selected is significant. The control state is switched based on which time region a or b the pulse period X is in.

When the significant pulse period x of the intra-office frame pulse is in the time region C, the state in which the phase difference between the n-stage transmission path frame pulse and the intra-office frame pulse is sufficiently large has been restored, so the control state S0 is entered. To do. When the significant pulse period x of the intra-office frame pulse is in the time region A and when the significant pulse period X of the n-stage transmission line frame pulse is in the time region b, the n-stage transmission line frame pulse and the intra-station frame pulse are Since the phase difference of is the same as the previous state, the control state S02 is continued. When the significant pulse period x of the intra-office frame pulse is in the time domain B,
Note that the intra-station frame pulse becomes significant after a slight delay from the n-stage transmission line frame pulse, and another caution is required, so that the selection of the n-stage transmission line input signal and the n-stage transmission line frame pulse can be continued. Transitions to another control state S01 for use with. Significant pulse period X of n-stage transmission line frame pulse
Is in the time domain a, the phase difference between the currently selected n-stage transmission path frame pulse and the intra-office frame pulse is almost zero.
Therefore, if this state is continued and slips occur frequently, a phase difference can be secured even if the phase change so far is taken into consideration. A control state S2 for selecting the 2n-stage transmission line input signal and the 2n-stage transmission line frame pulse. Transition to. In this case, the slip occurs once.

In the control state S1, the significant pulse period Y of the currently selected 0th stage transmission line frame pulse is a time region a.
Alternatively, the control state is switched based only on whether or not it is in b.

When the significant pulse period Y of the 0-stage transmission line frame pulse is in the time region b, the phase difference between the currently selected 0-stage transmission line frame pulse and the intra-office frame pulse is
The control state S1 is continued because the frame memory 7 is secured to the extent that it does not malfunction. When the significant pulse period Y of the 0-stage transmission path frame pulse is in the time region a, the phase difference between the currently selected 0-stage transmission path frame pulse and the intra-office frame pulse is almost 0, so the phase difference is secured. Control state S1 to suppress frequent occurrence of slip
Transition to the control state S01 before the transition to. In this case, the slip occurs once.

In the control state S2, the control state is switched only based on which time region a or b the significant pulse period Z of the currently selected 2n-stage transmission path frame pulse is.

When the significant pulse period Z of the 2n-stage transmission line frame pulse is in the time domain b, the 2n currently selected
Since the phase difference between the stage transmission path frame pulse and the intra-office frame pulse can be ensured to the extent that the frame memory 7 does not malfunction, the control state S2 is continued. When the significant pulse period Z of the 2n-stage transmission line frame pulse is in the time region a, the phase difference between the currently selected 2n-stage transmission line frame pulse and the intra-office frame pulse is almost 0, so the phase difference is secured. In order to suppress the frequent occurrence of slip, the control state S02 is changed to the control state S02 before the change to the control state S2. In this case, the slip occurs once.

In FIG. 8, the significant pulse interval of the transmission path frame pulses is relatively shorter than the significant pulse interval of the transmission path frame pulses, and the shift amount control unit 5 changes the control state from S02 to S2. The transmission path frame pulse and the intra-station frame pulse are shown in the case of changing to.
As is clear from FIG. 8, the control states are changed from S02 to S.
When the mode is switched to 2, the slip occurs once and the data of the transmission path input signal for n clocks is lost, but thereafter, the state shifts to a stable state again.

Therefore, according to the second embodiment as well, (1) the memory required for the frame phase synchronization processing may have a capacity of one frame, and the configuration can be made smaller and simpler than before. (2) shift Since the number of stages is set as the register in consideration of the amount of phase fluctuation, even if the write phase is changed, the write phase and the read phase do not reverse (slip), and the shift amount (phase shift amount) does not occur. Even if the value is changed, the data for about one frame is not lost or added, and the communication quality can be improved as compared with the conventional one. (3) The shift amount control unit 5 can be set in the initial setting and in the steady state. It is possible to obtain the effect that the operation can be made the same and the configuration of the shift amount control unit 5 can be simplified.

Further, according to the second embodiment, the selectors 3,
Since there are three types of selection candidates in 4, the frame phase synchronizing circuit can be made smaller than in the first embodiment.

(C) Other Embodiments In the first embodiment, the n + 1th stage transmission path frame pulse of the shift register 2 is input to the shift amount control section 5 to change the write phase and the read phase. However, the input transmission line frame pulse which is not shifted at all is directly input to the shift amount control unit 5, and the significant timing of the transmission line frame pulse at the reference shift amount is estimated to shift. The amount may be determined. By doing so, even when the shift amount is advanced and changed to the phase side (see FIG. 4), the phase shift processing can be completed in that frame.

In the second embodiment, the shift amount control section 5 receives three types of transmission path frame pulses having different phase differences to capture the relationship between the write phase and the read phase. However, any one type of transmission path frame pulse (for example, n-stage transmission path frame pulse) may be input to the shift amount control unit 5 for control operation. Since the phase difference from other transmission line frame pulses is fixed, the control operation can be executed in this way as well.

Further, in the above-mentioned first and second embodiments, the transmission path frame pulse input to the shift amount control section 5 for determining the shift amount is shown before passing through the selector 4. The transmission path frame pulse after passing may be used.

Furthermore, in the first embodiment,
It has been shown that the shift amount is changed each time the significant timing of the transmission line frame pulse (n + 1th stage transmission line frame pulse) at the reference shift amount is changed within the write-prohibited range. Even if the amount is maintained, the shift amount may not be changed when the significant timing of the transmission path frame pulse from the selector 4 is outside the write-inhibit range. By doing so, the number of times the shift amount is changed can be reduced.

Further, in the second embodiment, the case where the number of phase shift amount candidates is 3 has been shown, but it may be an odd number of 5 or more, and the reference shift amount is in the middle of the phase shift possible range. However, it may be an even number of four or more.

Further, in the first and second embodiments, the wander tendency is not used for the shift amount control, but the past read address value at the significant timing of the transmission path frame pulse at the reference shift amount is shown. The shift amount may be determined by accumulating the wander tendency and using this information as well. For example, in the first embodiment, the values of the shift amount offsets α and β may be changed according to the wonder tendency. Further, for example, in the second embodiment, the control states S01 and S02 may be transited to the control states S1 and S2, and which transition may be determined depending on the wonder tendency.

Furthermore, in the above-mentioned first and second embodiments, the transmission path system is the transmission signal input system and the intra-station device system is the transmission signal acquisition system. ,
The present invention can be applied. Also in this case, it is preferable to perform variable phase shift control on the intra-station input signal and the intra-station frame pulse of the transmission signal input system.

Incidentally, it is conceivable to perform variable phase shift control on the signal on the side of the transmission signal acquisition system, but in the case of the frame phase synchronizing circuit, since the transmission signal acquisition system side becomes the reference, Manipulating the signals is not a practical way because the standards are disturbed.

[0104]

As described above, according to the present invention, the elastic store memory having the capacity of one frame is applied, and the transmission signal from the input system is variably phase-shifted so as to be elastic store memory. And a first variable phase-shifting means for which a phase-shiftable range is determined according to the amount of phase fluctuation of the input-system clock with respect to the acquisition-system clock, and the input-system frame pulse is variably phase-shifted to generate a write address. Detecting the relationship between the second variable phase shift means for which the phase shiftable range given to the section is determined in the same manner as the first variable phase shift means, and the write phase and the read phase for the elastic store memory. , And the phase shift amount control means for determining the common phase shift amount of the first and second variable phase shift means, the memory capacity of the entire circuit can be reduced and one access phase differs by one frame. Unnecessary configuration for generating shall be realized frame phase synchronization circuit can be eliminated almost the occurrence of slip.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment.

FIG. 2 is a timing chart of each part at the time of initial setting in the first embodiment.

FIG. 3 is a timing chart (No. 1) of each part in a steady state according to the first embodiment.

FIG. 4 is a timing chart (No. 2) of each part in a steady state according to the first embodiment.

FIG. 5 is a block diagram showing a configuration of a second embodiment.

FIG. 6 is a timing chart for explaining a control method of a shift amount control unit of the second embodiment.

FIG. 7 is a state transition diagram of a control state of a shift amount control unit of the second embodiment.

FIG. 8 is a timing chart of each part in a steady state according to the second embodiment.

[Explanation of symbols]

1, 2 ... Shift register, 3, 4 ... Selector, 5 ... Shift amount control unit, 6 ... Write address generating unit, 7 ... Frame memory, 8 ... Read address generating unit.

Claims (3)

[Claims] 1. A transmission signal from an input system is written into an elastic store memory according to a write address generated by a write address generator based on an input system frame pulse and an input system clock, and a capture system frame pulse is also included. And a frame phase synchronization for reading the transmission signal stored in the elastic store memory in accordance with the read address formed by the read address generator based on the acquisition system clock and performing frame synchronization of the input system and the acquisition system and clock transfer. In the circuit, the elastic store memory having a capacity of one frame is applied, and the transmission signal from the input system is variably phase-shifted and given to the elastic store memory. The allowable range of phase shift is set according to the amount of phase fluctuation with respect to the system clock. The first variable phase shift means and the second variable phase shift means, in which the input system frame pulse is variably phase-shifted and given to the write address generating section, and the phase shiftable range is set similarly to the first variable phase shift means. And the phase shift amount control for determining the common phase shift amount of the first and second variable phase shifters by detecting the relationship between the write phase and the read phase with respect to the elastic store memory. And a frame phase synchronization circuit comprising: 2. The first and second variable phase shift means each comprises a shift register for serial-parallel conversion, and a selector for selecting one output from the parallel output from the shift register. The frame phase synchronization circuit according to claim 1. 3. A shift register, wherein each of the first and second variable phase shift means forms an even number of signals which differ from the input signal by an integral multiple of a predetermined phase difference, and an even number from the shift register. 2. The frame phase synchronizing circuit according to claim 1, further comprising a selector that selects one of the phase-shifted input signal and the phase-shifted input signal.