JPH07176577A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a time required for tests by a method wherein a sense line through which the contents of a probe point accessed by a first probe line are read is provided in the row direction of a first region and a sense line through which the contents of a probe point accessed by a second probe line are read is provided in the row direction of a second region. CONSTITUTION:A probe point 190 on the upper left side of a base array 140 are accessed independently by a sense line 120a and a probe line 130a and a probe point 190 on the upper right side of the base array 140 are accessed independently by a sense line 120b and a probe line 130b. While a sense line switch 220 is in an off-state, at the time of reading, the states of the logic circuits of the probe points 190 on the probe lines 120a and 120b which are in high states are read through the left and right sense lines 120a and 120b. At the time of reading, data which are stored in data registers 170a and 170b beforehand are transferred through the left and right sense lines 120a and 120b to the right and left probe points 190 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for writing data in a register of a logic circuit on an LSI in a matrix probing method.

[0002]

2. Description of the Related Art It is very important for product quality control to form a logic circuit having various functions on an LSI and test whether the logic circuit is operating normally. However, if the circuit is highly integrated and the circuit scale becomes very large, testing becomes very difficult. In particular, in a logic circuit including a sequential circuit, the number of states is very large, which is very troublesome. Also, the number of test points increases, many test leads are required, and the package shape becomes very large. Therefore, it is necessary to enable testing with a small number of test leads in an LSI in which a logic circuit including such a sequential circuit is formed. As one of the methods, there is a matrix probing method (for example, "JP-A-1-179338").

FIG. 3 shows an overview of an LSI chip 110 which enables a logic circuit test by the matrix probing method. On the logic circuit formed in the base array 140 of the LSI chip 110, the sense lines 120 are arranged vertically and the probe lines 130 are arranged horizontally.
Is wired.

The sense line 120 is connected to the data register 1
70 is transferred to a register on the base array 140, or the state of an internal node (probe point 190) such as a register or a test point on the base array 140 is read and the contents of the data register 170 are registered in the logic circuit 140. To transfer to. The connection between the sense line 120 and the data register 170 is
It is controlled by the sense line driver 160. The probe line 130 is for controlling the connection between the sense line 120 and the register or test point of the logic circuit 140, and is selected by the probe line driver 180. The internal node on the selected probe line 130 is read or written.

The test controller 155 controls the probe line driver 180 and the sense line driver 160 and reads and writes the contents of the data register 170. By this matrix probing method, the number of pads 150 for external connection required for the circuit under test is extremely reduced, and the number of leads of the LSI package required is reduced.

FIG. 4 shows an example of a schematic circuit near the probe point. The probe line 130 and the sense line 1 are shown in FIG.
At the intersection with 20, the NMOS sense transistor 21
5a and 5b are provided. This sense transistor 2
15a and 15b are circuit parts 142 of the logic circuit to be checked.
connected between a and b and the sense line 120,
The gate is connected to the probe line 130.
The probe lines 130 are set high one by one to make the sense transistors 215a and 215b on the probe lines 130 conductive, and the circuit portions 142a and 142b are connected to the probe lines 130.
It is designed to be sequentially connected to.

When it is desired to read the data, the states of the circuit sections 142a and 142b are held in the data register 170, and the contents of the data register 170 are compared with the expected value by the test controller 155 or output from the pad 150 to the outside. , You can check the logic circuit. When it is desired to change the content or state of the logic circuit, the test controller 155 transfers data from the outside to the data register 170 in advance, and this data is transferred from the data register 170 to the circuit portion of the logic circuit. In this way, the states of the circuit units 142a and 142b can be sequentially read or changed.

The circuit section 142a shows a case where it is desired to read the output state, and the output of the gate in the circuit section 142a is connected to the probe line 130 via the sense transistor 215a. In addition, there are cases where the logic circuit on the base array 140 has a flip-flop or a latch, and it is desired to transfer data to these registers to check the operation. The circuit portion 142b shows the case, and the sense transistor 215b is connected to the input of the flip-flop so that the flip-flop of the circuit portion 142b can be written from the sense line 120. As described above, the matrix mechanism of the probe line 130 and the sense line 120 is used to directly write the data of the sense line 120 into the flip-flop, thereby providing the controllability.

[0009]

In the circuit described above, the probe lines 130 are set high one by one, and the probe points 19 are turned on.
Since the state of 0 is read or changed, the time required for the test becomes long, especially when the number of probe points 190 increases. Further, writing to the probe points 190 on the same sense line 120 can be performed at the same time with the same data, but must be performed separately if the data is different. In particular, when the number of probe points 190 is large, the amount of data to be written is small in the same case, so that it is very difficult to reduce the time required for the test. In recent years, circuits integrated on an LSI have become large-scaled and complicated, and a very long test time greatly reduces productivity.

[0010]

In order to solve the above problems, a semiconductor device according to the present invention comprises a base array in which a logic circuit is formed and first and second regions obtained by dividing the base array in the column direction. Of which are arranged in the column direction on the first region,
The first probe line for accessing the probe point of the logic circuit on the first area and the contents of the probe point which is arranged in the row direction on the first area and accessed by the first probe line are displayed. First for reading or modifying
Of the sense lines of the above and arranged in the column direction on the second region,
A first probe line for accessing a probe point of a logic circuit on a second area independently of the first probe line, and a second probe line arranged in a row direction on the second area. A second sense line for reading or changing the content of the probe point accessed at.

It may be characterized by further comprising a switch element for connecting the end points of the first and second sense lines by a signal from the outside.

[0012]

The content of the probe point on the logic circuit is read from the sense line by accessing the probe line, or the content is changed by transferring data from the sense line to the probe point. Here, in the semiconductor device of the present invention, the probe point of the logic circuit on the first region can be accessed by the first probe line, and the content of the probe point can be read or changed from the first sense line. It is possible. Also,
It is possible to access the probe point of the logic circuit on the second area with the second probe line and read or change the content of the probe point from the second sense line. The reading or changing of the probe points in the first and second areas can be performed independently and simultaneously. Therefore, the probe points can be read out or changed at a higher speed, so that the logic circuit on the base array can be tested more quickly.

[0013]

Embodiments of the present invention will be described with reference to the drawings.
Descriptions of the same or equivalent elements as those of the above-described conventional example will be simplified or omitted.

FIG. 1 shows an LSI chip 11 using the present invention.
0 shows a similar view of the sense lines 120a and b and the probe line 130 on the logic circuit formed in the base array 140 of the LSI chip 110.
a and b are wired. Then, the sense line 120
a and the probe line 130a, the probe point 190 on the left side of the base array 140 in the drawing is connected to the sense line 120b.
The probe line 130b can independently access the probe point 190 on the right side of the base array 140 in the drawing. The sense lines 120a and 120b can be connected by a sense line switch 220, and the LSI of FIG. 1 is characterized by these points.

The data registers 170a and 170b and the sense line drivers 160a and 160b are respectively connected to the sense line 120.
The probe line drivers 180a and 180b are for controlling a and b, respectively.
This is for controlling a and b separately. These basic configurations are similar to those of the above-described conventional example, and are provided on the left side and the right side of the base array 140, respectively.

The sense line switch 220 can be composed of a CMOS transmission element and is turned on / off according to a signal from the test controller 156.

The test controller 155 includes a data register 170a, 170b, a sense line driver 160a,
b for controlling the probe line drivers 180a and 180b, respectively, and can be realized by a configuration having two systems similar to the above-described conventional example. Further, the sense line switch 220 is controlled so as to turn on the sense line switch 220 when simultaneously writing to the left and right probe points 190. The circuit in the vicinity of the probe point is similar to that of the above-mentioned conventional example. Therefore, the probe point 19
The access to 0 is performed by making the probe line high one by one, and this point is similar to the above-mentioned conventional example.

In the LSI of FIG. 1, when the sense line switch 220 is off, the probe line driver 1
80a and 80b are operated independently, and the left and right probe lines 130a and 130b become independently high one by one. At the time of reading, the probe line 130a which has become high,
The state of the logic circuit of the probe point 190 on the line b is read to the left and right sense lines 120a and 120b, respectively. Then, these data are stored in the left and right data registers 170a,
test controller 155 after being respectively held in b
Then, the contents of the left and right data registers 170a and 170b are compared with expected values, respectively, or output to the outside to check the logic circuit formed in the base array 140.

Similarly, when the sense line switch 220 is in the OFF state, at the time of writing, the left and right probe lines 130a and 130b are independently set to two high, and the data held in advance in the data registers 170a and 170b, respectively. It is transferred to the right and left probe points 190 via the left and right sense lines 120a and 120b.

As described above, when the sense line switch 220 is in the off state, the probe point 190 is accessed independently on the right side and the left side, so that different data can be read and written at the same time. The time taken to access the probe points 190 of the array 140 will be halved. Therefore, the time required for the test can be significantly reduced. In particular,
At the time of writing, the sense lines 120a and 120b are set to 2
Since it is divided, different values can be set, the controllability of writing to the flip-flop is improved, the number of times the value is reset to the sense line is halved, and the time is drastically reduced.

Further, the probe line driver 180a,
Since b has a structure in which the same circuit is repeated, it does not greatly increase the area occupied on the LSI chip even if it is divided into left and right, and the sense line drivers 160a and 160b and the data registers 170a and 170b also require such a large area. Not a thing. Therefore, the area of the LSI chip is not increased so much, that is, the area impact can be suppressed and the time required for the test can be significantly reduced.

When the same value is transferred to the right and left probe points 190, the time can be further reduced by turning on the sense line switch 220. When the sense line switch 220 is in the ON state, the left and right sense lines 120a and 120b have the same value, and the left and right probe lines 130a and 130b become high, so that the probe points 190 on the probe lines 130a and 130b are simultaneously detected. The value is transferred. At this time, the data register 170a,
If the same value is set in b, the left and right sense lines 1
Since the lines 20a and 20b are connected and the line becomes shorter than in the case of FIG. 3, the precharge time of the sense lines 120a and 120b is not only shortened but also becomes the same potential. In this way, the write time can be shortened to shorten the test time and increase the controllability.

The present invention is not limited to the above-described embodiment, but various modifications can be made.

Although FIG. 1 shows an example in which the left and right are divided into two, as shown in FIG. 2, the base array 140 is divided into four and the sense lines 120a, b, c, d and the probe lines 130a,
You may make it provide b, c, d and the circuit corresponding to them. By doing so, it becomes possible to independently access the probe points of the divided areas, and it becomes possible to perform the test at a higher speed.
Further, it may be divided into a larger number.

[0025]

As described above, according to the present invention, the reading or changing of the probe points in the first and second regions can be carried out independently and simultaneously, so that more Since the probe points can be read or changed at high speed, the logic circuit on the base array can be tested more quickly.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment.

FIG. 2 is a configuration diagram of a modified example.

FIG. 3 is a schematic view of an LSI.

FIG. 4 is a configuration diagram of a conventional example.

[Explanation of symbols]

120a, b, c, d ... Sense line, 130a, b,
c, d ... Probe line, 190 ... Probe point, 215
a, b ... NMOS transistor, 220 ... Sense line switch.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/822 H03K 19/00 B 8839-5J

Claims (2)

[Claims] 1. A base array in which a logic circuit is formed, and a first array arranged in the column direction on the first area of the first and second areas obtained by dividing the base array in the column direction. A first probe line for accessing a probe point of the logic circuit on the region of, and a probe point that is arranged in a row direction on the first region and is accessed by the first probe line. A first sense line for reading or changing the contents, and a logic circuit arranged in the column direction on the second region and independent of the first probe line on the second region. A first probe line for accessing a probe point and a row of the second area are arranged in the row direction to read or change the contents of the probe point accessed by the second probe line. Semiconductor device and a second sense line of fit. 2. The semiconductor device according to claim 1, further comprising a switch element for connecting the end points of the first and second sense lines by a signal from the outside.