JPH07175724A - Memory caching method and device therefor - Google Patents

Abstract

PURPOSE:To shorten the overall access time of a system by considering the congestion information on the access path set to a main memory in a replacement system for cache blocks and then by preventing the accesses from concentrating in a specific access path. CONSTITUTION:A cache memory 2 sends the information on the access path set to a main memory 5 from a replaceable cache block to an access path monitoring mechanism 4. The mechanism 4 detects the congestion state of each access path based on the received access path information and sends these detecting results to a block selecting mechanism 3. The mechanism 3 selects an access path of the least congestion based on the congestion states of access paths detected by the mechanism 4. Then the mechanism 3 decides the cache block which uses the selected access path as a replacing block and sends the information on this block to the memory 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, for example, a memory caching method and apparatus for a parallel processing system.

[0002]

2. Description of the Related Art Conventionally, in a parallel processing system in which a main memory shared by a plurality of information processing devices can be accessed, if each information processing device has a single access path to the main memory, Access requests from the devices to the main memory are concentrated and congested on a single access path, and the main memory access from each information processing device is delayed.

Therefore, it is advantageous that there are a plurality of access routes from each information processing device to the main memory. Conventionally, there is a parallel processing system in which there are a plurality of access routes from each information processing device to the main memory. Has been proposed.
In the parallel processing system described above, when a certain access route among a plurality of access routes is congested, main memory access using the access route from each information processing device is greatly delayed. Therefore, in the conventional parallel processing system, the areas of the main memory that store the data to be accessed simultaneously are distributed over the areas of the main memory on multiple access routes, and the capacity of the cache memory of each information processing device is increased. Therefore, the main memory access is reduced, and the access route to each main memory is kept as crowded as possible.

In addition, the memory caching device of the conventional information processing device has a plurality of cache blocks. In the caching device of the main memory data for the plurality of cache blocks, a direct mapping system and a set associative system are used. There are three types of full associative methods. Of the three types of data storage methods of the memory caching device, in the two methods of the set associative method and the full associative method, when storing certain data in the main memory in the cache memory, one of a plurality of cache blocks is used. A block replacement occurs in which a cache block is selected and the data stored in the cache block must be swept or invalidated. Conventionally, this replacement algorithm has been LRU (L
A method based on east recently used) is adopted,
The selection scheme was based on the process that the cost of main memory access to write data to the main memory or read the data again is the same in all cache blocks. Further, as a replacement algorithm other than the LRU-based method, for example, a known FIF is used.
The O method and the method of deciding the cache block to be replaced have been adopted based on the access time to the data stored in the main memory.

[0005]

However, in the above-mentioned conventional example, when there are a plurality of access paths to the main memory in the parallel processing system, the replacement is performed in accordance with the selection of which of the plurality of cache blocks is to be replaced. The congestion situation of the access route to the main memory with the cache block was not considered.

Therefore, in a memory caching apparatus which adopts the set associative method or the full associative method as a method for storing main memory data in a plurality of cache blocks, accesses are concentrated on a specific access path and only that access path is stored. It gets crowded. As a result, there has been a problem that the memory access time of the entire parallel processing system becomes long and the processing capability is lowered.

[0007]

The present invention has been made for the purpose of solving the above-mentioned problems. As one means for solving the above-mentioned problems, the following structure is provided. That is, a memory caching device having a plurality of cache blocks capable of storing data at a predetermined address, the main memory access means accessing a main memory by a plurality of access paths, and all access paths of the main memory access means. Congestion state detection means for detecting the congestion state of,
An access route selecting unit that selects an access route having the most margin according to the congestion status of all the access routes detected by the congestion state detecting unit, and a cache block that uses the access route selected by the access route selecting unit are replaced. Block selection means for selecting as a block, main memory access means for accessing the main memory by the main memory access means by using the access path selected by the access path selection means, and cache selected by the block selection means The block has block replacement means for copying data from the main memory by the main memory access means.

For example, the main memory access means configures an access path to a plurality of main memories by an interconnection network, and the congestion state detection means detects the packet by adding packet count information to a packet in the interconnection network. It is characterized by doing.

[0009]

In the above configuration, in a parallel information processing apparatus having a plurality of access routes to the main memory, the replacement control method of the cache block allows the congestion information of the access route to the main memory to be taken into consideration, so that a specific access route can be obtained. It is possible to prevent a delay in access time due to the concentration of accesses to the memory, reduce the memory access time of the entire system, and increase the processing speed of the entire system.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described in detail below with reference to the drawings. <First Embodiment> FIG. 1 is a block diagram showing a schematic configuration of a memory caching device in a parallel processing system of the present embodiment and its operation target.

In FIG. 1, reference numeral 10 surrounded by a broken line is a memory caching device in this embodiment, which is composed of a cache memory 2, a block selection mechanism 3, and an access route monitoring mechanism 4. The memory caching device 10 is
It is connected to the main memory 5 by a plurality of access paths 6 and provides the data stored in the main memory 5 to the central processing unit 1. Here, the main memory 5 can be considered by being divided into a plurality of areas by a plurality of access paths 6.

Further, a configuration in which the central processing unit 1 is added to the memory caching device 10 is referred to as a memory caching unit 20. In the parallel processing system of this embodiment, there are a plurality of memory caching units 20 having the same configuration, and the description thereof will be omitted. . Next, FIG. 2 shows a schematic configuration example of a parallel processing system including the memory caching device of this embodiment shown in FIG.

In FIG. 2, reference numerals 21 to 24 are main memories 0 to 3, which can be divided into four areas, and are accessed from the memory caching units 25 to 28 using the four buses 29 as respective access paths. It The memory caching units 25 to 28 are the memory caching unit 20 shown in FIG. 1, and only the central processing unit and the cache memory are shown in FIG.

The operation of the memory caching device 10 having the above configuration will be described in detail with reference to FIGS. 3 and 4. FIG. 3 is a diagram showing the flow of each information in the memory caching device of this embodiment. The access route monitoring mechanism 32 detects the congestion status of each of the plurality of access routes 6 shown in FIG. 1 by examining the access route occupancy rate for a predetermined period in the past using a bus snoop mechanism or the like (not shown).

When a cache block replacement request is generated in the cache memory 33, the cache memory 33 includes access paths from the replaceable cache blocks to the main memory as access path information by including the access path in a memory address described later. It is sent to the route monitoring mechanism 32. The access route monitoring mechanism 32 detects the congestion status of each access route according to the access route information obtained from the cache memory 33, and sends it to the block selection mechanism 31.

Then, the block selecting mechanism 31 selects the least congested access route judging from the congestion status of each access route received from the access route monitoring mechanism 32, and uses the selected access route. Is determined as a replace block, and the information is sent to the cache memory 33. In the cache memory 33, the contents of the cache block are replaced with the contents of the corresponding block of the main memory via the access path in accordance with the replacement block information obtained as described above.

In the example shown in FIG. 3 described above, the congestion status of the access route is checked by notifying the access route monitoring mechanism 32 of the access route selection information as the memory address information, but this embodiment is not limited to this. However, if the number of access routes is small, for example, the congestion status can be unconditionally checked for all access routes. An example thereof will be described with reference to FIG.

In FIG. 4, when a cache block replacement request is issued to the cache memory 43,
The cache memory 43 sends the access path from the replaceable cache block to the main memory to the block selection mechanism 41 as access path information. Also,
At the same time, the cache memory 43 sends a congestion status report request to the access path monitoring mechanism 42 so as to detect the congestion status of all access paths and send it to the block selection mechanism 41. The access path monitoring mechanism 42 detects the congestion status of all access paths according to the congestion status report request from the cache memory 43, and sends it to the block selection mechanism 41.

Then, the block selecting mechanism 41 selects the least congested access route judging from the congestion status of all the access routes received from the access route monitoring mechanism 42, and uses the selected access route in the cache block. Is determined as a replace block, and the information is sent to the cache memory 43. In the cache memory 43, the contents of the cache block are replaced with the contents of the corresponding block of the main memory via the access path in accordance with the replacement block information obtained as described above.

As described above, in the memory caching device of this embodiment, the block selection mechanisms 31 and 41 are used.
Selects a cache block in which the access route is not congested as a replacement block according to the congestion state of the access route obtained by the method shown in FIG. 3 or 4.
Next, the configuration of the cache memory in the above-described memory caching device of the present embodiment will be described below with reference to FIGS. 5, 6 and 7.

FIG. 5 is a diagram showing a configuration example of a cache memory using a set associative system (hereinafter, 4-way set associative cache) having four access routes. In FIG. 5, reference numeral 51 is a memory address storing the address of the reference data in the main memory, 52 to 55 are cache memory banks, respectively, and in this embodiment, there are four banks.

In this embodiment, the lower bits of the memory address 51 of the reference data determine the blocks that can be stored one by one from the four cache memory banks 52 to 55, that is, four blocks are selected as replacement candidates. To be done. Then, the address information of the blocks on the selected cache memory banks 52 to 55 is sent to the block selection mechanism.

FIGS. 6 and 7 are examples showing how the main memory is divided into areas in this embodiment. FIG. 6 shows the contents of the memory address 51 shown in FIG. In FIG. 6, the memory address 51 indicates the identification of the main memory banks 0 to 3 by the middle bit 61, and the lower bit 62 following the middle bit 61 indicates the address in the cache memory. Then, as shown in FIG. 6, for example, the address area corresponding to the main memory bank 0 is "0x ??????? 0000 to 0x ?????? 0fff" in the memory address 51.
Is expressed as That is, the lower 16 bits of the memory address 51 indicate the address in the cache memory, and the subsequent 4 bits are the main memory bank identification.

It is assumed that the 4 bits represented by "??????" shown in the example of the address area in FIG. 6 take an arbitrary value. In the present embodiment, the main memory is divided into areas as shown in FIG. 6, for example, and the access path is determined depending on which bank of the main memory is accessed.

Further, as in FIG. 6, the upper bits 71 of the memory address are set to the main memory banks 0 to 3 as shown in FIG.
It is also possible to divide the main memory area using the lower bit 72 as an address in the cache memory. As described above, the bit information for determining the main memory bank as shown in FIG. 6 or 7 is transferred from the cache memory 33 shown in FIG.
By sending the replacement candidate block, the congestion status of the access route of each replacement candidate block can be detected.

In this embodiment, the replacement block is replaced only by the congestion condition of the access route, such as when no bus is accessed at all in the past within a certain period of time or a block having the same congestion condition is selected. There may be cases where the decision cannot be made. In that case, first, a replacement candidate block is selected according to the congestion status of the access route, and then the replacement block is determined by a method such as LRU approximation.

As described above, according to the present embodiment, in a parallel processing system having a plurality of access paths to the main memory, the replacement control method of the cache block is made to consider the congestion information of the access path to the main memory. This has the effect of reducing the memory access time of the entire system and increasing the processing speed of the entire system.

<Second Embodiment> A second embodiment according to the present invention will be described below. In the above-described first embodiment, the case where the access path to the main memory can be directly monitored from the memory caching device has been described, but in the second embodiment,
With reference to FIGS. 8 and 9, an example in which the present invention is applied to a system in which a main memory is accessed by transmitting a packet by an interconnection network will be shown.

FIG. 8 is a block diagram showing a schematic configuration of a parallel processing system connected by an interconnection network. In FIG. 8, reference numeral 80 is a memory caching unit, which includes a central processing unit 81 and a memory caching unit 82. The memory caching device 82 has the same configuration as the memory caching device 10 of the first embodiment shown in FIG. 1 and includes a cache memory 2, a block selection mechanism 3, and an access route monitoring mechanism 4.

There are a plurality of memory caching units 80,
For example, a main memory 84 divided into a plurality of areas via an interconnection network 83 such as a crossbar, multistage connection, or torus.
Connected to. An interconnection network 83 as shown in FIG.
In the parallel processing system in which the main memory 84 and the central processing unit 81 are connected by, the access to the main memory 84 is performed by transmitting a packet by the mutual connection network 83. Therefore, the congestion status of the access path to the main memory 84 cannot be directly detected from the memory caching device 82.

Therefore, in the second embodiment, an example in which the information on the congestion status of the access route is added to the packet for accessing the main memory 84 will be described in detail below with reference to FIG. FIG. 9 is a diagram showing the concept of a switch that adds the congestion status of an access route to a packet.

In FIG. 9, 90 is a switch that exists in each network of the mutual connection network 83 shown in FIG. In the second embodiment, for simplicity of explanation, it is assumed that the switch 90 includes two inputs 95 and 96 from the memory caching unit 80 and two outputs 97 and 98 to the main memory 84.
The packet 93 is input from 6 and the packet 9 is output 97.
4 shows an example in which 4 is output. Switch 90 is counter 9
Including 1, 92, the number of packet inputs per unit time is counted. The packet count values of the counters 91 and 92 are cleared by a circuit (not shown) every predetermined unit time. The packets 93 and 94 are transmitted to a plurality of central processing units 81.
Identification information, address information of the main memory 84 to be accessed, an area for storing the data itself stored at the address, and the like, and packet count information 100, 101.

The operation of the switch shown in FIG. 9 in the second embodiment having the above structure will be described below. As shown in FIG. 9, consider the case where the packet 93 is input from the input 96. Packet 93 input 96
When the data is input to the switch 90 from the counter, the counter 92 in the switch 90 adds 1 to the value to accumulate the number of input packets. Then, the value of the counter 92 is stored in the packet count information 100 of the packet 93, and the packet 94 is output from the switch 90 to the output 97.
Is output, the value of the counter 92 is stored in the packet count information 101, that is, the access path from the caching device 82 to the main memory 84 is input 96.
If it is, the congestion situation is detected.

Therefore, the access path monitoring mechanism 4 shown in FIG. 1 included in the memory caching device 82 obtains the congestion status from the value of the packet count information included in the packet returned from the main memory 84, and the memory caching device The statistical information of the congestion status of the access path from 82 to the area of each main memory 84 is stored. Then, the access route monitoring mechanism 4 notifies the block selection mechanism 3 shown in FIG. 1 included in the memory caching device 82 of the statistical information of the congestion status of each access route.

As described above, also in the second embodiment, the replacement block is determined as in the first embodiment.
Although the example of counting the packets by the counter 92 is shown in the above-mentioned example, the same applies to the counting by the counter 91. Also, the access route from the input 96 to the switch 90 to the output 97 is shown, but of course the input 9
Similar results are obtained from 6 to output 98.

As described above, according to the second embodiment,
Even in the parallel processing system in which the main memory and the central processing unit are connected by the mutual connection network, by adding the packet count information to the packet, it is possible to use the cache block replacement control method as in the first embodiment, as in the first embodiment. It is possible to take into consideration the congestion information of the access path to the memory, which has the effect of reducing the memory access time of the entire system and increasing the processing speed of the entire system.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0038]

As described above, according to the present invention, in a parallel information processing apparatus having a plurality of main memory access paths, the cache block replacement control method takes into consideration congestion information of the main memory access paths. By doing so, it is possible to prevent the delay of access time due to the concentration of accesses on a specific access route, reduce the memory access time of the entire system, and increase the processing speed of the entire system. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic structure of a memory caching device in a first embodiment according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a parallel processing system using a plurality of buses according to the present embodiment.

FIG. 3 is a diagram showing a flow of each piece of information regarding a selected access path in the memory caching device of the present embodiment.

FIG. 4 is a diagram showing a flow of each information regarding all access paths in the memory caching device of the present embodiment.

FIG. 5 is a diagram showing a configuration example of a cache memory using the set associative method of the present embodiment.

FIG. 6 is a diagram showing an example of area division of a main memory by a plurality of buses according to the present embodiment.

FIG. 7 is a diagram showing an example of area division of a main memory by a plurality of buses according to the present embodiment.

FIG. 8 is a block diagram showing a schematic configuration of a parallel processing system connected by an interconnection network in a second embodiment according to the present invention.

FIG. 9 is a conceptual diagram of a switch that adds a congestion status of an access route to a packet in the second embodiment.

[Explanation of symbols]

 1 central processing unit 2 cache memory 3 block selection mechanism 4 access time storage mechanism 5 main memory 6 access path 10 memory caching device 20 memory caching unit

Claims (4)

[Claims] 1. A memory caching method in a memory caching apparatus having a plurality of cache blocks capable of storing data at a predetermined address, wherein all access paths by a main memory access means for accessing a main memory by a plurality of access paths. A congestion status detecting step of detecting the congestion status of the access path, an access path selecting step of selecting an access path having the most room according to the congestion status of all the access paths detected by the congestion status detecting step, and the access path selecting step A block selecting step of selecting a cache block using the selected access path as a replacement block; and a main memory access step of accessing the main memory by the main memory access means using the access path selected in the access path selecting step. Memory caching method characterized by comprising the scan process, and a block replacement process of copying data from the main memory by said main memory access process to the cache block selected by the block selection process. 2. The main memory access means configures an access path to a plurality of main memories by an interconnection network, and the congestion state detecting step detects by adding packet count information to a packet in the interconnection network. The memory caching method according to claim 1, wherein: 3. A memory caching device having a plurality of cache blocks capable of storing data at a predetermined address, the main memory access device accessing a main memory through a plurality of access paths, and all of the main memory access devices. Congestion status detection means for detecting the congestion status of the access path, access path selection means for selecting the access path with the most room according to the congestion status of all access paths detected by the congestion status detection means, the access path Block selecting means for selecting a cache block that uses the access path selected by the selecting means as a replacement block, and accessing the main memory by the main memory accessing means using the access path selected by the access path selecting means. Main memory access hand When, memory caching apparatus characterized by having a block replacement means for copying data from the main memory by said main memory access means to the cache block selected by said block selecting means. 4. The main memory access means configures an access path to a plurality of main memories by an interconnection network, and the congestion status detection means detects by adding packet count information to a packet in the interconnection network. The memory caching device according to claim 3, wherein: