JPH07170192A - Vector quantization device - Google Patents

Abstract

PURPOSE:To conduct high speed code book retrieval even when the size of the code book is large by providing a bit inversion position information generating means generating bit inversion position information and a retrieval means for retrieving a code word and a code vector to the device. CONSTITUTION:A control section 20 references an M1 bit code word bit inverting location information table 18 based on the value k1 of a low-order counter 16 to provide the output of bit inversion location information (v) to a computer section 21. The computer section 21 makes calculation of equation I to inverts a sign of thetav and to update an inner product C and a power G. A comparator section 22 makes discrimination of C<2>Gb>Cb<2>G (C is an inner product, Gb, Cb are parameters, and G is a code vector power). In the case of C<2>Gb>Cb<2>G, optimum parameters Cb, Gb and a variable mb are updated by using the C, G, n, and no updating is made in the case of C<2>Gb<Cb<2>G. Then the value k1, the count (n) are incremented by 1, the information (v) is obtained from the table 18 by the same procedure to update the inner product C and the power G, and a succeeding code word is retrieved by the comparison with the preceding optimum code word. The retrieval above is continued till the value k1 reaches 2M<1>-1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector quantizing device in a coding device for coding an information signal such as a voice signal, and more particularly to a vector quantizing device using a vector sum type codebook.

[0002]

2. Description of the Related Art VSE is one of the coding systems capable of high-quality coding of a voice signal at a low rate of about 8 kbit / sec.
An LP (Vector sum Excited Linear Prediction) method is known. For details of the VSELP method, see “VECTOR SUM EXC” by Ira A. Gerson and others.
ITED LINEAR PREDICTION (VSELP) SPEECH CODING AT 8k
BPS ”, Proc.IEEE Int.Conf. On Acoustics.Speech an
d Signal Processing, pp.461-464, April 1990 (hereinafter,
Reference 1) and pages 344 to 345 (hereinafter referred to as Reference 2) of "Digital Signal Processing Handbook" edited by the Institute of Electronics, Information and Communication Engineers.

The VSELP system is based on CELP (Code Excit).
ed Linear Predicion) is the basic method. As is well known, the CELP method stores drive signal candidates of an LPC (Liner Predictive Coding) synthesis filter in a codebook as a drive signal vector to generate a synthesized speech signal and an input speech signal. The optimum drive signal vector is searched from the codebook while evaluating the error of, and the codeword corresponding to the drive signal vector is output. A major difference between the VSELP system and the CELP system is that a so-called vector sum type codebook is used, which expresses a codebook by multiplying each of a plurality of basis vectors by the polarity information and adding them.

A vector sum type codebook used in the VSELP system will be briefly described with reference to FIG. As described above, the vector sum codebook expresses 2 ^M code vectors (for example, drive signal vectors) by a combination of sums or differences of M basis vectors, and information of the combination of the sums and differences is M bits. It is expressed by the code word of. FIG. 6 schematically shows the structure of this vector sum-type codebook. V _m (n) represents the m-th base vector, u _i (n) represents the code vector of the code word i, and the base The coefficient θ _im (which is referred to as polarity information) for multiplying the vector takes any one of +1 and −1 depending on the values of the code words i and m. In addition, 0 ≦ i ≦ 2 ^M −1, 0 ≦ n ≦ N
−1 (N is the number of dimensions of the vector). If this relationship is expressed in more detail by mathematical expressions, the following expressions (1) and (2) are obtained.

[0005]

[Equation 1]

By effectively utilizing the structure of such a vector sum type codebook, the amount of calculation required for the codebook search can be significantly reduced as compared with the case of searching for a normal noise codebook. Specifically, a codeword sequence G (for example, Gray code) having a structure in which adjacent M-bit codewords are inverted by only 1 bit is used, and each codeword of this codeword sequence G is used as a code for each codebook. It is known that if a codebook search (search for codewords and codevectors from a codebook) is performed in the order of the codewords in correspondence with the words and codevectors, a simple recursive search can be performed. The amount of calculation required for can be greatly reduced.

However, in the above-described recursive calculation, since the search is performed in the order of the codewords of the codeword sequence G, the bit inversion positions of the adjacent codewords in the codeword sequence G,
That is, the bit inversion position information FLIP (), which indicates what number bit of the immediately preceding search code word is inverted to generate the current search code word i, is required, and this bit inversion position information FLIP (). We need some means to obtain The conventional technology does not mention any specific means for obtaining the bit inversion position information FLIP (), which is indispensable for the codeword search. Bit reversal position information F
The method of calculating LIP () by calculation greatly increases the amount of calculation required for codeword search. To avoid this, a ROM table may be used. In this case, it is known that the number of data required for the bit inversion position information FLIP () is 2 ^M-1 -1. Therefore, in this method, if the codebook size M reaches ten or more bits, the ROM capacity for storing the bit inversion position information becomes enormous, and the hardware load increases. As a result, it becomes difficult to realize a vector quantizer using a vector sum type codebook.

[0008]

As described above, in the conventional vector quantizer using the vector sum type codebook, the method of calculating the bit inversion position information necessary for efficient codebook search is used. In addition, the calculation amount required for the search is significantly increased, and the method of storing the bit inversion position information in the ROM table requires the bit inversion position information when the codebook size becomes ten or more bits. Since the amount of data becomes enormous, there is a problem that a hardware burden becomes heavy and it becomes difficult to realize a vector quantization device using a vector sum type codebook.

It is an object of the present invention to provide a vector quantization device using a vector sum type codebook which can perform a codebook search at high speed with a small amount of hardware even if the size of the codebook is large. .

[0010]

In order to achieve the above object, the present invention provides a vector sum type codebook that expresses an M-bit codebook by multiplying M basis vectors by polarity information and adding them. In the vector quantizer which performs vector quantization by using
As information indicating the bit inversion position of adjacent codewords in a codeword sequence having a structure in which the codewords of bits are inverted by one bit from each other, L pieces of information satisfying the relationship of M-1 = M1 + ... + ML (L ≧ 2) Mi bits (Mi = M1, ..., M
Bit inversion position information generating means for generating bit inversion position information of a code word of L, Mi <M-1), and an optimum code word and a code corresponding thereto from the code book with reference to the bit inversion position information And a search means for searching a vector. Here, Mi is almost (M-
1) / L is preferable. Also, Mi is small,
Increasing L is also effective.

[0011]

As described above, according to the present invention, a code word sequence G having a structure in which adjacent M-bit code words are inverted by one bit from each other
Codebook search using (eg Gray code) (search for codewords and codevectors from codebook)
In order to obtain the bit inversion position information required for performing M, M−1 = M1 + ... + ML, (L ≧ 2) (3) Mi bits (Mi = M1, ...
ML, Mi <M-1) is defined. Then, the code word search is performed by virtually separating M-1 bits, which is the actual search range of the code word in the code word sequence G, into L Mi bits.

At this time, L pieces of bit inversion position information FLIPi () of Mi bits are required. For example, when FLIPi () is generated by table lookup using ROM, Mi is greater than M-1. Since it is also small, the total size of the table of the L bit inversion position information FLIPi () is significantly smaller than that of the M-1 bit bit inversion position information FLIP () table. This is also clear from the following equation (4). 2 ^M-1 = 2 ^M1 2 ^M2 ... 2 ^ML > 2 ^M1 +2 ^M2 + ... +2 ^ML (4) Therefore, when the ROM table is used to store the bit inversion position information, the required memory amount is significantly increased according to the present invention. You can see that it can be reduced to.

Next, with Mi bits smaller than M-1, M
It shows that the bit inversion position information of the -1 bit codeword can be efficiently expressed. FIG. 4 shows a 4-bit counter value k, Gray code Gray (k) and (Gray (k)) XOR (Gray (k-
The relationship between the binary representation of 1)) and the bit inversion position information FLIP (k) of the Gray code Gray (k) is shown. here,
(i) XOR (j) represents the bitwise exclusive OR of i and j. As shown in FIG. 4, in the Gray code, adjacent code words differ by only 1 bit. Also, (Gray (k)) X
The position of "1" in the value of OR (Gray (k-1)) indicates which position of the bit of Gray (k-1) is inverted to obtain the codeword of Gray (k). I understand. However, (Gray (k))
In the table of XOR (Gray (k-1)), the position of the bit to be inverted is not directly indicated by a numeral, so in actual processing, the FLI that directly indicates the bit inversion position of the gray code
Information in the form of P (k) is needed.

FIG. 5A shows the value of (Gray (k)) XOR (Gray (k-1)) when the number of bits of k is expanded from 4 bits. In this figure, in order to make the structure of the bit inversion position information easy to understand visually, the bit inversion positions indicated by "1" are connected by a straight line for every adjacent bit positions.
It can be seen that the figures connected by straight lines in this way have a binary tree structure.

FIG. 5B shows that this binary tree structure has a structure that repeats at a cycle corresponding to each bit position. That is, it can be seen that the bit inversion of the codeword occurs in the region 101 at a period of 2 ⁰ , in the region 102 at a period of 2 ¹ , and in the region 103 at a period of 2 ² . In addition, FIG.
The binary tree structure indicates that the bit inversion position information having a large number of bits includes the bit inversion position information of a small bit. That is, region 104 is also part of region 105 and part of region 106. The region 105 is a part of the region 106. From this structure, if the bit inversion position information having a large number of bits is obtained, the bit inversion position information having a smaller number of bits can be substituted with the bit inversion position information having a larger number of bits.

Considering such a bit inversion structure of the code word sequence G represented by the Gray code, as shown in the equation (3), the M-1 bit code word is virtually divided into L pieces. By dividing into small Mi-bit-unit codewords,
By combining the bit inversion position information FLIPi () of the Mi bit code word of the small table data with a regular algorithm, it becomes possible to express the inversion position information of the M-1 bit large code word.

Therefore, according to the present invention, it is possible to provide a vector quantizer using a vector sum type codebook which can obtain bit inversion position information at high speed with a small memory amount even if the codebook size M is large.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a main part of a speech coder when a vector quantizer using a vector sum codebook according to an embodiment of the present invention is applied to drive signal coding. . In the present embodiment, as a method of implementing the drive signal encoding, the drive signal encoding unit is divided into a front stage and a rear stage, and the vector quantizer according to the present invention is applied to the rear stage encoding unit. Further, in the latter-stage encoding unit of this drive signal, the optimum vector is searched for by orthogonalizing the composite vector generated from the base vector with the orthogonalization processing vector p obtained from the former-stage encoding unit of the drive signal. An example of a method of performing is described.

In FIG. 1, an input audio signal is input from a terminal 10 to a first processing unit 11 which performs synthesis filter encoding, pre-stage encoding of a drive signal, and gain information encoding. The first processing unit 11 is a known technology CE.
It can be realized by a configuration similar to that of a speech encoding unit of LP (Code Excited Linear Prediction) system. That is, the first processing unit 11 first analyzes the input voice signal to extract the coefficient information of the synthesis filter that is the spectrum envelope information of the voice, encodes this, and outputs the code A, and then the drive signal. The driving signal information such as the pitch period is extracted as the preceding-stage encoding, and this is encoded to output the code L. Further, the first processing unit 11 is a second processing unit 1 described later.
The target vector X used for the post-coding of the drive signal at 2,
The impulse response vector h and the orthogonalization processing vector p are output to the second processing unit 12. Further, the first processing unit 11 extracts the gain information for controlling the gain of the encoded audio signal in consideration of the code vector u _I from the second processing unit 12, encodes this, and outputs the code R. .

The second processing unit 12 performs post-stage encoding of the drive signal by vector quantization using a vector sum type codebook that expresses each code vector of the codebook by a combination of sums and differences of decimal base vectors. The optimum codeword I and the code vector u _I corresponding thereto are output as the encoded output. Here, M-bit vector quantization using M basis vectors will be described.

First, a brief description will be given of the codeword search algorithm of the vector sum type codebook. As described above, when a codeword search is performed using a codeword sequence G (for example, Gray code) in which adjacent M-bit codewords are inverted by 1 bit from each other, the codeword search calculation recursively. Since it is possible, it is known that the amount of calculation can be extremely reduced. For example, the code word u and the code word i are M-bit adjacent code words, and the v-th bit (1 ≦ v ≦ M)
However, the recursive formula shown in the following formula (5) generally holds, as shown in the above-mentioned Document 1.

[0022]

[Equation 2] Next, when the expression (5) is written down in the form of an assignment expression from the right side to the left side, the following expression (6) is obtained.

[0023]

[Equation 3]

Here, θ _v is a variable representing the state of the positive and negative signs of θ of the v-th bit, which is “−1” or “1”, and C
Represents the inner product of the orthogonalized weighted code vector and the target vector X, and G represents the power of the orthogonalized weighted code vector. In addition, R _v is a value obtained by doubling the inner product value of the orthogonalized weighted v-th basis vector and X, and D _mv is the orthogonalized weighted m-th and v-th
Shows the value obtained by multiplying the inner product value of the th basis vector by four, and R
Both _v and D _mv are values that can be calculated before the codebook search.

The codeword search for the codeword sequence G is performed in the order of codewords (for example, in the order of the size of the natural binary code corresponding to the codewords) and when C ² / G determined for each codeword is the maximum. By selecting the codeword of Also,
The code vector of the 1's complement of the code word i and the code vector of the code word i have the same vector shape but different positive and negative signs, so that if one code word is searched for as a result, it corresponds to it. When the value of C is negative, M of the code word
It can be seen that the one's complement of bits is the more suitable codeword. From this, in the M-bit vector sum type codebook search, the search range is 0 to 2 ^M-1 -1 M-
It is known that one bit is enough. The above is the outline of the search algorithm of the vector sum type codebook.

Next, returning to FIG. 1, a specific structure for realizing the above-described vector sum type codebook search algorithm will be described. Second processing unit 12 of FIG.
In, the basis vector generation unit 14 has a function of reading information of M basis vectors from the memory or generating the information by calculation. The pre-processing unit 13 uses the impulse response vector h and the vector p to perform weighting and orthogonalization processing of each basis vector. The output unit 23 outputs the optimum codeword I and the code vector u _I corresponding thereto as described later. That is, a vector sum type codebook is realized by the basis vector generation unit 14 and the output unit 23.

The initialization unit 15 performs an initialization process that should be performed before the codeword search loop. Specifically, the variable n _b that holds the search count counter value n and n when the optimum codeword is updated is set to 0, and the inner product value C and power G corresponding to the initial value codeword are calculated. , The inner product value C and the power G are set to optimum value parameters C _b and G _b , respectively. Further, as one method of initializing θ, the value θ _v of θ for each bit is set to “−1”. The initialization unit 15 also calculates inner product values R _v and D _mv .

In this embodiment, the M-1 bit is the lower (LSB side) M1 bit and the upper (MSB side) M2.
When divided into 2 by bits, that is, M1 + M2 = M-1,
The example of realization of the codeword search based on the present invention when the number of divisions L = 2 is shown.

First, after setting the value k1 of the lower counter 16 to an initial value, for example, "1", the control unit 20 increments the counter value n. Bit inversion position information table 18 for M1 bit codeword based on the lower counter value k1
The bit inversion position information v is given to the calculation unit 21 with reference to (FLIP1). The content of FLIP1 is, for example, the FLIP of FIG. 4 when the codeword sequence G is a Gray code and M1 = 4.
It becomes the table of (k). The calculation unit 21 performs the calculation of the equation (6), inverts the positive and negative signs of θv, and updates the inner product value C and the power G using this.

[0030] Next, the comparison unit 22 makes a determination of _{^{C 2 G b> C b 2}} G, C 2 G b> C b 2 G C when the, G, parameters of the optimal value at n C _b, G _b and the variable n _b are updated, and when C ² G _b ≦ Cb ² G is not updated.
The determination used here is essentially the same as the method of “selecting the code vector that maximizes C ² / G” described above, and is a modification of the equation so that division does not appear in the equation. .

Next, the value k1 and the counter value n of the lower counter 16 are incremented, and M is incremented by the same procedure as above.
1-bit code word bit inversion position information table 18 (F
The value v is obtained from LIP1), the inner product value C and the power G are updated, and the next codeword is searched by comparing with the previous optimum codeword. The lower counter value k1 is 2 ^M1 -1
The search is performed when is reached.

The lower counter value k1 and FLIP described above
A series of processing using 1 will be referred to as "lower bit codeword search". Next, after setting the value k2 of the high-order counter 17 to an initial value, for example, "1", the control unit 20 increments the counter value n. Bit inversion position information table 19 for M2 bit codeword based on the upper counter value k2
The bit inversion position information v is given to the calculation unit 21 with reference to (FLIP2). The content of FLIP2 is, for example, if the codeword sequence G is a Gray code and M2 = 4, there is M1 bit in the lower part of the M2 bit, so the bit inversion position of the upper bit is M1 added to the value of FLIP (k) in FIG. It becomes a table. The calculation unit 21 performs the calculation of Expression (6), inverts the positive and negative signs of θ _v , and updates the values of the inner product value C and the power G using this.

[0033] Next, the comparison unit 22 makes a determination of _{^{C 2 G b> C b 2}} G, C 2 G b> C b 2 parameters C _b of the optimum value when the G, respectively G _b and n _b C, G and n
Update with.

Subsequent to this, the low-order bit codeword search is performed in exactly the same manner as described above. That is, after searching the upper bit codeword referring to FLIP2 once, 2 ^M1 −
The control unit 20 controls the search process so as to search for one lower bit codeword. Next, the high-order counter value k2 and the counter value n are incremented, the bit inversion position information v is obtained from the FLIP2 by the same procedure as above, the inner product value C and the power G are updated, and the result is compared with the previous optimum codeword. To do.
This operation is performed up to the search when the high-order counter value k2 becomes 2 ^M2 -1.

After the above processing is completed, the total code search number counter value n is 1+ (2 ^M1 −1) +2 ^M1 (2 ^M2 −
1) = 2 ^{M1 + M2} = 2 ^M-1 . Therefore, at this point M
This means that the search for all code words for -1 bit has been completed.

The output unit 23 is a variable n _b indicating the search order of the optimum codeword after the completion of the search of M−1 bits from the comparison unit 22.
And the inner product value C _b corresponding to the optimum code word are input, and when C _b is positive, Gray (n _b ) is directly used as the optimum code word I, and C
_{When b} is negative, the one's complement of Gray (n _b ) is used as the optimum codeword I.
Output as. At this time, the code vector u _I corresponding to the optimum code word I is output to the first processing unit 11.

Next, the second part which is the main part of this embodiment
An example of the codeword search procedure in the processing unit 12 will be described with reference to the flowchart shown in FIG. First, the initialization process,
That is, initial setting is performed (step S10). In this initial setting, specifically, the counter values n and n _b are set to 0, the inner product value C and the power G corresponding to the code word I = 0 are calculated, and these values are set to C _b and G _b , respectively. set. At this time, all θ _v for each bit position are simultaneously set to “−1”. In addition, R _v and D mv in equation (6) are also calculated.

In step S11, the lower counter value k1
In a loop that increments from 1 to 2 ^M1 -1,
A process of outputting bit inversion position information v by FLIP1 (k1) (step S12), and a search number counter value n
Of θ _v , C, G according to the equation (6), and comparison of codewords using G _b , C _b , G, C, and then C, G, n, which is the optimum value parameter C _b at the time of updating. , G _b , n
A process of updating _b (step S13) is performed. As a result, the first 2 ^M1 − of the lower M1 bits of the M−1 bits are
One codeword is searched.

[0039] In the next step S14, in a loop that increments higher counter value k2 from 1 to 2 ^M2 -1, upper M2 by step S15 and step S16
The code word corresponding to the bit inversion occurring in the bit is searched, and the search processing of the code word corresponding to the bit inversion occurring in the lower M1 bit is performed in step S17.

In step S15, FLIP2 (k2)
Then, the bit inversion position information v generated in the upper M2 bits is output. As the content of FLIP2, it is sufficient to use the bit inversion position considered by the M2 bit codeword alone, with M1 added. If FLIP1 and FLIP2 are realized by reading from storage means independent of each other, the contents of FLIP2 can be obtained by adding M1 in advance. Also, if FLIP1 and FLIP
When 2 is realized by reading from the common storage means, FLIP2 (k2) may be FLIP1 (k2) + M1. In step S16, the code word is searched for by the same process as in step S13. In step S17, the same process as step S11 is performed, and a codeword search is performed when bit inversion of the codeword occurs in the lower M1 bit of M-1 bits.

By the processing in steps S11 to S14 described above, the search loop for the code word for M-1 bits is completed. Next, the counter value n _b when the optimum value is updated in step S18 is set to the codeword sequence G (Gray code in this case).
To obtain the codeword I. Finally, in steps S19 to S20, when the positive or negative sign of the parameter C _b having the optimum value is negative, all the M bit signs of the code word I are inverted and used as the output code word I to obtain the M bit code. The word search ends.

The effects of the above-described structure of the present embodiment will be shown below with reference to specific numerical examples. Now, M =
13, M1 = 6, M2 = 6 (M-1 = M1 + M2), when the bit inversion position information is represented in the ROM table, at most (2 ^M1 -1) + (2 ^M2 ) in the method of this embodiment.
-1) = 126 table data may be stored.
On the other hand, in the conventional technology, about 32 times as much as 2 ^M-1 -1.
= 4,095 pieces of table data need to be stored.

Further, when the two bit inversion position information is realized by using the common ROM table, it is possible to further reduce the table data to 63 pieces of table data. Further, as a comparative example, FIG. 3 shows a configuration in which the main part of the speech coding apparatus shown in FIG. 1 is replaced based on the conventional technique. As can be seen by comparing FIGS. 1 and 3, the embodiment of the present invention shown in FIG.
The bit inversion position information table (FLIP) 32 in FIG. 3 is different from the counter 31 in the preceding stage and the configuration corresponding to the control unit 30 thereof, and other configurations can be realized by the same configuration as the conventional technique. By dividing the information table, the circuit size can be significantly reduced.

By the way, in the above description, the relationship between the sizes of M1 and M2 was not particularly mentioned, but in the present invention, when the number of divisions of the codeword search range (M-1 bit) is L = 2. In order to reduce the number of tables as much as possible, the numbers of M1 and M2 are almost the same ((M-1) / 2).
Is desirable. The reason is that the number of divisions L is fixed, and the allocation of the number of bits when the total number of tables (2 ^M1 + ... +2 ^ML ) is minimized under the condition of Expression (3) is determined by Lagrange's undetermined constant method. When asked, the optimal solution is M
This is because i = (M−1) / L, and it can be understood that the division should be performed evenly. Further, if the number of divisions that minimizes the number of tables is obtained under this condition, L = (ln2) (M
−1), resulting in Mi = 1 / (ln2),
It becomes about 1.4. Therefore, from the viewpoint of minimizing the number of tables, it is desirable to increase L and decrease Mi.

[0045]

As described above, according to the present invention, even if the codebook size M is large, the amount of memory is small,
That is, it is possible to provide a vector quantization device using a vector sum type codebook that can generate bit inversion position information at high speed without increasing the scale of hardware.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of a speech coding apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a codeword search procedure in the vector quantization device according to the embodiment.

FIG. 3 is a block diagram of a speech coder according to a comparative example based on the related art.

FIG. 4 is a 4-bit counter value k and its Gray code G
Diagram showing the relationship between the binary representation of ray (k) and (Gray (k)) XOR (Gray (k-1)) and the bit inversion position information FLIP (k) of the Gray code.

FIG. 5 is a diagram for explaining the principle of reducing the amount of memory for storing bit inversion position information according to the present invention.

FIG. 6 is a block diagram showing the configuration of a vector sum codebook in the VSELP system.

[Explanation of symbols]

10 ... Audio signal input terminal 11 ... First processing unit 12 ... Second processing unit 13 ... Pre-processing unit 14 ... Basis vector generation unit 15 ... Initialization unit 16 ... Lower counter 17 ... Upper counter 18 ... Bit inversion position information Table 19 ... Bit inversion position information table 20 ... Control unit 21 ... Calculation unit 22 ... Comparison unit I ... Optimal codeword U _I ... Code vector corresponding to I

Claims (2)

[Claims] 1. A vector quantizer for performing vector quantization using a vector sum-type codebook that represents an M-bit codebook by multiplying M basis vectors by each of which is added with polarity information and adding them. M−1 = M1 + ... + ML, as information indicating the bit inversion position of adjacent codewords in a codeword sequence having a structure in which matching M-bit codewords are inverted by one bit from each other.
(L ≧ 2) L number of Mi bits (Mi =
M1, ..., ML, bit inversion position information generating means for generating bit inversion position information of codewords of Mi <M-1), and an optimum codeword from the codebook with reference to the bit inversion position information And a search means for searching the code vector corresponding to the vector quantization device. 2. The bit inversion position information generating means substitutes the bit inversion position information of a smaller bit number with the bit inversion position information of a larger bit number, and the bit inversion position information of a plurality of equal bit numbers. The vector quantization device according to claim 1, further comprising at least one of means for sharing.