JPH07169277A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To prevent the destruction in the memory data at the time of multiple selection of a word line without sacrificing an access time by detecting the multiple selection of plural word lines and controlling an impedance of a bit line load. CONSTITUTION:When two pieces or more of word lines WL0-WL511 are multiple-selected through a row decoder 14 in the state where a clock signal phibecomes an H, and a word line detection circuit 20 is activated, corresponding transistors(TR) TNS0-TNS511 are turned on, and a multiple selection detection signal LC is lowered. Then, the conduction of the TRs TP1, TP2 of a variable load circuit 30 are controlled, and a bit line pair BL, BLb are pulled up by pull-up TRs TN3, TN4 of the circuit 30 in an overlapped state to the conduction of the bit line load TRs TN1, TN2, and a bit line load impedance is controlled, and the potential lowering of the bit line pair is suppressed without using a delay circuit. Thus, the destruction in the memory cell data at the time of multiple selection of the word line is prevented without sacrificing the access time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a word line connected to a bit line load transistor and a word line connected to a decoder, which can prevent data destruction due to multiple selection of word lines. Line and memory cells arranged in a matrix so as to be selected by the bit line and the word line, and the memory cell activated by the selection of the word line and the bit line is a target of read / write. The present invention relates to an improved semiconductor memory device.

[0002]

2. Description of the Related Art As shown in FIG. 1, a conventional semiconductor memory device has a pair of bit lines BL and BLb to which bit line load transistors TN1 and TN2 are connected and a word line WL0 to WL511 to which a subsequent decoder is connected. And memory cells MC0 to MC511 arranged in a matrix so as to be selectively selected by the bit line and the word line, and an address buffer circuit group (ADB) that generates a complementary signal of an address signal input from the outside. Group) 10 and a predecoder group (P-DEC group) 12 that receives complementary signals from the address buffer circuit group 10 and generates a 1 / N selection signal.
And a row decoder (R-DE that selectively selects a word line in response to a 1 / N selection signal from the predecoder group 12).
C) 14 and a read / write circuit (not shown) and other peripheral circuits.

Each address buffer circuit which constitutes the address buffer circuit group 10 generates complementary signals x ₀ and x _0b of the address signal X 0 input from the outside, for example, as shown in FIG. 2 for the external address signal X _0. Is configured.

Further, each of the predecoder groups 12 is formed.
The predecoder is shown in FIG. ₀, X_0b, X₁, X
_1bThe address buffer circuit group
Complementary signal x from 10₀, X_0b, X₁, X_1bReceived
1 / N selection signal a₁, A₂, A₃, A_FourWill generate
It is configured as

Further, the row decoder 14 is shown in FIG.
N selection signals A (a _{1 to} a ₄ ), B (b _{1 to} b ₄ ), C
(C ₁ ~c _4), as will be exemplified D (d ₁ ~d _4), receives 1 / N selection signals A, B, C, and D, alternatively configured to select the word line WL Has been done.

In such a conventional semiconductor memory device, when an external address signal (X0, ...) Is input, the address buffer circuit group 10 and the predecoder group 1 are inputted.
After 2, the row decoder 14 finally selects only one word line WL, and along with the selection of the bit line, the memory cell MC activated by this is targeted for read / write.

However, in the process of finally selecting one word line, a plurality of word lines may be temporarily selected. For example, when the output of the address buffer circuit is inverted based on the external address signal, if the complementary signals (x ₀ , x _0b ) are both at the L level, the outputs a ₁ and a _{2 of} the predecoder for inputting them are Both become H level (however, complementary signals x ₁ = L level, x _1b = H level). Then, the row decoder 14 to which these are input
Is because the predecode signal group A (a ₁ , a ₂ , a ₃ , a ₄ ) that should originally select only one of the four wires, selects _{two of} them (a ₁ , a ₂ ). , Finally, 51
Two of the two word lines are multiply selected.
At this time, if the other predecode signal groups B, C, and D are also multi-selected, the number of word lines to be multi-selected is further increased.

As the number of word lines to be multiple selected increases,
Since the number of activated memory cells increases, the potential of the bit line is significantly lower than the bit line potential (solid line) when multiple selection does not occur as shown by the broken line in FIG. This shows a case of calling cell data in which BL = H level and BLb = L level as values). Therefore, there is a problem that not only the reading of the finally selected memory cell is hindered but also the data in the memory cell is destroyed in the worst case. That is, depending on the number of data of 1 and 0 stored in the multiple-selected memory cell and the ratio thereof, the bit line potential largely moves to the state opposite to the data of the memory cell. As a result, the contents of the memory cell and other memory cells are rewritten depending on the amount of movement, and the data is destroyed.

In order to prevent this, the conventional method shown in FIG.
As described above, the delay circuit DLY is provided in the address buffer circuit.
As shown in FIG. 6, the output of the address buffer circuit is complementary.
Signal x ₀, X_0bShould be set to a period P in which both are at H level.
By, the predecoder signal group a₁, A₂, A₃, A_Four
The multiple selection of was not made to occur.

[0010]

However, when the delay circuit DLY is provided, the selection of the word line is delayed by the delay time, which causes a delay in access time.

Further, when setting the delay time P of the delay circuit DLY, it is necessary to take into account process variations and circuit operation margins, and there is a problem that the access time is further delayed.

[0012]

According to the present invention, a bit line to which a bit line load transistor is connected, a word line to which a decoder is connected, and a matrix arranged so as to be selected by the bit line and the word line. And a memory cell that is activated by selection of the word line and the bit line, in a semiconductor memory device to be read / written, the word line detecting multiple selection of a plurality of word lines. The object is achieved by providing a detection circuit and a variable load circuit that controls the impedance of the bit line load based on the output of the word line detection circuit.

Further, there is provided means for deactivating the word line detection circuit during a write period or after a lapse of a predetermined time from an address call during a read period.

Also, the variable load circuit pulls up the bit line when multiple selections of a plurality of word lines are made.

[0015]

In the present invention, the word line detection circuit for detecting the multiple selection of a plurality of word lines is provided, and the impedance of the bit line load is controlled based on the output of the word line detection circuit. When multiple lines are selected, a decrease in bit line potential can be suppressed. Therefore, it is not necessary to provide a delay circuit as in the conventional case, and it is possible to prevent the data destruction of the memory cell due to the word line multiple selection without sacrificing the access time.

If a means for inactivating the word line detection circuit is provided after a predetermined time has passed from the address call during the write period or the read period, the current consumption by the word line detection circuit is reduced. It can be reduced.

Further, when the variable load circuit pulls up the bit line when multiple word lines are selected, the impedance of the bit line load can be easily changed.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

In this embodiment, as shown in FIG. 7, a bit line pair BL and BLb to which bit line load transistors TN1 and TN2 similar to the conventional one are connected, and word lines WL0 to WL511 to which a row decoder 14 is connected. , The bit line B
L and BLb and memory cells MC0 to MC511 arranged in a matrix so as to be selectively selected by the word lines WL0 to WL511, the word line WL0
A word line detection circuit 20 for detecting multiple selection of a plurality of word lines in a semiconductor memory device in which a memory cell activated by selection of WL511 and bit lines BL, BLb is a target of read / write; Based on the output of the word line detection circuit 20, a variable load circuit 30 is provided for pulling up the bit line and controlling the impedance of the bit line load at the time of multiple selection of a plurality of word lines.

The word line detection circuit 20 includes a transistor TP3 connected to the power source Vdd and each word line WL0 to WL0.
Transistor TNS0 connected to WL511, respectively
-TNS511 and transistors TNS0-TNS51
1 has one terminal connected to the transistor TP3 or transistors TP4 and TN for connecting to the power supply voltage Vdd.
5, and the multi-selection detection signal LC is higher than the power supply voltage Vdd by TP only when two or more word lines are selected.
1 and TP2 are lower than the potential (Vdd-Vtp) lower by VTp.

The clock signal φ supplied to the transistors TP4 and TN5 controls the active state of the word line detection circuit 20. That is, when the clock signal φ is at the L level, the word line detection circuit 20 is deactivated,
The multiple selection detection signal LC is fixed at the H level. on the other hand,
When the clock signal φ is at the H level, the transistors TNS0 to TNS5 whose conduction state is determined by the word line are set.
11 and the transistor TP3, the multiple selection detection signal L
The potential of C is determined as above.

Here, the clock signal φ is a signal generated by a clock generator (not shown), is generated by detecting a change in address, and has a fixed time T from the address call during the write period and the read period. After the lapse of time, the word line detection circuit 20 is deactivated by fixing it to the L level in order to reduce current consumption.

The variable load circuit 30 controls the conduction of the transistors TP1 and TP2 by the multiplex selection detection signal LC, and overlaps the conduction of the bit line load transistors TN1 and TN2, and the bit line load transistors TN3 and TN4 control the bit. Pull up the line pair BL, BLb.

The word line detection circuit 20 functioning in this way
The circuit operation including the variable load circuit 30 and the variable load circuit 30 will be described in detail with reference to FIG.

When the selection shifts from the word line WL511 to the word line WL0 during the active period of the clock signal φ at the H level, the row decoder 14 causes multiple selection, and the word lines WL0 and WL511 and other word lines are selected. Consider the case where both of them temporarily become H level. Then, the bit line potential tends to largely decrease as described in the conventional example shown by the broken line in FIG.

On the other hand, the transistors TNS0 and TNS51
When 1 and the like are turned on at the same time, the potential of the multiple selection detection signal LC drops to Vdd-Vtp or less. Then, the transistors TP1 and TP2 receiving this at their gates become conductive,
Pull-up transistors TN3 and TN4 are connected in parallel to the bit line load transistors TN1 and TN2, respectively, to more strongly pull up the bit lines BL and BLb.
As a result, the amount of decrease in the bit line potential can be suppressed.

In this case, the inversion phenomenon of the potential of the bit line pair may occur as in the conventional example, but the bit line potential itself is high,
Since the potential difference between the bit line pair can be suppressed to a small value, the contents of the memory cell will not be destroyed. Further, at the same time when the period of multiple selection is over, the bit line load is restored to the same level as the conventional one, so that the data of the selected cell appears on the bit line promptly. Therefore, the problem of always strengthening the pull-up is also avoided.

Further, if multiple selection does not occur, the transistors TNS0 to TNS511 do not become conductive more than once at the same time, so the multiple selection detection signal LC
Holds a potential of Vdd-Vtp or higher, and the bit line load behaves as in the conventional case.

In the present embodiment, the word line detection circuit 20 is deactivated by the clock signal φ after a predetermined time has elapsed from the address call during the write period or the read period, so that the word line detection circuit 20 is deactivated. It is possible to reduce the current consumption of the detection circuit. The configuration for deactivating the word line detection circuit is not limited to this. Further, when the current consumption by the word line detection circuit does not cause a problem, it is possible to always activate the word line detection circuit.

Further, in the present embodiment, the variable load circuit pulls up the bit line when multiple selections of a plurality of word lines are made, so that the structure is simple. The configuration for changing the load of the bit line is not limited to this, and the impedance of the bit line may be controlled by other means.

Further, in the above embodiment, the bit line is configured to include the bit line pair BL, BLb.
The application target of the present invention is not limited to this, and can be similarly applied to the case where the number of bit lines is one.

[0032]

As described above, according to the present invention, it is possible to prevent the data destruction of the memory cell due to the word line multiple selection without sacrificing the access time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a conventional semiconductor memory device.

FIG. 2 is a circuit diagram showing a configuration example of an address buffer used in a conventional example.

FIG. 3 is a circuit diagram showing a configuration example of a predecoder in the same manner.

FIG. 4 is a circuit diagram showing a configuration example of a row decoder.

FIG. 5 is a diagram showing an example of a change state of a bit line potential in a conventional example.

FIG. 6 is a diagram for explaining measures in a conventional example.

FIG. 7 is a circuit diagram showing a configuration of an embodiment of a semiconductor memory circuit according to the present invention.

FIG. 8 is a diagram showing an example of a signal waveform of each part in the embodiment of the present invention.

[Explanation of symbols]

 TN1, TN2 ... Bit line load transistor BL, BLb ... Bit line pair 12, 14 ... Decoder WL0-WL511 ... Word line MC0-MC511 ... Memory cell 20 ... Word line detection circuit LC ... Multiple selection detection signal 30 ... Variable load circuit φ ... Clock signals TN3, TN4 ... Pull-up transistors

Claims (3)

[Claims] 1. A bit line to which a bit line load transistor is connected, a word line to which a decoder is connected, and memory cells arranged in a matrix so as to be selected by the bit line and the word line. A word line detection circuit for detecting multiple selection of a plurality of word lines in a semiconductor memory device in which a memory cell activated by selection of the word line and bit line is a target of read / write, and the word line detection circuit. A semiconductor memory device comprising a variable load circuit for controlling impedance of a bit line load based on an output of the circuit. 2. The method according to claim 1, wherein after a predetermined time has elapsed from the address call during the write period or the read period,
A semiconductor memory device comprising means for deactivating the word line detection circuit. 3. The semiconductor memory device according to claim 1, wherein the variable load circuit is configured to pull up the bit line when multiple selection of a plurality of word lines is performed.