JPH07169185A - Data reading and writing system for disk storage device - Google Patents

Abstract

PURPOSE:To speed-up reading and writing operations of a disk storage device by making data possible to be read-out and written-in in parallel simultaneously via plural heads without using a high-level head and related circuit. CONSTITUTION:A head selecting means 10 selects plural heads 3 simultaneously and plural conversion means 20 convert alternately a bit string signal with which data are read-out and written-in and data having a plural bits constitution via selected heads 3. Data to be read-out and written-in are stored in a temporary storage means 40 and data are read-out from and written-in to a disk 1 by shifting the timming of data transmission successively via a bus connecting means 30 between the storage means 40 and a computer and among the storage means 40 and respective conversion means 20. Data reading and writing operations are progressed to the computer while controlling data transmission between the storage means 40 and the computer with bus connecting means 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data read / write system of a disk storage device for simultaneously reading / writing data to / from a disk through a plurality of heads in parallel.

[0002]

2. Description of the Related Art Disk storage devices such as fixed disk devices are widely used as external storage devices for computers, but on the other hand, they have the advantage that their storage capacities are significantly larger than the internal memory of computers. Because of the drawbacks involved, high-speed read / write operations are always required.
This is a problem common to storage devices that use tapes, disks, drums, etc. as magnetic recording media, and there is a limit to the speed at which data can be read and written via one head. Means for reading and writing data using heads have been known for some time.

In a typical example of such a conventional technique, a head is provided for each bit to read and write a plurality of bits at the same time by utilizing the fact that data to be read and written by a storage device has a plurality of bits. For example, it is common to use 8 heads to read / write 8-bit data, that is, 1-byte data collectively. More specifically, at the time of writing, each data is divided into a plurality of bits, and each bit is converted into 0 or 1 on a disk recording medium through a corresponding head.
Are simultaneously written with a code pattern representing the above, and at the time of reading, a plurality of bits simultaneously read through a plurality of heads are edited into one data. As a result, the time required to read / write data is 1 / the number of heads, for example, 1/8.
Is shortened to.

[0004]

However, in the above-mentioned prior art, not only is mechanical displacement or misalignment easily caused between a plurality of heads, but also data is divided into a plurality of bits or conversely a plurality of bits. Since the operation characteristics of the circuit for editing bits into data, especially the operation delay characteristics of the amplification circuit for the read signal and write signal for each bit, are likely to vary, it is very mechanical and electrical. Although precise adjustment is required, it is not suitable for a small-sized and inexpensive disk storage device that is mass-produced for a personal computer or the like even though it is suitable for a high-grade and expensive external recording device.

As a means for solving this problem, for example, Japanese Patent Laid-Open No.
As disclosed in Japanese Patent Publication No. 2785, there is known a conventional technique in which writing and reading of each bit are almost synchronized, but (a) a bit error occurs in one head due to a defect of a recording medium. Then, the bit signals related to other heads are also affected and the reliability decreases.
(b) Since the bit signal easily varies among a plurality of heads, the storage density of bit data cannot be increased to the full performance of the head or recording medium, which is disadvantageous in terms of storage capacity.
(c) It is still necessary to adjust the write and read timings of bit data by each head, and the head and its related circuits are still insufficient in terms of simplification because they are likely to be misaligned during operation.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and enable simultaneous reading and writing of data through a plurality of heads while using a simple head and its related circuit, thereby speeding up the reading and writing operation of a disk storage device. is there.

[0007]

In the data read / write system of the present invention, the above object is to provide a head selecting means for simultaneously selecting a plurality of heads for reading and writing data, and a plurality of heads corresponding to the heads selected by the head selecting means. Conversion means for mutually converting a bit string signal for reading and writing data through each head and data of a plurality of bits, storage means for temporarily storing read / write data, and between this storage means and the computer and each conversion means. Using the bus connecting means inserted in the data transfer path, the data is read and written to the computer while sequentially shifting the timing of data transfer through the bus connecting means between each converting means and the storing means to the disk. Is achieved by advancing the read / write operation while controlling the data transfer between it and the storage means by the bus connection means.

In the system of the present invention having the above configuration,
Data units forming data are sequentially recorded at the same circumferential position in a plurality of tracks corresponding to the heads simultaneously selected by the head selecting means so as to be continuous on a logical address designated by the computer to the disk storage device. It is the most rational and advantageous to do. Also, it is possible to simultaneously select a plurality of heads, one head provided for each disk surface, by the head selecting means, as usual, but a plurality of heads are provided for each disk surface and these heads are simultaneously selected. You may make it select.

Further, as an advantageous embodiment of the method of the present invention, when reading / writing data from / to the disk, addresses in which data units in the data are interdigitated in the memory means in the order of a plurality of heads simultaneously selected by the head selecting means Are sequentially stored in the storage means, and when transferring data to and from the computer, the data units are sequentially transferred in the order of consecutive addresses in the storage means, or when reading and writing data to the disk, the data units are stored in the storage means by the head selecting means. It is preferable that the heads to be selected at the same time are stored at consecutive addresses, and when the data is transferred to and from the computer, the address in the storage means is switched in the order of a plurality of heads and the data units are sequentially transferred.

[0010]

The system of the present invention does not employ a means for simultaneously reading and writing a plurality of bits constituting data as in the prior art described above, but stores data in a corresponding track in a disk via a plurality of heads in the same manner as a normal disk storage device. By reading and writing individually through each head, but simultaneously in parallel through multiple heads, it is possible to eliminate the need for synchronization of operations between multiple heads as in the past, and to mechanically operate the heads and related circuits. Or eliminates the need for precision electrical adjustments. Therefore, in the present invention, as described in the above-mentioned configuration, the head selecting means simultaneously selects a plurality of heads for reading and writing data, and the converting means is used for each head to serially read and write a plurality of bits constituting each data. Converts bit string signals and data to and from each other.

Next, in the method of the present invention, a bus connecting means is provided for controlling the data transfer between the storage means for temporarily storing the read / write data and the plurality of converting means, and when the data is read / written from / to the disk. The function of sequentially shifting the timing of the data transfer between the plurality of conversion means and the storage means is given to this, so that the plurality of sets of the head and the conversion means are operated independently of each other and the head and the conversion means are operated independently of each other. Smoothly transfer data between them.

Further, according to the present invention, for the host computer, a data read / write operation is performed while controlling the data transfer between the host computer and the storage means by the bus connection means, so that a plurality of simultaneously selected computers can be selected from the viewpoint of the computer. The plurality of tracks corresponding to the head are regarded as one high recording density track so that data can be read and written in the same manner as in a normal disk storage device.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a structural circuit diagram showing an internal configuration example including a mechanical portion of a disk storage device suitable for carrying out the read / write system of the present invention, and FIG. 2 is a diagram showing a plurality of tracks corresponding to a plurality of heads simultaneously selected in the present invention system. FIG. 3 is an exploded view of a main part of a disk showing an example of the arrangement of sectors, FIG. 3 is a circuit diagram showing an example of the configuration of bus connection means, FIG. 4 is a storage area allocation diagram showing an example of how data is stored in the storage means, and FIG. FIG. 6 is a circuit diagram showing a different configuration example of the bus connecting means corresponding to FIG. 4. It should be noted that in the present invention, at the same time, an arbitrary number, usually 2 to 8
Although it is possible to select one head, it is assumed that two heads are simultaneously selected for simplification of the drawings in the following embodiments.

The mechanism of the disk storage device, the main part of which is simply shown in the upper part of FIG.
A spindle motor 2 for driving them at a constant speed, a total of four heads 3 provided for each disk surface, a swing arm 4 for carrying them in common via a thin leaf spring, and a drive arm for driving the same. An actuator 5 such as a voice coil motor is included, and the drive circuit 6 drives the actuator 5 according to control data CD received from the processor 7 to move the head 3 to a desired radial position of the disk 1 and position it there. You can do it. In the illustrated example, one head 3 is provided for each disk surface, but by incorporating this into a so-called slider supported at the tip of the above-mentioned leaf spring, two to several disks are provided for each disk surface. It is also possible to arrange the individual heads 3.

The head selecting means 10 used in the method of the present invention receives a head selecting command HS of one to several bits from the above-mentioned processor 7, and accordingly, a plurality of heads corresponding to different disk surfaces or the same disk surface described above are provided. In the embodiment, the two heads 3 are selected at the same time, and the read / write circuit 11 shown on the lower side thereof receives from the processor 7.
According to the bit read / write command RW, the plurality of heads 3 are put into a reading state or a writing state. Further, the two signal processing circuits 12 respectively receive the read signal RS of the data from the read / write circuit 11 as usual, demodulate the signals RS and separate the synchronous clocks, and then give the converted signals to the conversion means 20 and vice versa. A data write signal WS is given to the read / write circuit 11 from the means 20.

According to the number of heads 3 which are simultaneously selected by the head selecting means 10, two converting means 20 used in the method of the present invention are provided in the illustrated embodiment.
It is a kind of sequence circuit that decodes RS into a predetermined bit string signal and then converts it into data, and conversely converts the data into a bit string signal and then encodes into a write signal WS. A small memory unit for temporarily storing the data before conversion is incorporated, and this memory unit is connected to the bus connection means 30 via a data bus DB having, for example, 8 or 16 bits. In addition, this conversion means
20 and the signal processing circuit 12 described above are given a clock pulse CP for designating their operation from the processor 7, for example.

The bus connecting means 30 controls data transfer between the converting means 20 described above and the storing means 40 which is usually a RAM shown in the lower right part of the figure.
In addition to the connection via the DB as described above, the storage means 40 is connected to the address bus AB and the data bus DB, and the processor 7 and the system bus SB of the disk storage device, respectively. Further, it is connected to a host computer (not shown) via the system bus SB and the interface circuit 8 to control the data transfer between the computer and the storage means 40. Further, in this embodiment, the bus connecting means 30 is supplied with operation designation data and the like from the processor 7 via the control bus CB, and is supplied with a clock pulse Cp different from the above for designating the data transfer rate.

In addition, a reference information reading circuit 9 is incorporated in the disk storage device, which receives a read signal RSa of an analog waveform before demodulation by the signal processing circuit 12 so-called collation data indicating the current position of the head 3. And servo information are detected and given to the processor 7 as detection data DD. The processor 7 which receives this is for the overall control in the disk storage device and outputs the above-mentioned control data CD designating the position of the head 3 to the drive circuit 6 of the actuator 5 based on the detection data DD, and also selects the head. A head selection command HS is issued to the means 10 and a read / write command RW is issued to the read / write circuit 11, and the interface circuit 8 and the system bus SB are issued.
Commands are exchanged with the computer via the, and the specified contents of the data to be read and written are accepted. In practice, it is often advantageous to separate the processor 7 into a control processor and a data processor, but in FIG. 1 this is shown as a single processor for convenience.

Before explaining an example of the structure of the bus connecting means 30 shown in FIG. 3, the arrangement of sectors for recording data units in a track will be described with reference to FIG. The two tracks Ta and Tb shown in FIG. 2 correspond to two heads 3 in this embodiment, which are simultaneously selected by the head selecting means 10.
In the present invention, these tracks Ta and Tb are regarded as a single track from the computer side and data is read and written. In the illustrated example, reference information RI including the collation data for detecting the position of the head 3 and the servo information is written in the disk 1 in the circumferential direction, and for example, 512 is written between them.
Sectors S0, S1, S2, S3, etc. for recording byte data units are set by so-called formatting. As shown below, each sector S is composed of a collation part ID, a gap part G, a data part DT, a gap part G, etc. Then, the data unit is recorded in the data part DT.

In the system of the present invention, as described above, the track Ta
And Tb are regarded as a single track from the computer side so that data can be read and written, in the same circumferential position in both tracks Ta and Tb above the so-called logical address specified by the computer to the disk storage device. It is rational to record the data units in a continuous order with the two sectors S0, S1, S2, S3, etc. arranged in the order of both tracks Ta and Tb in the sector arrangement of FIG. It is preferable to store the data so that the addresses are consecutive.

FIG. 3 shows an example of the configuration of the bus connecting means 30 when the data units of read / write data are stored in the storage means 40 in the above-mentioned logical address order. Bus connection means as shown
30 is three bus connection circuits 31 and three addressing circuits
32, one register 33 each, a sequence control circuit 35, and an address selection circuit 36. Two bus connection circuits 31 are inserted in the data transfer path between the storage means 40 and each conversion means 20 via the data bus DB, and the other bus connection circuit 31 is connected to the computer via the data bus DB and the system bus SB. Is inserted in the data transfer path. The address designating circuit 32 includes an address pointer 32a and a transfer counter 32b, is connected to the processor 7 via a control bus CB, and each address pointer 32a is connected to an address selecting circuit 36 via an address bus AB. The register 33 that receives the control bus CB is the address pointer 32a of the two addressing circuits 32 via the register bus RB.
Connected with. The sequence control circuit 35 receives the control bus CB and outputs the timing signal TS to each addressing circuit 32 individually.
The selection data SD is issued to the address selection circuit 36, respectively.

A clock pulse Cp for designating a data transfer rate is given to the bus connecting means 30 from the processor 7, and in the embodiment shown in the drawing, the clock pulse Cp is also given to the memory section 21 and the interface circuit 8 in the converting means 20. . The frequency of this clock pulse CP is preferably set to be considerably higher than that of the clock pulse CP for reading / writing data from / to the disk 1. The storage means 40 is each bus connection circuit 31 and data bus
It is connected via DB via the address selection circuit 36 and the address bus AB. In addition, the bus connection circuit 31 includes a bidirectional bus driver, and the data transfer direction designation and the connection operation command thereof are specified by the corresponding address designation circuit in this embodiment.
It is designed to be given from 32.

In the bus connecting means 30 of FIG. 3 configured as described above, at the time of reading the data, the data is read from the two converting means 20 via the corresponding bus connecting circuit 31 and the data is alternately stored for each unit first. After being transferred to and stored in the storage unit 40, the data read from the storage unit 40 through the bus connection circuit 31 corresponding to the interface circuit 8 from the tracks Ta and Tb in FIG. Then, the data is first transferred from the computer to the storage means 40 and stored therein, and then the data is alternately transferred from the storage means 40 to the two conversion means 20 and written in the tracks Ta and Tb. Less than,
The operation of the bus connecting means 30 related to this reading and writing will be specifically described.

A unique address on the control bus CB is assigned to each address designating circuit 32 and register 33. Before starting the read / write operation, the data designated by the computer from the processor 7 via the control bus CB is first stored. The head address is written in the address pointer 32a, the number of data units or the number of sectors designating the data length is written in the transfer counter 32b, and the number of bytes in the data unit is written in the register 33. However, in this embodiment, the transfer counter 32b of the two addressing circuits 32 corresponding to the converting means 20 has a half of the above-mentioned number of sectors, and one address pointer 32a has a byte of a data unit at the head address. It is better to write the added addresses respectively.

Further, in parallel with this, the processor 7 referring to the detection data DD by the reference information reading circuit 9 of FIG.
Thus, the head 3 is moved to the tracks Ta and Tb in FIG. 2 corresponding to the designated head address in the above-described manner, and the head 3 is accurately positioned thereon. The position of the head 3 is sequentially shifted by one track pitch as needed each time data is read from or written to these tracks.

At the time of reading / writing data, the sequence control circuit 35 selectively supplies the timing signal TS to the addressing circuit 32 to operate it, and also supplies the selection data SD to the address selecting circuit 36 to store the corresponding address bus AB. Connect to means 40. When reading data, first, the two addressing circuits 32 connected to the converting means 20 are alternately operated. Each addressing circuit 32 has a corresponding conversion means 20.
The address pointer is synchronized with the clock pulse Cp with the data transfer direction specified and the connection operation commanded.
The address to be put on the address bus AB is incremented from 32a. At the same time, from the memory unit 21 of the conversion means 20, for example, 1
The read data for each sector is transferred byte by byte to the storage means 40 via the corresponding bus connection circuit 31 and the data bus DB and stored at the above address.

In this way, after the transfer of the data unit for one sector is completed, for example, one address designating circuit 32
1 is subtracted from the count value in the transfer counter 32b, the number of bytes of the data unit stored in the register 33 is added to the address pointer 32a, and then the operation is switched to the other address designation circuit 32. By alternately switching the operations of the two addressing circuits 32 and the corresponding bus connection circuits 31, the two heads 3 of FIG.
The data read simultaneously from Tb and Tb are stored in the storage means 20 from the two conversion means 20 alternately in the data unit for one sector in this embodiment, so that they are continuous on the logical address as seen from the computer. .

When the count values in the transfer counters 32b of the above-mentioned two addressing circuits 32 become 0, the conversion means
The transfer of the read data from 20 to the storage means 40 is completed,
Then, another addressing circuit 32 is operated to transfer this data from the storage means 40 to the computer through the corresponding bus connection circuit 31, system bus SB and interface circuit 8. Since the transfer operation at this time is the same as that described above, detailed description thereof will be omitted. However, in this embodiment, since the read data is stored in the storage means 20 in the order of the logical address as seen from the computer, the address of the address designating circuit 32 is Pointer 32
The count value in the transfer counter 32b may be subtracted one by one each time the transfer of the data unit is completed, while advancing the address to be put on the address bus AB from a simply in synchronization with the clock pulse Cp. Of course, the data reading operation is completed when the count value of the transfer counter 32b becomes zero.

Contrary to the above, the operation at the time of writing data in this embodiment is such that, first, one addressing circuit 32 corresponding to the computer is operated to store the data to be written from the computer via the corresponding bus connection circuit 31 from the computer. The data is transferred to the storage means 40 and stored in the order of logical addresses, and then the two addressing circuits 32 are alternately operated to store the data from the storage means 40 through the corresponding two bus connection circuits 31 into the two conversion means 20. The data units are alternately transferred to the memory unit 21 and stored in the memory unit 21. Of course, this causes data to be written in parallel to the tracks Ta and Tb of FIG. 2 via the two heads 3 of FIG.

Before describing the configuration and operation of the bus connecting means 30 shown in FIG. 5, an example of allocating storage areas in the storage means 40 will be described with reference to the corresponding FIG. As shown in the figure, the area in the storage means 40 is divided into two areas 41 and 42 represented by a track Ta and a track Tb, and an address for storing each data unit inside them is a sector in the track Ta or Tb. Allocate in the order in which S0 to Sn are arranged.

Bus connection means 30 of FIG. 5 corresponding to FIG. 4
3 is provided with three bus connection circuits 31 and two address designation circuits 32 corresponding to the conversion means 20, as in FIG. 3, but another address designation circuit corresponding to the computer is provided.
34 is provided and the register 33 is attached to this side. The address designating circuit 34 includes two address pointers 34a and one transfer counter 34b.
34a receives the register bus RB from the register 33 and gives its address to the address selection circuit 36, respectively. The address selection circuit 36 is different from that of FIG. 3 only in that four addresses are switched and given to the storage means 40. The sequence control circuit 35 is the same as in FIG.

In addition to the above, the bus connecting means 30 of this embodiment will be described with respect to the points slightly different from FIG. In addition to the above-described bidirectional bus driver, the two bus connection circuits 31 corresponding to the conversion means 20 incorporate a so-called FIF0 (First In First Out) type register of the first-in first-out type as a data storage means. The conversion means 20 is provided with only the clock pulse CP for designating the data read / write speed through the head without providing the above-mentioned memory section, and the FIF0 of the bus connection circuit 31 is supplied via the data bus dB which operates in synchronization with this. Connect with register. Such a bus connection circuit 31 can of course be used in the embodiment of FIG. The interface circuit 8 for connection with the computer is also supplied with the clock pulse Cp having a higher frequency in this embodiment.

The bus connecting means of FIG. 5 configured in this way
Even at 30, the addressing means 32 and 34 are initialized from the processor 7 via the control bus CB before the start of the read / write operation.
At this time, the address pointers of the two address designating means 32
The start address of the partial area 41 in the storage means 40 is written in one of the 32a and the start address of the partial area 42 in the other, and two address pointers 34 in the address designating means 34 are written.
3 is different from the embodiment of FIG. 3 only in that the head addresses of the partial areas 41 and 42 are respectively written in a. The transfer counter 32b in the address specifying means 32, the register 33, and the transfer counter 34b in the address specifying means 34 are initialized. The procedure is the same as in the previous embodiment.

The transfer procedure of the read / write data is similar to that of the embodiment shown in FIG. 3, and when transferring the data between the conversion means 20 and the storage means 40, two data are transferred by the timing signal TS from the sequence control circuit 35. When the address designating means 32 is alternately operated for each data unit and the data is transferred between the storage means 40 and the computer, 2 in the address designating means 32 is transferred.
The address pointers 32a may be operated alternately for each data unit. The point that the number of bytes of the data unit in the register 33 is added to the address at the end of each operation of the address pointer 32a is also the same as the previous embodiment.

In any of the embodiments described above,
A plurality of heads 3 selected by the head selecting means 10 of FIG.
Converting means while advancing read / write operations in parallel via
The bit string signal and the data are mutually converted by 20 and the timing of data transfer between the plurality of conversion means 20 and the storage means 40 is sequentially shifted for each data unit by the bus connection means 30, and further between the computer and the storage means 40. The data read / write operation of the disk storage device can be advanced at high speed and smoothly while controlling the data transfer of (1) through the bus connection means (30).

The present invention is not limited to the above embodiments and can be implemented in various modes. For example, instead of continuously reading and writing all of the data specified by the computer, it is actually better to divide the data into multiple tracks corresponding to the heads that are selected at the same time, and to perform the reading and writing operation for each data portion. In many cases In this case, the address selection circuit 32 in the bus connecting means 30 in FIG. 3 or FIG.
34 or register 33 can be initialized.

In some cases, it may be desirable for the conversion means 20 to have a function of reading the collation part ID in each sector S of FIG. 2. In this case, each conversion means 20 is connected to the processor 7 via the system bus SB. It is good to connect. Further, the present invention can be applied to a so-called CDR type disk storage device in which the data linear recording density in a track is substantially constant regardless of the radial position in the disk surface. The frequency of the clock pulse CP given from the processor 7 to the signal processing circuit 12 and the conversion means 20 may be switched for each so-called zone composed of a plurality of tracks.

[0038]

As described above, in the data read / write method of the disk storage device of the present invention, the head selecting means for selecting a plurality of heads to read / write data in parallel, and the bit string for reading / writing via each selected head. A plurality of conversion means for mutually converting signals and data, a storage means for temporarily storing data to be read and written, and a bus connection means inserted in a data transfer path between the storage means and the computer and each conversion means Data is read from and written to the disk while sequentially shifting the timing of data transfer via the bus connection means between each conversion means and the storage means, and for the computer, the data transfer between it and the storage means is performed by the bus connection means. The following effects can be obtained by advancing the read / write operation while controlling by.

(A) A plurality of heads are simultaneously selected by the head selecting means and a converting means is provided for each head, and a plurality of sets of combinations of the head and the converting means are operated independently of each other, and data of By advancing the reading and writing in parallel at the same time, the read / write operation is speeded up to be twice as many as the heads selected at the same time as compared with a normal disk storage device that reads and writes data by using the heads one by one, and the effective performance of the disk storage device is improved. The access time can be shortened.

(B) A bit string signal and data for serially reading and writing a plurality of bits constituting each data by providing conversion means for each head simultaneously selected by the head selection means as in a normal disk storage device. By performing mutual conversion between the two, parallel adjustment of mechanical or electrical precision is achieved by using a high-grade head or its related circuit to synchronize the operation between multiple heads like the conventional bit parallel read / write method. The disk storage device can be mass-produced at low cost without the need to perform it.

(C) When reading / writing data from / to the disk, the bus connection means is provided with the function of sequentially shifting the timing of data transfer between the plurality of conversion means and the storage means, thereby converting the head and the conversion means. It is possible to allow a plurality of sets of means to perform independent read / write operations while smoothly performing data transfer between the conversion means and the storage means in parallel.

(D) For the computer, data transfer between the computer and the storage means is controlled by the bus connection means while the data read / write operation of the disk storage device is proceeded, so that the simultaneous selection is made from the viewpoint of the computer. A plurality of tracks corresponding to a plurality of heads can be regarded as one high recording density track so that data can be read and written in exactly the same manner as in a normal disk storage device.

[Brief description of drawings]

FIG. 1 is a configuration circuit diagram illustrating an internal configuration including a mechanical unit of a disk storage device suitable for implementing a data read / write method according to the present invention.

FIG. 2 is a development view of a main part of a disk showing an example of an arrangement of sectors in a plurality of tracks corresponding to a plurality of heads simultaneously selected in the method of the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a bus connecting unit.

FIG. 4 is a storage area allocation diagram showing an example of a procedure for storing data in a storage unit.

FIG. 5 is a circuit diagram showing a different configuration example of the bus connecting means corresponding to FIG.

[Explanation of symbols]

1 disk 3 head 7 processor incorporated in disk storage device 10 head selecting means 20 converting means 21 memory section in converting means 30 bus connecting means 31 bus connecting circuit of bus connecting means 32 addressing circuit in bus connecting means 33 bus Register in connection means 34 Addressing circuit in bus connection means 35 Sequence control circuit in bus connection means 36 Address selection circuit in bus connection means 40 Storage means or RAM 41 Partial area in storage means 42 Part in storage means Area AB Address bus for storage means CB bus Control bus for connection means CP Clock pulse for specifying read / write speed via the head Cp Clock pulse for specifying data transfer speed DB Data transfer data bus HS Head selection command RS Data read signal RW Read / write command Ta The track corresponding to the heads that are selected simultaneously. Write signal track WS data corresponding to Tb heads simultaneously selected

Claims (5)

[Claims] 1. A head selecting means for simultaneously selecting a plurality of heads for reading and writing data, and a plurality of bit string signals for data reading and writing via each head provided in a plurality corresponding to the heads selected by the head selecting means. A conversion means for mutually converting bit-structured data, a storage means for temporarily storing data to be read and written, and a bus connection means inserted in a data transfer path between the storage means and the computer and each conversion means are used. , Data is read from and written to the disk while sequentially shifting the timing of data transfer via the bus connection means between each conversion means and the storage means, and for the computer, data transfer between the storage means and the bus connection means is performed. A data read / write method for a disk storage device, which is characterized in that the data read / write operation is carried out while being controlled by. 2. A system according to claim 1, wherein when reading / writing data from / to a disk, a unit of data is stored in an address interdigitated in the storage means in the order of a plurality of heads simultaneously selected by the head selection means. A data read / write method for a disk storage device, wherein data units are sequentially transferred in the order of consecutive addresses in the storage means during data transfer with a computer. 3. A system according to claim 1, wherein when reading / writing data from / to a disk, a data unit is stored in a storage means at consecutive addresses for each head simultaneously selected by a head selection means, and data is transferred to a computer. A data read / write system for a disk storage device, wherein the data unit is sequentially transferred while the address in the storage means is switched in the order of a plurality of heads to proceed. 4. A data read / write system for a disk storage device according to claim 1, wherein a plurality of heads corresponding to different disk surfaces are simultaneously selected by the head selection means. 5. A data read / write system for a disk storage device according to claim 1, wherein a plurality of heads corresponding to the same disk surface are simultaneously selected by the head selecting means.