JPH07162754A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To simplify constitution, to, reduce the load of a driving circuit and to discharge unnecessary electric charges by discharging the unnecessary electric charges to a substrate immediately under a horizontal transfer register part. CONSTITUTION:This device is provided with light receiving parts 32 to be picture elements, vertical transfer register parts 33 corresponding to the columns of the light receiving parts and the horizontal transfer register part 35. Then, the unnecessary electric charges are discharged to the substrate immediately under the horizontal transfer register part 35. For instance, a separation area for electrically separating an area 34 including the light receiving parts 32 and the vertical transfer register parts 33 and the horizontal transfer register part 35 and an overflow barrier provided inside the substrate immediately under the horizontal transfer register part 35 are provided and a substrate voltage HVsub different from the substrate of the area 34 is applied to the substrate immediately under the horizontal transfer register part 35. That is, since the unnecessary electric charges are discharged to the substrate immediately under the horizontal transfer register part 35, high-speed horizontal driving is unnecessitated or shortened and the load of the driving circuit 39 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 8, for example, a plurality of light receiving sections are arranged and an image pickup area 1 in which a vertical transfer register section is provided on one side of each light receiving section row, and a horizontal transfer register section 4.
IT (interline transfer) type CC equipped with
In a solid-state image pickup device for picking up an image using a solid-state image pickup device 6 such as a D image sensor, an image pickup area 1 having a larger area than a display area 11 for actually displaying an image is formed, and a shake of an image is picked up by a shake detecting unit. There has been proposed a solid-state imaging device that detects the amount and moves the display area 11 in the imaging area 1 according to the detected amount of camera shake.

That is, FIG. 8A shows the position of the display area 11 in a state where, for example, the image is not shaken, and FIG. 8B shows the position of the display area 11 in the state where the image is shaken in the Y direction. Areas 12 and 13 indicated by diagonal lines above and below the display area 11 are unnecessary charge areas that are not output as an image.

FIG. 9 shows an IT type CCD with a camera shake countermeasure.
The solid-state image sensor 6 is shown. This CCD solid-state image sensor 6 is
A signal charge storage unit that stores signal charges generated by photoelectric conversion, that is, a plurality of light receiving units 2 that are pixels and a signal charge that is provided on one side of each light receiving unit row and that is read out from the light receiving units 2 is vertically transferred. A vertical transfer register unit 3 having a CCD structure, a horizontal transfer register unit 4 for horizontally transferring each signal charge, and a final stage of the horizontal transfer register unit 4 for detecting and amplifying the horizontally transferred signal charge. A data detection unit, that is, an output unit 5 is provided. The charge-voltage conversion unit, that is, the floating diffusion region in the output unit 5 is connected to the reset drain RD via the reset gate unit RG in order to reset after outputting the signal charge of each pixel.

In the solid-state image pickup device having the CCD solid-state image pickup device 6 as described above, when image pickup is started, the shake detection means (that is, the shake detection circuit) 7 detects the amount of shake during image pickup. This camera shake detection data is supplied to the drive means (that is, CCD driver) 8 of the solid-state image sensor 6, and the display area 11 is determined according to the camera shake detection data.

The driving means 8 reads the charge accumulated in the light receiving section 2 to the vertical transfer register section 3 and a read pulse voltage VT, and each charge read to the vertical transfer register section 3 at a normal speed. A normal vertical transfer pulse voltage (for example, a 4-phase clock pulse) VLC for vertical transfer to the horizontal transfer register unit 4 and each charge read to the vertical transfer register unit 3 are vertically transferred to the horizontal transfer register unit 4 at high speed. High-speed vertical transfer pulse voltage (for example, four-phase clock pulse) VHC, normal horizontal transfer pulse voltage (for example, two-phase clock pulse) HLC for horizontally transferring each charge transferred to the horizontal transfer register unit 4 at a normal speed, horizontal High-speed horizontal transfer pulse voltage (for example, two-phase clock pulse) HH for horizontally transferring each charge transferred to the transfer register unit 4 at high speed
C, reset pulse voltage RP and reset gate unit RG
Is supplied with a switch pulse voltage SP.

Here, for example, as shown in FIG. 8B, it is assumed that the display area 11 is determined in the imaging area 1. The vertical blanking period V− shown in FIG.
At time t ₂ of BLK1, the read pulse voltage VT shown in the figure is supplied from the driving means 8, and the charges accumulated in each light receiving portion 2 are read out to the vertical transfer register portion 3.

Next, the driving means 8 starts the vertical blanking period V from the time t ₂ when the read pulse voltage VT is supplied.
During the high-speed transfer period THS1 until the time t ₃ when -BLK1 ends, the high-speed vertical transfer pulse voltage VH shown in FIG.
The C and the high-speed horizontal transfer pulse voltage HHC are supplied to the vertical transfer register unit 3 and the horizontal transfer register unit 4. The charges read to the vertical transfer register unit 3 are transferred at high speed vertically to the horizontal transfer register unit 4 by the high speed vertical transfer pulse voltage VHC, and further transferred at high speed horizontally at the horizontal transfer register unit 4 by the high speed horizontal transfer pulse voltage HHC. It

In the driving means 8, in the high speed transfer period THS1, each high speed vertical transfer pulse voltage VHC is set so that all the charges in the unnecessary charge area 12 in the lower stage of the display area 11 shown in FIG. 8B are transferred at high speed. And a high-speed horizontal transfer pulse voltage HHC to the vertical transfer register unit 3 and the horizontal transfer register unit 4.

The reset gate portion RG is normally in the off state, but in the high speed transfer period THS1, the switch pulse voltage SP of FIG. 10 is supplied from the driving means 8 in synchronism with the reset gate portion RG to be in the on state. As a result, the amount of unnecessary charges in the unnecessary charge region 12 that is transferred at high speed is reduced by the reset gate portion RG.
Through the reset drain RD and is not output.

Next, in the vertical video period TVK1 from time t ₃ to time t ₄ , the driving means 8 drives the normal vertical transfer pulse voltage VLC and the normal horizontal transfer pulse voltage H shown in FIG.
LC is a vertical transfer register unit 3 and a horizontal transfer register unit 4
And the signal charges in the display area 11 are normally transferred. At this time, since the reset gate unit RG is in the OFF state (however, the reset pulse RP is applied every time each signal charge is output), the signal charge of the display area 11 normally transferred within the vertical video period TVK1. Is detected by the output unit 5, amplified, and output to the outside through the output terminal 10.

[0012] Next, for the unnecessary charges of the upper unnecessary charge region 13 of the display region 11, high-speed vertical transfer pulse voltage VHC and between the first half of the time t ₄ ~t ₅ of the next vertical blanking period V-BLK2 High-speed horizontal transfer pulse voltage HHC
As a result, the data is swept from the reset gate portion RG that has been transferred at high speed and turned on to the reset drain RD, and is not output to the outside.

In the solid-state image pickup device, only the signal charges accumulated in the display area 11 thus moved according to the amount of camera shake are output to the outside.

FIG. 11 is an IT type CCD with a camera shake countermeasure.
The other conventional example of a solid-state image sensor is shown. The CCD solid-state imaging device 15 is provided with an unnecessary charge discharging gate section 16 and an unnecessary charge discharging section 17 which are continuously provided below the horizontal transfer register section 4. Since other configurations are the same as those in FIG. 9, the corresponding portions are denoted by the same reference numerals and duplicate description will be omitted.

In this CCD solid-state image pickup device 15, the unnecessary charges in the unnecessary charge regions 12 and 13 are removed from the time t _{2 to} t _{3 in} the latter half of the vertical blanking period V-BLK1 and in the first half of the next vertical blanking period V-BLK2. High-speed transfer is performed from time t _{4 to} time t ₅ , passes through the horizontal transfer register unit 4, and is swept out to the unnecessary charge discharging unit 17 via the unnecessary charge discharging gate unit 16. The unnecessary charges transferred to the horizontal transfer register unit 4 due to insufficient sweeping to the unnecessary charge discharging unit 17 are reset gate unit R by the high-speed horizontal transfer pulse voltage.
It is swept out to the reset drain RD via G.

As the IT type CCD solid-state image pickup device, a CCD solid-state image pickup device 19 having a plurality of horizontal transfer register sections 4A and 4B has been proposed as shown in FIG. Output sections 5A and 5B are connected to the final stages of the horizontal transfer register sections 4A and 4B, respectively, and a floating diffusion region which is a charge-voltage conversion section of the output sections 5A and 5B is reset drain section RD ₁ via a reset gate section RG.
Connected to RD ₂ .

[0017]

By the way, in the CCD solid-state imaging device 6 shown in FIG. 9, unnecessary charges in the regions 12 and 13 other than the charges in the display region 11 are removed from the vertical blanking periods V-BLK1, V-BLK2. High-speed transfer must be performed within the high-speed transfer time VHS1, VHS2, which is approximately half the time.

Therefore, a high-speed vertical transfer pulse voltage VHC and a high-speed horizontal transfer pulse voltage H for transferring unnecessary charges at high speed.
A large load is applied to the driving means 8 that supplies HC. As a result, the transfer efficiency is deteriorated, and some of the unnecessary charges in the unnecessary charge regions 12 and 13 and the signal charges in the display region 11 are mixed on the horizontal transfer register unit 4, and the mixed charges are output as they are, and displayed. This may cause color unevenness in the image.

The CCD solid-state image pickup device 1 shown in FIG.
5, it is necessary to widen the horizontal transfer register section 4 side by providing the unnecessary charge discharging gate section 16 and the unnecessary charge discharging section 17 for discharging the unnecessary charges connected to the horizontal transfer register section 4, At present, the solid-state image pickup device is becoming smaller due to a trade-off of yield and the like, and the yield from one wafer is poor.

Further, in the CCD solid-state image pickup device 19 having a plurality of horizontal transfer register sections 4A, 4B shown in FIG. 12, unnecessary charge discharging gate sections and a plurality of unnecessary charge discharging gate sections are continuously provided in the lower direction of the plurality of horizontal transfer register sections 4A, 4B. To provide the unnecessary charge discharging section, the pattern for forming the unnecessary charge discharging gate section and the unnecessary charge discharging section becomes complicated, and as a result, it is difficult to completely discharge the unnecessary charge.

In view of the above points, the present invention provides a solid-state image pickup device which has a simple structure and reduces the load on a drive circuit to enable discharge of unnecessary charges.

[0022]

According to the present invention, a light receiving portion 32 which becomes a pixel and a vertical transfer register portion 3 corresponding to a light receiving portion array are provided.
3 and the solid-state imaging device including the horizontal transfer register unit 35 are configured to discharge unnecessary charges to the substrate immediately below the horizontal transfer register unit 35.

When discharging the unnecessary charges, the driving of the horizontal transfer register section 35 is stopped and the unnecessary charges are discharged.

The solid-state image pickup device according to the present invention includes a light receiving section 32.
And a separation region 58 that electrically separates the region 34 including the vertical transfer register unit 33 and the horizontal transfer register unit 35,
An overflow barrier 59 is provided in the substrate 41 directly below the horizontal transfer register unit 35, and the light receiving unit 32 and the vertical transfer register unit 3 are provided on the substrate directly below the horizontal transfer register unit 35.
Substrate voltage H different from that of the substrate 51 immediately below the region 34 including 3
It is configured to apply V _sub .

According to the present invention, a solid-state image pickup device is provided with a light receiving section 32 which becomes a pixel, a vertical transfer register section 33 corresponding to a light receiving section row, and a horizontal transfer register section 35 on a semiconductor substrate 71 of the first conductivity type. In the above, a second conductivity type first semiconductor layer 74 that forms a first potential barrier is provided between the vertical transfer register section 33 and the semiconductor substrate 71, and between the horizontal transfer section register 35 and the semiconductor substrate 71. A second semiconductor layer 7 of the second conductivity type that forms a second potential barrier in the
5 is provided, and the second potential barrier is configured to be deeper than the first potential barrier.

The impurity concentration of the second semiconductor layer 75 is set lower than that of the first semiconductor layer 74.

Further, the second potential barrier is deeper than the potential barrier formed between each bit of the horizontal transfer register section 35.

[0028]

In the present invention, since unnecessary charges are discharged to the substrate 41 directly below the horizontal transfer register section 35, high-speed horizontal driving becomes unnecessary or becomes a short period, and the driving circuit 39
Burden is reduced.

Since the driving of the horizontal transfer register section 35 is stopped when the unnecessary charges are discharged, the load on the drive circuit 39 can be reduced more reliably.

Further, it is possible to prevent color unevenness of a display image due to deterioration of charge transfer efficiency.

Further, it is not necessary to provide the unnecessary charge discharging gate section and the unnecessary charge discharging section in the lower direction of the horizontal transfer register section 35, which makes it possible to miniaturize the solid-state image pickup device.

In the present invention, the area 34 including the light receiving section 32 and the vertical transfer register section 33 and the horizontal transfer register section 35 are electrically separated from each other by the separation area 58, and the inside of the substrate 41 directly below the horizontal transfer register section 35. An overflow barrier 59 is provided in the vertical transfer register by applying a different substrate voltage HV _sub to the substrate 41 immediately below the horizontal transfer register unit 35 from the substrate 51 immediately below the region 34 including the light receiving unit 32 and the vertical transfer register unit 33. Unwanted charges transferred from the portion 33 to the horizontal transfer register portion 35 can be discharged through the substrate 41 directly below the horizontal transfer register portion 35.

Further, according to the present invention, in the solid-state image pickup device, the first conductivity type barrier which forms the first potential barrier between the vertical transfer register section 33 and the semiconductor substrate 71 is used.
A second conductive type second semiconductor layer 75 that forms a second potential barrier between the horizontal transfer register section 35 and the semiconductor substrate 71. By constructing the electric charge deeper than the potential barrier of the vertical transfer register 33,
Can be transferred to the horizontal transfer register unit 35 from above, and can be discharged through the substrate 71 directly below the horizontal transfer register unit 35 over the second potential barrier 46. In this case, the vertical transfer register unit 33 and the horizontal transfer register unit 35 can use the common substrate 71.

Further, by making the impurity concentration of the second semiconductor layer 75 lower than that of the first semiconductor layer 74, it is possible to make a difference between the first and second potential barriers. At the same time, the height of the second potential barrier 46 can be set appropriately.

Further, by making the second potential barrier 46 deeper than the potential barrier formed between each bit of the horizontal transfer register section 35, blooming in the horizontal transfer register section can be prevented.

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of an IT type CCD solid-state image pickup device 31 according to the present invention. CCD solid-state imaging device 3 of this example
1 is a signal charge storage unit that stores signal charges generated by photoelectric conversion, that is, a plurality of light receiving units 32 that are pixels are arranged in a matrix, and read from the light receiving unit 32 on one side of each light receiving unit row. An imaging area 34 provided with a vertical transfer register section 33 having a CCD structure for vertically transferring signal charges, and C for horizontally transferring signal charges from the vertical transfer register section 33.
A solid-state image sensor (so-called CCD image sensor) including a horizontal transfer register section 35 having a CD structure and a data detection section provided at the final stage of the horizontal transfer register section 35 for detecting and amplifying signal charges, that is, an output section 36. Part) 37,
Further, it has a camera shake detection circuit 38 which is a camera shake detection means for detecting the amount of camera shake generated during imaging and a pulse driver or drive circuit 39 which is a drive means for driving the solid-state image sensor 37 according to a drive pulse voltage or the like. Become.

For example, in the floating diffusion region which constitutes the charge-voltage conversion unit in the output unit 36,
After outputting the signal charge for each pixel, a reset gate unit RG and a reset drain R for resetting the charge
D is connected.

Thus, in the present example, as shown in FIG. 3A, in particular, unnecessary charges are discharged into the silicon substrate 41 immediately below the horizontal transfer register section 35 for discharging the unnecessary charges in the substrate direction, that is, in the vertical direction. A so-called overflow barrier 42, which is a gate, is provided.

From the drive circuit 39, a read pulse voltage VT for reading the electric charges accumulated in the light receiving portion 32 of the image pickup area 34 to the vertical transfer register portion 33, and the electric charges read to the vertical transfer register portion 33 are vertically transferred. For example, four-phase vertical transfer clock pulses φIM _{1 to} φIM ₄ , more specifically, high-speed vertical transfer pulse voltage V for high-speed vertical transfer
HC and normal vertical transfer pulse voltage VLC for vertical transfer at normal speed, for example two-phase horizontal transfer clock pulses φH ₁ and φH ₂ for horizontal transfer of charges transferred to the horizontal transfer register unit 34, that is, normal The horizontal transfer pulse voltage HLC, the substrate voltage HV _sub limited to the substrate 41 directly below the horizontal transfer register unit 34, and the substrate voltage IV _sub limited to the substrate immediately below the imaging region 34 are supplied.

Next, the operation of the CCD solid-state image pickup device 31 will be described. First, when image pickup is started, the camera shake detection circuit 38 detects the amount of camera shake during image pickup, determines the display area 11 shown in FIG. 8B in the image pickup area 34, and outputs the camera shake detection data to the drive circuit 39. Supply to.

In the solid-state image pickup device 37, the read pulse voltage VT is supplied at the approximate intermediate time t ₁₂ of the vertical blanking period V-BLK1 shown in FIG. 2, and the charge accumulated in each light receiving section 32 is passed through the read gate section. Respectively to the vertical transfer register section 33.

Next, the unnecessary charge discharging period THS1 from time t ₁₂ to the read pulse voltage VT is supplied to the time t ₁₃ to the vertical blanking period V-BLK1 ends, to the vertical transfer register portion 33 in the imaging region 35 The high-speed vertical transfer pulse voltage VHC in the vertical transfer clock pulses φIM _{1 to} φIM ₄ is supplied, and the unnecessary charges in the unnecessary charge region 12 of FIG. 8B are transferred to the horizontal transfer register section 34 at high speed in the vertical direction.

At the same time, during the unnecessary charge discharging period THS1, water is discharged.
Horizontal transfer clock pulse φH to the flat transfer register unit 34
₁, ΦH₂Is stopped and the horizontal transfer register unit 3
The high-speed vertical transfer pulse voltage VHC is applied to the substrate 41 immediately below 4.
Synchronized substrate pulse voltage HV _subIs supplied to FIG. 3B
As shown in FIG.
Minimum potential of (φ_min) 43 and maximum potential
φ_maxThat is, the potential with the overflow barrier 42
Difference (φ_B) 44 disappears.

Therefore, the unnecessary charge regions 12 transferred at high speed from the vertical transfer register section 33 to the horizontal transfer register section 35.
The unnecessary charge e ₁ of
All are discharged to the silicon substrate 41 immediately below.

Next, in the vertical video period TVK1 from time t _{13 to} time t ₁₄ shown in FIG. 2, as shown in the figure, the normal vertical transfer pulse voltage VLC and the horizontal transfer pulse voltage VLC in the vertical transfer clock pulses φIM _{1 to} φIM ₄ are transferred. Clock pulse φH ₁ ,
The normal horizontal transfer pulse voltage HLC at φH ₂ is supplied, the signal charges in the display area 11 of FIG. 8B are normally transferred,
An output signal (output image data) is output from the output terminal 40 of the output unit 5.

FIG. 3A is a potential diagram immediately below the horizontal transfer register section 35 when the signal charges in the display area 11 are normally transferred.

Then, similarly, the next vertical blanking period is performed.
Time t in the first half of V-BLK2₁₄~ T₁₅Unnecessary charge discharge
Vertical transfer clock pulse φIM during period THS2₁~ Φ
IM _FourThe high-speed vertical transfer pulse voltage VHC at
At the same time, the horizontal transfer register unit 35
Lock pulse φH₁, ΦH₂Stops and horizontal transfer register
The substrate pulse voltage HV on the substrate 41 immediately below the switch unit 35._subMark
In addition, the unnecessary charge region 13 in the upper stage of the display region 11 is unnecessary
The charge is transferred at high speed, and the substrate is transferred in the horizontal transfer register section.
It is discharged to the 41 side.

According to the above-described embodiment, the unnecessary charges in the unnecessary charge regions 12 and 13 based on the amount of camera shake are transferred at high speed and then discharged to the silicon substrate 41 directly below the horizontal transfer register section 34, which is the same as in the conventional case. The horizontal transfer register unit 3
It is not necessary to transfer the unwanted charges transferred at high speed vertically to the transfer circuit 5 at a higher speed, and the load on the drive circuit 39 can be reduced.

Further, since the high-speed horizontal transfer can be omitted and a time margin is produced, the charge transfer efficiency can be improved and the color unevenness of the image can be prevented.

On the other hand, since unnecessary charges transferred at high speed to the horizontal transfer register section 35 are discharged to the silicon substrate 41,
The horizontal unnecessary charge discharging gate portion 16 shown in FIG.
The unnecessary charge discharging unit 17 can be omitted. Therefore,
Compared with the conventional solid-state imaging device 15 for preventing camera shake in FIG. 11, the entire chip size can be reduced, and the yield of solid-state imaging chips from one semiconductor wafer is improved.

Furthermore, the present invention can be easily applied to the CCD solid-state image pickup device 19 having a plurality of horizontal transfer register portions shown in FIG. 12, and unnecessary charges due to camera shake can be completely discharged.

4 and 5 (cross section taken along line YY in FIG. 4)
Shows a specific example of the IT type CCD solid-state image pickup device according to the above-mentioned embodiment. In this specific example, a portion of the silicon substrate 51 of the first conductivity type, such as the N type, corresponding to the vertical transfer register portion 33 on the imaging region 37 side is provided with a second conductivity type, that is, an N ⁺ transfer channel region via a P ⁺ wafer region 52. 53 is formed.
On the transfer channel region 53, transfer electrodes 55 made of, for example, polycrystalline silicon are arrayed in the vertical transfer direction via a gate insulating film 54 made of, for example, SiO ₂ to form a vertical transfer register section 33. Four-phase vertical transfer clock pulses φIM ₁ , φIM ₂ , and φIM are applied to the transfer electrode 55.
₃ , φIM ₄ is applied.

An N ⁺ transfer channel region 56 continuous with the transfer channel region 53 of the vertical transfer register unit 33 is formed in a portion corresponding to the horizontal transfer register unit 34. On the transfer channel region 56, transfer electrodes 57 made of, for example, polycrystalline silicon are arrayed in the horizontal transfer direction via a gate insulating film 54 made of, for example, SiO ₂ to form a horizontal transfer register section 34. Two-phase horizontal transfer clock pulses φH ₁ and φH ₂ are applied to the transfer electrode 57.

On the other hand, in the N-type silicon substrate 51, the N-type substrate 41 directly below the horizontal transfer register section 34 and the substrate 51 immediately below the imaging region 34 including the light receiving section 32 and the vertical transfer register section 33 are electrically separated. So that the P ⁺ isolation region 5
8 is formed. A P-type overflow barrier region 59 is formed in the N-type substrate 41 immediately below the horizontal transfer register portion 35 electrically separated by the P ⁺ isolation region 58.
Then, the N under the overflow barrier region 59 is
The substrate voltage HV _sub is independently applied to the shaped substrate 41, and the substrate voltage IV is independently applied to the substrate 51 immediately below the imaging region 37.
_sub is applied. A P well region 60 is also formed on the substrate 51 on the imaging region 35 side, and this P well region 60 serves as an overflow barrier region for discharging charges to the substrate 51 side as an electronic shutter function in the light receiving section 32.

In such a configuration, the P ⁺ isolation region 58
Therefore, even if the substrate is separated between the vertical transfer register unit 33 and the horizontal transfer register unit 35, as shown by the potential distribution 61 in FIG.
Since the potential difference Δφ between them is large, there is no adverse effect on the transfer of charges from the vertical transfer register section 33 to the horizontal transfer register section 35.

At the time of discharging the unnecessary charges, the substrate voltage HV _sub different from that of the substrate 51 immediately below the other imaging region 35 can be independently applied to the substrate 41 immediately below the horizontal transfer register unit 35. Only the unnecessary charges transferred to the substrate 41 can be reliably discharged to the substrate 41.

FIG. 6 is a sectional view showing another specific example of the IT type CCD solid-state image pickup device according to the present invention. In this specific example, the P ⁻ well region 72 and the N ⁺ transfer channel region 73 are formed on the silicon substrate 71 of the first conductivity type, for example, the N type, and the N ⁺ channel region 73 is directly below the region corresponding to the vertical transfer register section 33. Then, a P ⁺ region 74 is formed. on the other hand,
Immediately below the N ⁺ channel region 74 in the region corresponding to the horizontal transfer register unit 35, the P ⁺ region 7 of the vertical transfer register unit 33 is provided.
A P region 75 having a concentration lower than 4 is formed.

Then, for example, SiO _{2 is formed} on the N ⁺ transfer channel region 73 in the region corresponding to the vertical transfer register section 33.
The vertical transfer register section 33 is configured by arranging the transfer electrodes 77 made of, for example, polycrystalline silicon in the vertical transfer direction via the gate insulating film 76 made of the like. 4 for the transfer electrode 77
Phase vertical transfer clock pulse φIM ₁ , φIM ₂ , φI
M ₃ and φIM ₄ are applied.

Further, the gate insulating film 76 is formed on the N ⁺ transfer channel region 73 in the region corresponding to the horizontal transfer register section 35.
Similarly, the transfer electrodes 78 made of polycrystalline silicon are arrayed in the horizontal transfer direction via the vias to form the horizontal transfer register section 35. Two-phase horizontal transfer clock pulses φH ₁ and φH ₂ are applied to the transfer electrode 78.

In this structure, the P region 75 is formed immediately below the N ⁺ transfer channel region 73 of the horizontal transfer register unit 35, so that the potential (φ _min ) overflows as shown in the potential distribution chart of FIG. An appropriate potential can be set between the barriers 46 (φ _OFB ).

In this structure, when the unnecessary charges in the unnecessary charge regions 12 and 13 are discharged, the driving of the horizontal transfer register unit 35 is stopped and the unnecessary charges transferred at high speed from the vertical transfer register unit are overflow barrier 46. (Φ _OFB ), and is discharged to the substrate 71. Then
Unwanted charges that cannot be completely discharged to the substrate 71, that is, unnecessary charges remaining in the potential (φ _min ) 43 are horizontally transferred at high speed and are all discharged to the reset drain.

In this structure, it is not necessary to use a separate substrate in the horizontal transfer register section 35, and the power supply can be a conventional power supply. Further, even in the case of high-speed horizontal transfer of unnecessary charges that cannot be completely discharged to the substrate, the transfer period is extremely short, so that the driving circuit is not overloaded.

In the above example, the unnecessary charge regions 12 and 13 in the upper and lower stages of the display region 11 are discharged according to the amount of camera shake, but in addition, the substrate 41 directly below the horizontal transfer register section is smeared. It can also be applied to a so-called smear drain for discharging unnecessary charges as a component.

Further, by making the potential of the overflow barrier 46 under the horizontal transfer register section 35 deeper than the potential of the bit separation area (transfer area) of the horizontal transfer register section 35, blooming in the horizontal transfer register can be prevented. it can.

In addition, although the above example is applied to the IT type CCD solid-state image pickup device, in addition to this, the light receiving portions to be pixels are arranged in a matrix, and the vertical transfer register portion is provided on one side of each light receiving portion row. It is also applicable to an FIT (frame interline transfer) CCD solid-state imaging device including an image pickup unit, a storage unit including a plurality of vertical transfer register units corresponding to the vertical transfer register unit of the image pickup unit, and a horizontal transfer register unit. .

[0067]

According to the solid-state image pickup device of the present invention, unnecessary charges are discharged to the substrate immediately below the horizontal transfer register section, whereby high-speed horizontal transfer to the horizontal transfer register section is omitted or becomes extremely short. The load on the drive circuit can be reduced.

Further, the charge transfer efficiency is not deteriorated, and it is possible to prevent color unevenness of the display image due to the transfer efficiency deterioration.

Further, the unnecessary charge discharging gate section and the unnecessary charge discharging section disposed below the conventional horizontal transfer register section can be omitted, and the chip size of the solid-state image pickup device as a whole can be reduced. The yield of solid-state imaging chips on a wafer can be improved.

Further, even in the solid-state image pickup device having a plurality of horizontal transfer register sections, the unnecessary charges can be easily and completely discharged.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of a solid-state imaging device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the present invention.

FIG. 3A is a potential distribution diagram of the horizontal transfer register section during signal charge transfer in the display area, which is used for explaining the operation of the present invention. B is a potential distribution diagram of the horizontal transfer register unit during unnecessary charge transfer in the unnecessary charge region, which is used for explaining the operation of the present invention. FIG.

FIG. 4 is a plan view of a main part showing a specific example of the solid-state imaging device according to the present invention.

5 is a cross-sectional view taken along the line YY of FIG.

FIG. 6 is a cross-sectional view of a main part showing another specific example of the solid-state imaging device according to the present invention.

FIG. 7 is a potential distribution diagram of the horizontal transfer register unit in FIG.

FIG. 8A is an explanatory diagram of a state of a display region and an unnecessary charge region in an imaging region when there is no camera shake. B is an explanatory diagram of states of a display region and an unnecessary charge region in an image pickup region when shaken by hand.

FIG. 9 is a block diagram showing an example of a conventional solid-state imaging device for camera shake prevention.

FIG. 10 is a timing chart for explaining the conventional operation.

FIG. 11 is a configuration diagram showing another example of a conventional solid-state imaging device for camera shake prevention.

FIG. 12 is a configuration diagram showing another example of a CCD solid-state imaging device.

[Explanation of symbols]

 31 solid-state image pickup device 32 light receiving part 33 vertical transfer register part 34 imaging area 35 horizontal transfer register part 36 output part 37 solid-state image sensor 38 camera shake detection circuit 39 drive circuit RG reset gate RD reset drain

Claims (6)

[Claims] 1. A solid-state imaging device comprising a light-receiving portion which becomes a pixel, a vertical transfer register portion corresponding to a light-receiving portion array, and a horizontal transfer register portion, wherein unnecessary charges are discharged to a substrate immediately below the horizontal transfer register portion. A solid-state imaging device comprising: 2. The solid-state imaging device according to claim 1, wherein the driving of the horizontal transfer register unit is stopped to discharge the unnecessary charges. 3. A separation region electrically separating a region including a light receiving unit and a vertical transfer register unit from a horizontal transfer register unit, and an overflow barrier provided in a substrate directly below the horizontal transfer register unit, A solid-state imaging device, wherein a substrate voltage different from that of a substrate immediately below a region including the light receiving unit and the vertical transfer register unit is applied to the substrate immediately below the horizontal transfer register unit. 4. A light receiving portion which becomes a pixel on a semiconductor substrate of the first conductivity type, and a vertical transfer register portion corresponding to the light receiving portion row,
In a solid-state imaging device including a horizontal transfer register unit, the first transfer unit is provided between the vertical transfer register unit and the semiconductor substrate.
Second conductive type first semiconductor layer forming a potential barrier is provided, and a second conductive type second semiconductor forming a second potential barrier between the horizontal transfer register section and the semiconductor substrate. A solid-state imaging device including a layer, wherein the second potential barrier is deeper than the first potential barrier. 5. The solid-state imaging device according to claim 4, wherein the impurity concentration of the second semiconductor layer is lower than the impurity concentration of the first semiconductor layer. 6. The solid-state imaging device according to claim 4, wherein the second potential barrier is deeper than a potential barrier formed between each bit of the horizontal transfer register section.