JPH07162245A - Amplifier circuit - Google Patents

Abstract

PURPOSE:To attain wide band constitution in a low power consumption by constituting a differential pair of two transistors(TRs) and a constant current source, constituting a current mirror circuit of two other TRs so that a differential output from the differential pair is converted into a single end signal and providing another TR to be connected to the differential pair and to ground through its source. CONSTITUTION:A differential pair is constituted of TRs 1, 4 in a push-pull amplifier circuit and respective current sources, a current mirror is constituted of TRs 10, 11 and TRs 8, 12 are used as gate-grounded TRs. Differential signals impressed to input terminal 60, 61 are converted into a single end signal by a current mirror constituted of TRs 2, 3 and the single end signal is outputted to the drains of the TRs 3, 4. A TR 13 is driven by the single end signal to supply an intake current from a load connected to an output terminal 62. A discharge side to the load has two signal routes. One passes five TRs, i.e., 7 9 10 11 12, and conducts three times of phase inversion. The other passes three TRs, i.e., 7 8 12, and generates one phase inversion. The latter route has higher speed and acts as a feedforward pass for the former route to suppress phase rotation at high frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit, and more particularly to a push-pull output amplifier circuit composed of insulated gate (MOS) transistors.

[0002]

2. Description of the Related Art Among conventional amplifier circuits of this type, a circuit called a push-pull output amplifier circuit is constructed, for example, as shown in FIG.

This conventional push-pull output amplifier circuit is
A differential pair is formed by each of the transistors 1 and 4 and the current source 50, and includes transistors 2 and 3, transistors 41 and 42, and transistors 43 and 44.
And current and mirror respectively, and transistor 4
4 and 45 are used as output stages. The capacitor 55 is for phase compensation.

Further, the gate of the transistor 1 is led to the inverting input terminal 60, the gate of the transistor 4 is led to the non-inverting input terminal 61, and the drains of the transistors 44 and 45 are led to the output terminal 62.

Next, the operation of the conventional push-pull output amplifier circuit will be described.

Consider the signal path to the output terminal 62 of the differential signal applied to the input terminals 60 and 61. The differential signal is converted into a single-ended signal by the current mirror composed of the transistors 2 and 3,
Is output to the respective drains of.

By driving the transistor 45 with this signal, the sink current from the load connected to the output terminal 62 is supplied. At the same time, this signal passes through an amplification circuit formed by the transistor 40 and the current source 52, and
Transistors 41 and 42 and Transistors 43 and 44
The discharge current is supplied to the load via two current mirrors composed of and.

The sink current, that is, the drain current of the transistor 45 increases as the gate voltage increases.

On the other hand, the drain current of transistor 44 increases as the gate voltage of transistor 40 decreases. In addition, this circuit has a so-called push-pull output amplification operation that can significantly reduce the current consumption when there is no signal by setting the mirror ratio of the current mirror included in the signal path on the discharge current side to 1 or more. Become.

[0010]

However, considering the frequency characteristics of the above-mentioned conventional push-pull output amplifier circuit, the main pole of the transfer function is determined by the phase compensation capacitance 55.
Higher-order poles of the second order and higher generally occur inside the load and the circuit.

In the signal path on the discharge current side of the conventional push-pull amplifier circuit, a total of three phase inversions occur from the gate of the transistor 40 to the output terminal 62. Furthermore, since the mirror ratio of the current mirror included in this path is large, a phase delay occurs due to the mirror effect. Due to these, higher-order poles are generated and the phase margin is reduced. Therefore, there is a drawback in that the current consumption when there is no signal increases because of increasing the frequency of these higher-order poles.

The present invention eliminates such drawbacks, and the CMOS
It is an object of the present invention to provide a push-pull output amplifier circuit which consumes low current in a process and has a wide band.

[0013]

In the amplifier circuit of the present invention, the differential pair led to the first and second input terminals, and the gate connected to the output of the differential pair and the source grounded. A first transistor; a second transistor whose source is connected to the drain of the first transistor and whose gate is grounded; and a second transistor whose source is connected to the drain of the second transistor and whose gate is grounded A third transistor of opposite polarity, a current mirror of the same polarity as the third transistor whose output is connected to the source of the third transistor, and a drain of which is connected to the input of the current mirror and whose source is grounded. 4th
And a fifth transistor whose gate is connected to the output of the differential pair and whose source is grounded. The drain of the first transistor is connected to the gate of the fourth transistor, and the third transistor is connected. The drain of the transistor and the drain of the fifth transistor are both led to the output terminal.

Further, each of the first, second, fourth and fifth transistors of the amplifier circuit of the present invention is an N channel type MOS transistor, and the third transistor is a P channel type MOS transistor. You can also

Further, the amplifier circuit of the present invention may be arranged such that a phase compensating capacitance element is connected between the gate and drain of the fifth transistor.

Further, in another amplifying circuit of the present invention, a differential pair introduced into each of the first and second input terminals, a gate connected to the first output of the differential pair, and a source grounded. A first transistor, a second transistor whose source is connected to the drain of the first transistor and whose gate is grounded, and a second transistor whose source is connected to the drain of the second transistor and whose gate is grounded A third transistor of opposite polarity, a first current mirror of which the output is connected to the source of the third transistor and having the same polarity as the third transistor, and a drain of the first current mirror. A fourth transistor connected to the input and having a source grounded; and a fifth transistor having a gate connected to the first output and having a source grounded, The drain of the first transistor and the gate of the fourth transistor are connected to each other, the drain of the third transistor and the drain of the fifth transistor are both led to the first output terminal, and the gate is the differential circuit. A sixth transistor having a source grounded and connected to a second output opposite in phase to the first output of the pair; and a seventh transistor having a source connected to the drain-in of the sixth transistor and grounded An eighth transistor whose source is connected to the drain of the seventh transistor and whose gate is grounded and whose polarity is opposite to that of the seventh transistor, and whose output is connected to the source of the eighth transistor. A second current mirror having the same polarity as that of the first current mirror, and a drain whose drain is connected to the input of the second current mirror and whose source is grounded. And a tenth transistor whose gate is connected to the second output of the differential pair and whose source is grounded, wherein the drain of the sixth transistor and the gate of the ninth transistor are connected to each other, The drain of the eighth transistor and the drain of the tenth transistor are both led to the second output terminal.

Furthermore, the first, second, fourth, fifth, sixth, seventh, ninth and first of the other amplifying circuits of the present invention.
Each of the 0 transistors may be an N-channel MOS transistor, and the third and eighth transistors may be P-channel MOS transistors.

[0018]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a push-pull output amplifier circuit according to a first embodiment of the present invention.

Referring to FIG. 1, in the push-pull output amplifier circuit of this embodiment, a differential pair is formed by each of the transistors 1 and 4 and the current source 50.
0 and 11 form a current mirror, and transistors 8 and 12 are used as grounded gate transistors.

The transistors 5 and 6 and the current source 51 form a bias circuit for the gate potential of the transistor 8.
In this configuration, the capacitor 55 is used for phase compensation.

Further, the gate of the transistor 1 is led to the inverting input terminal 60, the gate of the transistor 4 is led to the non-inverting input terminal 61, and the drains of the transistors 12 and 13 are led to the output terminal 62.

Next, the operation of the push-pull amplifier circuit of the first embodiment of the present invention will be described.

First, consider the signal path to the output terminal 62 of the differential signals applied to the input terminals 60 and 61. The differential signal is a current composed of transistors 2 and 3.
It is converted into a single-ended signal by the mirror and output to the drains of the transistors 3 and 4, respectively. By driving the transistor 13 with this signal, the sink current from the load connected to the output terminal 62 is supplied.

Next, the discharge current side to the load has two signal paths in this circuit.

One is transistor 7 → transistor 9
The phase inversion is performed three times through the five transistors, that is, the transistor 10, the transistor 11, and the transistor 12. The other is transistor 7 → transistor 8
→ 1 via 3 transistors of transistor 12
Phase inversion occurs only once.

Considering the signal delays of these two signal paths, it is clear that the latter is faster by comparing the number of transistors included in the paths.

Therefore, the latter signal path becomes a feed-forward path of the former signal path and suppresses phase rotation at high frequencies. Further, the grounded-gate transistor 12 which is commonly included in both paths is inserted to perform the level shift with the output, but the Miller effect generated in the transistor 11 is also reduced.

Next, the fact that the slew rate of the push-pull amplifier circuit of this embodiment can be increased will be described in comparison with the conventional example.

The maximum discharge current to the load of the conventional push-pull amplifier circuit is when the transistor 40 is turned off. IB the current value of the current source 52 now, a transistor (41 to 44), if the m times the current amplification is performed, this value becomes (m × I _B).

On the other hand, the increase in the discharge current of the push-pull amplifier circuit of the first embodiment of the present invention occurs when the transistor 7 is turned off. For equalizing the current consumption when no signal, the current value of the current source 51 and _{I BO = (I B / 2} ), and all the same for simplicity of description the size of the transistor (5-9), the gate width Is W and the gate length is L. Further, it is assumed that the current mirror composed of the transistors 10 and 11 performs m-fold current amplification.

If β = μC _ox W / 2L μ: surface mobility, C _ox : gate capacitance per unit area, the gate potential V _G5 of the transistors 5 and 8 is

[0033]

Therefore, the gate potential VG9 of the transistor 9 when the transistor 7 is turned off is

[0035]

The drain-in current ID9 of the transistor 9 at this time is I _D9 ≈β (V _G9 −V _T ) ² = 4 × (I _BO ) = 2 ×
To become (I _B). From the above, the maximum value of the discharge current is (2 m) × (I _B ), which is twice as fast as the conventional circuit.

The sink current is the same as in the conventional circuit.

Next, a push-pull amplifier circuit according to the second embodiment of the present invention will be described.

Referring to FIG. 2, the push-pull amplifier circuit of this embodiment is a fully differential operational amplifier circuit realized by using two push-pull amplifier circuits of the first embodiment.

The operation of the push-pull amplifier circuit according to the second embodiment is similar to that of the push-pull amplifier circuit according to the first embodiment, and detailed description thereof will be omitted. This embodiment also improves the phase margin and reduces the current consumption when there is no signal, as in the first embodiment.

[0041]

As described above, according to the present invention, the circuit configuration allows a phase margin even with a low current consumption, so that the band can be widened and the load driving capability at the time of a large signal is excellent.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a push-pull output amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a push-pull output amplifier circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a conventional push-pull output amplifier circuit.

[Explanation of symbols]

 1 to 13, 20 to 37, 40 to 45 Transistor 50 to 52 Constant current source 55 to 57 Capacitance 60, 61, 64, 65, 67 Input terminal 62, 63, 66 Output terminal

Claims (5)

[Claims] 1. A differential pair led to first and second input terminals, a first transistor whose gate is connected to an output of the differential pair and whose source is grounded, and a source whose first terminal is the first transistor. A second transistor connected to the drain of the second transistor and grounded to the gate; and a third transistor having a source connected to the drain of the second transistor and grounded to the second transistor and having a polarity opposite to that of the second transistor.
A current mirror having the same polarity as the third transistor, the output of which is connected to the source of the third transistor;
A fourth transistor whose drain is connected to the input of the current mirror and whose source is grounded; and a fifth transistor whose gate is connected to the output of the differential pair and whose source is grounded. An amplifier circuit, wherein a drain and a gate of the fourth transistor are connected to each other, and a drain of the third transistor and a drain of the fifth transistor are both led to an output terminal. 2. The first, second, fourth and fifth transistors are N-channel type MOS transistors, and the third transistor is a P-channel type MOS transistor. The described amplifier circuit. 3. The amplifier circuit according to claim 1, wherein a phase compensating capacitance element is connected between the gate and the drain of the fifth transistor. 4. A differential pair introduced into each of the first and second input terminals, a first transistor whose gate is connected to the first output of the differential pair and whose source is grounded, and a source A second transistor connected to the drain of the first transistor and grounded to the gate; and a third transistor having a source connected to the drain of the second transistor and grounded to the second transistor and having a polarity opposite to that of the second transistor. A first current mirror whose output is connected to the source of the third transistor and having the same polarity as the third transistor; and a drain whose source is grounded and which is connected to the input of the first current mirror. 4 transistor and a fifth transistor whose gate is connected to the first output of the differential pair and whose source is grounded, and the drain of the first transistor Is connected to the gate of the fourth transistor, the drain of the third transistor and the drain of the fifth transistor are both led to the first output terminal, and the gate of the first transistor of the differential pair is A sixth transistor whose source is grounded and which is connected to a second output opposite in phase to the output, a seventh transistor whose source is connected to the drain-in of the sixth transistor and whose gate is grounded, and a source which is the seventh An eighth transistor having a polarity opposite to that of the seventh transistor connected to the drain of the second transistor and having a gate grounded; and a second transistor having an output having the same polarity as the eighth transistor connected to the source of the eighth transistor. Current mirror, a ninth transistor whose drain is connected to the input of the second current mirror and whose source is grounded, and whose gate is The differential pair 2
A drain of the sixth transistor and a gate of the ninth transistor are connected to each other, and a drain of the eighth transistor and a drain of the tenth transistor are connected to each other. An amplifier circuit, in which both the drain and the drain are led to the second output terminal. 5. The first, second, fourth, fifth, sixth, seventh, ninth and tenth transistors are N-channel type MOS transistors, and the third and eighth transistors are respectively. 5. The amplifier circuit according to claim 4, wherein is a P-channel type MOS transistor.