JPH07160676A - Fast fourier transformation device and fast fourier transformation method - Google Patents

Abstract

PURPOSE:To contrive the transformation method in which the final result data after Fourier transformation are rearranged efficiently inside the device without depending on a data processing in the form of a software in an improvement of a fast Fourier transformation device. CONSTITUTION:This device is provided with an arithmetic means 11 for Fourier transforming N[p<n>] pieces of the data expressed by a cardinal (p) other than '2', a storage means 12 for tentatively storing the data before and after the Fourier transformation and an address coversion means 13 for converting the addresses of the binary display of the data to the addresses of p-ary display or converting the addresses of the p-ary display to the addresses of the binary display. The address conversion means 13 is provided with a p-ary digit position inversion means 13A and the digit position inversion means 13A inverts the address digit position of the p-ary display of the data before the Fourier transformation and outputs the inverted address of the p-ary display.

Description

Detailed Description of the Invention

[Table of Contents] Industrial Application Field of the Prior Art (FIG. 12) Problem to be Solved by the Invention Means for Solving the Problem (FIG. 1) Action Example (FIGS. 2 to 11) Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fast Fourier transform device and a fast Fourier transform method, and more specifically to a device for fast Fourier transform of a digital signal having a radix p other than 2. And the improvement of the method. In recent years, high-speed arithmetic processing devices have been used in the field of information processing such as image identification and voice recognition. Among them, a fast Fourier transform device (hereinafter also referred to as an FFT arithmetic device) is applied when analyzing a signal waveform. Has been done.

According to this, a device for performing a fast Fourier transform on a radix p other than 2 has been researched and developed, and the speed of data processing has been advanced. However, the method of storing the final result data after the Fourier transform in the original p-adic notation address depends on data processing by software. Therefore, there is a demand for an apparatus and method capable of efficiently rearranging the data inside the final result data after Fourier transformation without depending on the data processing by software.

[0004]

2. Description of the Related Art FIG. 12 is an explanatory diagram according to a conventional example. Figure
12A is a configuration diagram of an FFT operation device according to a conventional example, and FIG. 12B shows a method of rearranging the final result data. For example, N with radix p = 2
A fast Fourier transform device for processing (= 2 ⁿ ) pieces of data is shown in FIG. 12A as a butterfly computing unit 1, a memory 2, a bit converting unit 3 and a central processing unit (hereinafter, CPU).
It consists of 4.

The function of the device is, for example, from the memory 2.
Read out eight element data [X ₀ ⁰, X_Four ⁰, X₂ ⁰, X
₆ ⁰, X₁ ⁰, X_Five ⁰, X₃ ⁰, X₇ ⁰] To the butterfly computing unit 1
When it is output, the element data of 8 pieces is processed by the calculation unit 1 concerned.
Rie transform (complex product sum operation) is performed. Of each data at this time
As shown in FIG. 12 (B), the addresses are ADD0, ADD4,
ADD2, ADD6, ADD1, ADD5, ADD3, ADD7
It

Further, the Fourier transformed final result data [X _O ⁰ X ₀ ¹ X ₀ ² , X ₀ ³ X ₀ ⁴ , X ₀ ⁵ , X ₀ ⁶ , X ₀ ⁷ ]
Are stored in the memory 2. The final result data is the address ADD0, which is bit-inverted by the bit conversion unit 3,
ADD1, ADD2, ADD3, ADD4, ADD5, ADD6, A
Stored in DD7. As a result, the final result data is stored in the same memory address as at the time of input and the data is rearranged. This is because the final result data string after the Fourier transform is located at the bit-inverted address of the input data string before the Fourier transform.

[0007]

Therefore, even in a device for Fourier transforming a radix p other than 2, in order to speed up data processing, the final result data after Fourier transform is stored in the same memory address as at the time of input. Must be stored. However, in order to store the final result data at the original address in p-adic notation, the applicant of the present invention previously filed Japanese Patent Laid-Open No.
No. 3-205767, the bit reverse device and Japanese Patent Laid-Open No.
Since the bit reverse circuit of No. 265358 cannot be applied as it is, there is no choice but to adopt a method of rearranging the final result data by software. This method is shown in Figure 12.
As shown in (B), the final result data is sequentially rearranged at the bit positions of the input data string before Fourier transform on the memory.

Therefore, in the case of performing fast Fourier transform on a large amount of data in image recognition, voice recognition, etc., such a software rearrangement method becomes very complicated and hinders high-speed data processing. is there.
An arithmetic circuit for processing N (= ^pn ) data represented by a radix p other than 2 is disclosed in JP-A-55-118179. However, the address of the p-value display of the final result data after the Fourier transform is not disclosed.

The present invention was created in view of the problems of the conventional example, and does not depend on software-based rearrangement processing of final result data after Fourier transform,
An object of the present invention is to provide a fast Fourier transform device and a fast Fourier transform method capable of efficiently rearranging data inside by devising an address transforming method.

[0010]

FIG. 1 shows a principle diagram of a fast Fourier transform device according to the present invention. As shown in FIG. 1, the fast Fourier transform device of the present invention includes a computing means 11 for performing a Fourier transform on N [ ^pn ] data represented by a radix p other than 2, and temporarily storing the data before and after the Fourier transform. Storage means 12 for storing the data, and an address conversion means 13 for converting the binary address of the data into a p-adic address or converting the p-adic address into a binary address. Conversion means 13
Has a p-adic digit position inverting means 13A. The digit position inverting means 13A inverts the p-adic address digit position of the data before the Fourier transform and outputs the inverted p-adic address. It is characterized by

In the fast Fourier transform device of the present invention,
The storage means 12 is characterized in that the data before and after the Fourier transform is temporarily stored in the address of binary number display or p-ary number display. The fast Fourier transform method of the present invention is a method of Fourier transforming N [ ^pn ] data represented by a radix p other than 2, and Fourier transforming data stored at an address in p-adic notation, The final result data subjected to the Fourier transform is rearranged into an address obtained by inverting the address digit position of the data before the Fourier transform.

In the fast Fourier transform method of the present invention, prior to the Fourier transform, the addresses of N [ ^pn ] data represented by a radix p other than 2 in binary notation are converted into p-adic notation. It is characterized by converting to an address. Further, in the fast Fourier transform method of the present invention, the p-adic address of the Fourier-transformed final result data is converted into a binary address, and the above object is achieved.

[0013]

[Operation] The operation of the fast Fourier transform device of the present invention will be described. For example, when N [ ^pn ] pieces of data represented by a radix p other than 2 are read from the storage means 12, the binary address of the data is converted into a p-adic address by the address converting means 13. To be done. This allows
The data of the address expressed in p-adic number is Fourier-transformed by the calculating means 11.

At the end of the Fourier transform, the p-adic digit position inverting means 13A inverts the address digit position of the p-adic representation of the data before the Fourier transform, and the inverted p-adic address is converted into the address translating means. 13 is output. Further, the address conversion means 13 converts the inverted p-adic number display address into a binary number display address, and outputs the binary number display address to the storage means 12.

Therefore, it is possible to store the final result data obtained by the Fourier transform at the address position of the data before the Fourier transform. As a result, the output data can be rearranged inside the device without depending on the software processing as in the conventional example. This makes it possible to easily configure a device for performing a fast Fourier transform on data of a number N (= p ⁿ ) that can be represented by a radix p other than 2.

In the fast Fourier transform device of the present invention, the data before and after the Fourier transform is directly stored in the address in the p-adic number instead of the storage means 12 for temporarily storing the data before and after the Fourier transform in the address in the binary number display. By providing the storage means 12 for storing the data, it is possible to further speed up the data processing. According to the fast Fourier transform method of the present invention, when N [ ^pn ] data represented by a radix p other than 2 is Fourier transformed, the final result data obtained by the Fourier transform is the address of the data before the Fourier transform. It is rearranged into an address in p-adic notation with the digit position reversed.

Therefore, since the final result data after the Fourier transform can be efficiently rearranged to the original address before the Fourier transform, the fast Fourier transform can be performed in the image identification and the voice recognition which handle a huge amount of data. Is possible. As a result, in the case where there is a large amount of data and it is more effective to match the configuration of the apparatus to the radix p = 2 than to match the radix p = 2, the data processing method according to the present invention. By adopting, it becomes possible to reduce the memory capacity.

[0018]

Embodiments of the present invention will now be described with reference to the drawings. 2 to 11 are diagrams illustrating a fast Fourier transform device and a fast Fourier transform method according to an embodiment of the present invention. FIG. 2 is a configuration diagram of an FFT operation device according to an embodiment of the present invention, and FIGS. 3 and 4 are explanatory views of the butterfly operation unit [No. 1 and 2]. Figure 5 shows that binary /
6A and 6B are a configuration diagram and a supplementary explanatory diagram of the ternary conversion unit, and FIG. 6 is an operation explanatory diagram thereof. FIG. 7 is a block diagram of the digit position inversion unit, and FIG. 8 is a block diagram of the ternary / binary conversion unit and a supplementary explanatory diagram. 9 to 11 are diagrams showing the fast Fourier transform algorithm (stages P1 to P3) according to the embodiment of the present invention, respectively.

For example, when the radix p = 3, N (= p³)Individual
The fast Fourier transform device for processing the data of
The butterfly operation unit 21, the multi-memory units 22 and 3
Base address conversion unit 23, data control unit 24, control device 2
5, an address bus 26 and a data bus 27 are provided. You
That is, the butterfly computing unit 21 is the computing means 11 of the principle diagram.
3 is an example of³= 27 data [X₀ ⁰, X₉ ⁰, X
₁₈ ⁰, X₃ ⁰, X₁₂ ⁰, X_{twenty one} ⁰, X₆ ⁰, X₁₅ ⁰, X_{twenty four} ⁰，
X₁ ⁰, X_Ten ⁰, X₁₉ ⁰, X_Four ⁰, X₁₃ ⁰, X_{twenty two} ⁰, X₇ ⁰，
X₁₆ ⁰, X_{twenty five} ⁰, X₂ ⁰, X₁₁ ⁰, X₂₀ ⁰, X_Five ⁰，
X₁₄ ⁰, X_{twenty three} ⁰, X₈ ⁰, X₁₇ ⁰, X₂₆ ⁰] Fourier transform
To replace. The superscript number of data element X is
Indicates the row number of the determinant, the subscript indicates the column number
It The internal configuration of the arithmetic unit 21 is shown in FIGS.
Will be described in detail.

The multi-memory unit 22 is an example of the storage means 12, and is composed of two memories 22A and 22B controlled based on the write / read signal W / R. The memory unit 22
Are connected to a ternary address conversion unit 23 via an address bus 26, and are also connected to a data control unit 24 via a data bus 27. In the embodiment of the present invention, the memory 22A temporarily stores 27 data in binary notation before Fourier transform and intermediate result data of butterfly operation.
Similarly, the memory 22B temporarily stores the intermediate result data and 27 pieces of binary data after Fourier transform.

The ternary address conversion unit 23 is an example of the address conversion unit 13, and includes a counter 31, a ternary number conversion unit 32, a ternary number register 33, 34, and a ternary digit position inverting unit.
23A, 3/2 binary number conversion unit 35 and multiplexer 36,
Composed of 37. The counter 31 is a circuit that generates a binary address based on the clock signal CLK. The 2 / 3-ary number conversion unit 32 is a circuit that converts an address in binary number into an address in ternary number display and outputs the address to the ternary number register 33. The internal configuration and function of the conversion unit 32 will be described in detail with reference to FIGS.

The ternary number register 33 is a circuit for temporarily holding an address of ternary number representation of data before Fourier transform. The ternary number register 34 is a circuit for temporarily holding the address of the ternary number display in which the digit position is inverted. The ternary digit position inverting unit 23A is an example of a p-adic digit position inverting unit 13A,
This is a circuit that inverts the address digit position in ternary number display of the data before Fourier transform and outputs the inverted address in ternary number display to the ternary number register 34. The inversion unit 23A
The internal configuration of will be described in detail in FIG.

The 3 / 2-ary number conversion unit 35 is a circuit for converting a ternary address into a binary address and outputting it to the multiplexer 37. The internal configuration and function of the conversion unit 32 will be described in detail with reference to FIG. The multiplexer 36, based on the address selection signal S1,
The binary address is output to the memory 22A or 22B. The multiplexer 37 stores the binary-displayed address whose digit position is inverted based on the address selection signal S2 in the memory 22A.
Alternatively, it is a circuit for outputting to 22B.

The data control unit 24 and the control device 25 are an example of the control means 14 of the principle diagram. The data control unit 24 includes multiplexers 38 and 39 and selectors 40 and 41. The multiplexer 38 transfers the data before Fourier transform or its intermediate result data from the memory 22A to the memory 22B based on the data selection signal S3. Multiplexer 3
Reference numeral 9 designates data before Fourier transform or intermediate result data thereof from the memory 22B to the memory 22 based on the data selection signal S4.
Transfer to A.

The selector 40 is a circuit for selecting data input based on the memory selection signal S5, and the selector 41
Is a circuit for selecting data input based on the memory selection signal S6. The controller 25 includes a butterfly computing unit 21,
This is a device for controlling input / output of the multi-memory unit 22, the ternary address conversion unit 23, and the data control unit 24. For example,
The control device 25 is composed of a timing generation circuit, a CPU, etc., and outputs the clock signal CLK to the counter 31. Further, the device 25 outputs the write / read signal / R to the memories 22A and 22B and outputs the address selection signals S1 and S2 to the multiplexers 36 and 37, respectively. Further, the device 25 sends the data selection signal S to the multiplexers 38 and 39.
3 and S4 are output, and the memory selection signals S5 and S6 are output to the selectors 40 and 41, respectively.

Next, the internal configuration of the butterfly computing unit 21 will be described. For example, as shown in FIG. 3A, the arithmetic unit 21 for performing Fourier transform of 3 ³ = 27 data in parallel has nine arithmetic units B11 to B19 on the first stage P1.
Is provided, and the nine arithmetic units B21 to
B29 is provided, and nine arithmetic units B are provided on the third stage P3.
31 to B39 are provided respectively. In addition, each stage P1
27 arithmetic units of P3 to P3 are disclosed in JP-A-55-118179.
The arithmetic circuit as disclosed in No.

For example, the function of the arithmetic unit B11 of the stage P1
As shown in FIG. 3B, element data [X₀ ⁰，
X₉ ⁰, X₁₈ ⁰], And the intermediate result data
[X₀ ⁰, X ₀ ¹, X₀ ²] Is output. That is, equation (1)
The sum of products operation of

[0028]

[Equation 1]

However, W is e^-jT, [T = 2π / N]
Where N is the number of elements and k is the stage (step)
Is an integer determined by Similarly, the operation unit of the stage P1
In B12 to B19, the remaining element data is product-sum calculated and
Output the intermediate result data. Also, the calculation of the stage P2
The function of the part B21 is as shown in FIG.
Data [X₀ ⁰, X₃ ⁰, X₆ ⁰] And multiply-accumulate
Result data [X₀ ⁰, X ₀ ³, X₀ ⁶] Is output. That is,
The product-sum calculation processing of the equation (2) is performed.

[0030]

[Equation 2]

Similarly, the arithmetic units B22 to B29 of the stage P2 are
Performs a product-sum operation on the remaining intermediate result data and outputs the intermediate result data. Further, the calculation unit B of the stage P3
The function of 31 is, as shown in FIG. 4 (B), a product-sum operation of the intermediate result data [X ₀ ⁰ , X ₁ ⁰ , X ₈ ⁰ ] and the final result data [X ₀ ⁰ , X ₀ ^9]. , X ₀ ¹⁸ ]. That is,
The sum of products operation of the equation (3) is performed.

[0032]

[Equation 3]

Similarly, the operation units B32 to B39 of the stage P3
Performs a product-sum operation on the remaining intermediate result data and outputs the final result data. Next, the internal configuration of the binary / ternary conversion unit 32 will be described. For example, binary / 3 that converts a 7-bit address in binary notation to a 5-bit ternary number
The binary conversion unit 32, as shown in FIG.
A, bit selectors 100-106 and adders 200-205.

The register 32A is a circuit for temporarily holding a 7-bit address in binary notation. Bit selector 100
Numerals to 106 are circuits for selectively outputting a binary signal of each bit. The adder 200 adds the binarized signals output from the bit selectors 100 and 101 and adds the added signal to the adder 201.
Output to. The adder 201 adds the binarized signal and the addition signal output from the bit selector 102 and the adder 201, and outputs the addition signal to the adder 202. Adder 202
Is 2 output from the bit selector 103 and the adder 202
Add the binarized signal and the addition signal and add the addition signal
Output to 203. Similarly, the adder 205 adds the binarized signal and the addition signal output from the bit selector 106 and the adder 204, and outputs the addition signal to the ternary number register 33.

FIG. 5B shows the bit selector 100.
10 shows a truth table of the input bits of the ternary number register 33 with respect to the output bits of ~ 106. In FIG. 5 (B),
"0", "1", and "2" correspond to ternary values [-1, 0, 1] and indicate addresses in ternary notation. In FIG. 5 (B),
The blank portion indicates “0”. Here, the function of the binary / ternary conversion unit 32 will be described. For example, in the case of converting a 7-bit address [1111111] represented by a binary number into a ternary number, when "2" and "1" are added by the adder 200 as shown in FIG. 1
0 ”and the output“ 11 ”of the bit selector 102 are added to the adder 20.
Added by 1. Further, the addition result “21” and the output “22” of the bit selector 103 are added by the adder 202, and the addition result “120” and the bit selector 10 are added.
The output “121” of 4 is added by the adder 202.

Further, the addition result "1011" and the output "1012" of the bit selector 105 are added by the adder 204, and the addition result "2100" and the output "2101" of the bit selector 106 are added by the adder 205. Is added. As a result, it is possible to output the 5-bit address [11201] representing the ternary number to the ternary number register 33.

Next, the internal structure of the ternary digit position reversal unit 23A will be described. For example, in FIG. 7, the ternary digit position reversing unit 23A for inverting the 5-bit address in ternary number is 5 in FIG.
3-1 selectors SE1 to SE5. The selector SE1 is set to 3 based on the inversion control signal N5, N4 or N3.
Select 3 ⁰ digit bit or a fixed "0" bit in ary register 33, and outputs it to the 3 ^four-digit bit ternary register 34. The selector SE2 has the inversion control signals N5, N.
Select 3 ⁰ digit bits, 3 ¹ digit bits or fixed "0" bits of the ternary number register 33 based on 4 or N3,
It is output to the 3 ³ -bit of the ternary register 34.

Similarly, the selector SE3 outputs the inverted control signal N.
3, ^{0 of the} ternary register 33 based on 5, N4 or N3
A digit bit, 3 ¹ digit bit, or 3 ¹ digit bit is selected and output to the 3 ² digit bit of the ternary number register 34. The selector SE4 uses the inversion control signals N5, N4 or N.
3 ¹ digit of ternary register 33 based on 3, 3
Select the ² digit bit or the 3 ³ digit bit and output it to the 3 ¹ digit bit of the ternary register 34. The selector SE5 switches to 3 based on the inversion control signal N5, N4 or N3.
Select the 3 ² digit bit, 3 ³ digit bit or 3 ⁴ digit bit of the radix register 33, and select it.
The output of the 3 ^0-digit bit.

Next, the internal structure of the ternary / binary conversion unit 35 will be described. For example, as shown in FIG. 8A, the ternary / binary conversion unit 35 for converting a 5-bit address represented by a ternary number into a 7-bit binary number is a bit selector 300.
.About.304, adders 400 to 403 and a register 35A.
The bit selectors 300 to 304 are circuits that selectively output the ternary signal of each bit. Adder 400 is a bit selector 30
The ternary signals output from 0 and 301 are added, and the added signal is output to the adder 401.

The adder 401 adds the ternary signal and the addition signal output from the bit selector 302 and the adder 400, and outputs the addition signal to the adder 402. Adder 402
Is output from the bit selector 303 and the adder 401.
Add the binarized signal and the addition signal and add the addition signal
Output to 403. The adder 403 adds the ternary signal and the addition signal output from the bit selector 304 and the adder 402, and outputs the addition signal to the binary number register 35A.
The register 35A is a circuit for temporarily holding a 7-bit address represented by a binary number.

FIG. 8B shows the bit selector 300.
3 shows a truth table of the input bits of the binary register 35A for the output bits of .about.304. In FIG. 8 (B),
The input has the states of "1" and "2" in addition to "0", whereby the addresses in binary notation are different. Next, the operation of the FFT operation device according to the embodiment of the present invention will be described. For example, the number of elements 27 [=
3 ³ ] input data are read from the memory 22A based on the write / read signal W / R. The address in binary number display is converted by the address conversion unit 23 into the address in ternary number display. That is, the 2/3 base number conversion unit 3
By 2, a binary address is converted into an address in ternary representation.

As a result, the element data X ₀ ⁰ is the address in ternary notation.

Stored in the storage location of the corresponding binary representation to [000], similarly, the data X ₉ ⁰ is stored in the [100]. This is X ₀ ⁰

[000], X₉ ⁰Display [100]
It Similarly, the relationship between ternary address and data
Is X₁₈ ⁰[200], X ₃ ⁰[010], X₁₂ ⁰[11
0], X_{twenty one} ⁰[210], X₆ ⁰[020], X₁₅ ⁰[1
20], X_{twenty four} ⁰[220], X₁ ⁰[001], X
_Ten ⁰[101], X₁₉ ⁰[201], X_Four ⁰[011],
X₁₃ ⁰[111], X_{twenty two} ⁰[211], X₇ ⁰, [02
1], X₁₆ ⁰[121], X_{twenty five} ⁰[221], X₂ ⁰[0
02], X₁₁ ⁰[102], X₂₀ ⁰[202], X
_Five ⁰[012], X₁₄ ⁰[112], X_{twenty three} ⁰[212],
X₈ ⁰[022], X₁₇ ⁰[122], X₂₆ ⁰[222]
Is.

The 27 element data X ₀ ^{0 to} X ₂₆ ⁰ are transferred from the memory 22A to the arithmetic units B11 to B19 of the butterfly arithmetic unit 21 via the selector 40 based on the memory selection signal S5. As a result, the butterfly calculator 21 performs a Fourier transform. At this time, when the butterfly calculation is performed three times by the stages P1 to P3, the Fourier transform ends.

Specifically, as shown in FIG. 9, the first screen
Tage P1 is 27 with 9 arithmetic units B11 to B19.
Element data [X₀ ⁰, X₉ ⁰, X₁₈ ⁰, X₃ ⁰, X₁₂ ⁰, X
_{twenty one} ⁰, X₆ ⁰, X₁₅ ⁰, X_{twenty four} ⁰, X₁ ⁰, X_Ten ⁰, X₁₉ ⁰，
X_Four ⁰, X₁₃ ⁰, X_{twenty two} ⁰, X₇ ⁰, X₁₆ ⁰, X_{twenty five} ⁰, X₂ ⁰，
X₁₁ ⁰, X₂₀ ⁰, X_Five ⁰, X₁₄ ⁰, X_{twenty three} ⁰, X₈ ⁰，
X₁₇ ⁰, X₂₆ ⁰] Is Fourier transformed, and the intermediate result
Data [X₀ ⁰, X₀ ¹, X₀ ², X ₃ ⁰, X₃ ¹, X₃ ², X₆ ⁰, X
₆ ¹, X₆ ², X₁ ⁰, X₁ ¹, X₁ ², X_Four ⁰, X_Four ¹, X_Four ²，
X ₇ ⁰, X₇ ¹, X₇ ², X₂ ⁰, X₂ ¹, X₂ ², X_Five ⁰, X_Five ¹, X
_Five ², X₈ ⁰, X₈ ¹, X₈ ²] Is transferred to the second stage P2
Be done.

Here, in the embodiment of the present invention, 27 pieces of intermediate result data are directly transferred inside the butterfly computing unit 21 to the computing units B21 to B29 of the next stage. Based on the memory selection signal S6, the intermediate result data is once transferred to the memory 22B via the selector 41. Based on the memory selection signal S5, the intermediate result data is transferred from the memory 22B to the calculator 21 via the selector 40.
It may be read out.

In the stage P2, 27 pieces of intermediate result data as shown in FIG. 10 are Fourier-transformed by the nine operation units B21 to B29, and the intermediate result data [X ₀ ⁰ , X
₀ ¹ , X ₀ ² , X ₀ ³ , X ₀ ⁴ , X ₀ ⁵ , X ₀ ⁶ , X ₀ ⁷ , X ₀ ⁸ ,
^{_{X 1 0, X 1 1,}} X 1 2, X 1 3, X 1 4, X 1 5, X 1 6, X 1 7, X
₁ ⁸ , X ₂ ⁰ , X ₂ ¹ , X ₂ ² , X ₂ ³ , X ₂ ⁴ , X ₂ ⁵ , X ₂ ⁶ ,
X ₂ ⁷ , X ₂ ⁸ ] is transferred to the third stage P3.

At this stage P3, 2 as shown in FIG.
7 pieces of intermediate result data are output by 9 pieces of arithmetic units B31 to B39.
Fourier transform, and the final result data [X₀ ⁰, X
₀ ¹, X ₀ ², X₀ ³, X₀ ^Four, X₀ ^Five, X₀ ⁶, X₀ ⁷, X₀ ⁸，
X₀ ⁹, X₀ ^Ten, X₀ ¹¹, X₀ ¹², X ₀ ¹³, X₀ ¹⁴, X₀
¹⁵, X₀ ¹⁶, X₀ ¹⁷, X₀ ¹⁸, X₀ ¹⁹, X₀ ²⁰, X₀
^{twenty one}, X ₀ ^{twenty two}, X₀ ^{twenty three}, X₀ ^{twenty four}, X₀ ^{twenty five}, X₀ ²⁶] Is
Based on the memory selection signal S6, a memo is sent via the selector 41.
It is transferred to the 22B.

Here, the storage addresses of the 27 final result data are as follows: the element data X ₀ ⁰ is the address [00
0] is stored in the storage address in binary notation, and similarly, the data X ₀ ¹ is stored in [001]. This is X ₀ ⁰

Displayed as [000], X ₀ ¹ [100]. Same as below 3
The relation between the address in decimal notation and the data is X ₀ ² [00
2], X ₀ ³ [010], X ₀ ⁴ [011], X ₀ ⁵ [01
2], X ₀ ⁶ [020], X ₀ ⁷ [021], X ₀ ⁸ [02
2], X ₀ ⁹ [100], X ₀ ¹⁰ [101], X ₀ ¹¹ [1
02], X ₀ ¹² [110], X ₀ ¹³ [111], X ₀ ¹⁴
[112], X ₀ ¹⁵ [120], X ₀ ¹⁶ [121], X
₀ ¹⁷ [122], X ₀ ¹⁸ [121], X ₀ ¹⁹ [20
1], X ₀ ²⁰ [201], X ₀ ²¹ [210], X
₀ ²² [211], X ₀ ²³ [212], X ₀ ²⁴ [22
0], X ₀ ²⁵ [221], and X ₀ ²⁶ [222].

The address of the final result data at this time has a relationship in which the digit position is exactly inverted from the address of the data before the Fourier transform when displayed in ternary number. This relationship is rearranged by the ternary digit position reversing unit 23A into the same address as the address of the data before conversion. For example, when the final result data is transferred to the memory 22B in the third stage P3, the ternary number register 3 held in the ternary number register 3
Three-valued address of the data before Fourier transform of 3 [00
0], [100], [200], [010], [11]
0], [210], [020], [120], [22
0], [001], [101], [201], [01]
1], [111], [211], [021], [12]
1], [221], [002], [102], [20]
2], [012], [112], [212], [02]
2], [122], and [222] are sequentially inverted in their digit positions by the ternary digit position inverting section 23A, and the inverted ternary address is displayed.

[000], [001], [00
2], [010], [011], [012], [02]
0], [021], [022], [100], [10]
1], [102], [110], [111], [11]
2], [120], [121], [122], [12
1], [201], [201], [210], [21]
1], [212], [220], [221], [22
2] is held in the ternary register 34.

Specifically, as shown in FIG. 7, the five 3-1 selectors SE1 to SE of the ternary digit position reversing unit 23A are used.
5 inverts the 3 ⁰ , 3 ¹ , 3 ² digit bits of the ternary number register 33 based on the inversion control signals N3 to N5. For example, the digit position of the address [210] is reversed and [01
2]. As a result, the address of the ternary number held in the ternary number register 34 becomes 2 by the 3 / 2-ary number conversion unit 35.
The address is converted into an address represented by a decimal number, which is selected by the multiplexer 37 based on the address selection signal S2. The binary display address with the digit position inverted is output to the memory 22B.

Therefore, at the end of the Fourier transform, 27 element data are stored in the memory 22B based on the write / read signal W / R. In this way, according to the FFT operation device according to the embodiment of the present invention, the butterfly operation unit 2
1, a multi-memory unit 22, a ternary address conversion unit 23, a data control unit 24, a control device 25, an address bus 26 and a data bus 27, the ternary digit position reversal unit 23A of the address conversion unit 23, Fourier transform Invert the digit position of the address of the ternary number display of the previous data, and
The address in decimal notation is output to the 3 / 2-ary number conversion unit 35.

Therefore, the address of the data before Fourier transform

[000], [001], [002], [01
0], [011], [012], [020], [02]
1], [022], [100], [101], [10]
2], [110], [111], [112], [12]
0], [121], [122], [121], [20]
1], [201], [210], [211], [21]
2], [220], [221], [222] Fourier transformed final result data [X ₀ ⁰ , X ₀ ¹ , X ₀ ² , X ₀ ³ ,
X ₀ ⁴ , X ₀ ⁰ , X ₀ ⁵ , X ₀ ⁶ , X ₀ ⁷ , X ₀ ⁸ , X ₀ ⁹ , X ₀ ¹⁰ ,
X ₀ ¹¹ , X ₀ ¹² , X ₀ ¹³ , X ₀ ^{1 4} , X ₀ ¹⁵ , X ₀ ¹⁶ , X
₀ ¹⁷ , X ₀ ¹⁸ , X ₀ ¹⁹ , X ₀ ²⁰ , X ₀ ²¹ , X ₀ ²² , X ₀ ^2
3 , X ₀ ²⁴ , X ₀ ²⁵ , X ₀ ²⁶ ] can be stored. As a result, the output data can be rearranged inside the device without depending on the software processing as in the conventional example. This makes it possible to read the Fourier-transformed data from the same address as the data before the Fourier transform.

As a result, the number N that can be represented by the radix p other than 2 is N.
It is possible to easily configure an apparatus for performing a fast Fourier transform on (= ^pn ) data. Further, according to the fast Fourier transform method of the present invention, the final result data after the Fourier transform can be efficiently rearranged to the original address before the Fourier transform. , Fast Fourier transform is possible.

Therefore, in the case where there is a large amount of data and it is more effective to match the configuration of the apparatus to the radix p = 2 than to match the radix p = 2, the data as in the present invention is obtained. By adopting the processing method, it is possible to reduce the memory capacity. In the embodiment of the present invention, the case where the address decoders of the memory 22A and the memory 22B correspond to the normal binary number display has been described. The address conversion unit 23 is reduced to only the digit position inversion unit 23A,
It is possible to simplify the FFT calculation device.

Further, in the fast Fourier transform device of the present invention, a memory means for directly storing the data before and after the Fourier transform is provided in the address of the ternary number display in place of the multi-memory part 22, so that further high speed data processing can be achieved. Can be realized. Thus, even in the case of a radix p other than 3, if a p-adic digit position reversing device is used,
The addresses can be rearranged efficiently.

[0056]

As described above, according to the fast Fourier transform device of the present invention, the p-adic digit position reversing means is provided to invert the address digit position of the p-adic representation of the data before the Fourier transform. This inverted p-adic address is output. Therefore, at the end of the Fourier transform,
It is possible to store the final result data that has been Fourier transformed at the address position of the data before the Fourier transformation. As a result, the output data can be rearranged inside the device without depending on the software processing as in the conventional example.

Further, according to the apparatus of the present invention, by further providing the storage means for directly storing the data before and after the Fourier transform at the address of the p-adic number display, the data processing can be further speeded up. Further, according to the fast Fourier transform method of the present invention, when N [ ^pn ] data represented by a radix p other than 2 is Fourier transformed, the final result data after the Fourier transform is efficiently converted into the original Fourier transform. It can be rearranged to the address before conversion.

Therefore, it is possible to perform fast Fourier transform in image identification, voice recognition, etc., which handles a huge amount of data. This greatly contributes to easily configuring a fast Fourier transform device that handles a radix p other than 2 and reducing the memory capacity of the device.

[Brief description of drawings]

FIG. 1 is a principle diagram of a fast Fourier transform device according to the present invention.

FIG. 2 is a configuration diagram of an FFT calculation device according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram (Part 1) of the butterfly computing unit according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram (part 2) of the butterfly computing unit according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a binary / ternary conversion unit according to an embodiment of the present invention and a supplementary explanatory diagram thereof.

FIG. 6 is an operation explanatory diagram of the binary / ternary conversion unit according to the embodiment of the present invention.

FIG. 7 is a configuration diagram of a girder position reversing unit according to the embodiment of the present invention.

FIG. 8 is a configuration diagram of a ternary / binary conversion unit according to an embodiment of the present invention and a supplementary explanatory diagram thereof.

FIG. 9 is a diagram (stage P1) showing an algorithm of the fast Fourier transform unit according to the embodiment of the present invention.

FIG. 10 is a diagram (stage P2) showing an algorithm of the fast Fourier transform unit according to the embodiment of the present invention.

FIG. 11 is a diagram (stage P3) showing an algorithm of the fast Fourier transform unit according to the embodiment of the present invention.

FIG. 12 is a configuration diagram of an FFT operation device according to a conventional example.

[Explanation of symbols]

 11 ... Arithmetic means, 12 ... Storage means, 13 ... Address conversion means, 13A ... P-adic digit position inverting means, 14 ... Control means.

Claims (5)

[Claims] 1. N [p ⁿ , n represented by a cardinal number p other than 2
= 1, 2, 3 ...] Fourier transform of the data, storage means (12) for temporarily storing the data before and after the Fourier transform, and a p-adic address for the binary representation of the data. An address conversion means (13) for converting the display address or the p-adic address to a binary display address, wherein the address conversion means (13) is a p-adic digit position inverting means (13A). ), The digit position inverting means (13A) inverts the digit position of the address in p-adic notation of the data before Fourier transform, and outputs the inverted address in p-adic notation. Fast Fourier transform device. 2. The fast Fourier transform device according to claim 1, wherein the storage means (12) temporarily stores data before and after Fourier transform at an address of binary number display or p-ary number display. 3. A method of performing Fourier transform of N [ ^pn ] data represented by a radix p other than 2, wherein the data assigned to an address represented by a p-adic number is Fourier-transformed, and is Fourier-transformed. A fast Fourier transform method characterized in that the final result data is rearranged into an address obtained by inverting the address digit position of the data before the Fourier transform. 4. Prior to the Fourier transform, the binary address of N [ ^pn ] data represented by a radix p other than 2 is converted into a p-address. The fast Fourier transform method according to claim 3. 5. The fast Fourier transform method according to claim 3, wherein the p-adic address of the final result data subjected to the Fourier transform is converted into a binary address.