JPH07160581A - Cache matching processing controller - Google Patents

Abstract

PURPOSE:To prevent performance from being lowered due to cache matching processing according to the increment of the number of CPUs. CONSTITUTION:In a multiprocessor system provided with second cache in a memory controller 2, a copy destination information field 2-2-1 representing on which first cache data in second cache is copied is provided in the second cache. The information of a CPU number, a CPU group number, plural CPUs, and plural CPU groups, etc., are efficiently provided in the copy destination information field 2-2-1, and when access is performed based on the information, a cache matching processing request is issued to the minimum number of CPUs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, and more particularly to a cache coincidence processing control device for a multiprocessor system.

[0002]

2. Description of the Related Art Conventionally, each CPU in an information processing device
Each had a cache with a copy of the memory. However, in the case of a multiprocessor system, when a store operation is performed on one cache, if another cache has the same memory content, the content becomes stale. As a conventional method for solving the cache coherency problem,
When a store operation was performed on a certain cache, a cache matching processing request, that is, a cache flush request was issued to all other caches.

In Japanese Patent Laid-Open No. 3-52043, the comparison result of the processor number 105 from the system control device 2 and the processor number of the own device is forcibly made to be inconsistent for all CPUs for use in debugging. An information processing device including a flip-flop 10 is disclosed. In this technique, it is necessary to match all CPU numbers.

[0004]

In recent years, the frequency of cache matching processing has increased in proportion to the increase in the number of CPUs of a multiprocessor. However, the same content is originally registered in a plurality of caches and the content is stored. It is said that the operation is rarely performed. However, in order to guarantee the cache coherency that occurs with such a low frequency, an originally useless cache matching processing request must be compared with all other CPU numbers as shown in Japanese Patent Laid-Open No. 3-52043, so that the original processing is stopped. The situation has occurred, which has become a serious problem in terms of performance. Furthermore, all CPs are used as tabs of cache memory
There was a problem that the U number had to be stored and the storage area of the memory had to be stored.

[0005]

The first device of the present invention comprises:
Central processing unit having a first cache memory (hereinafter C
PU) and a second cache memory having a directory including a copy destination CPU number of data or information indicating whether the same information is copied to a plurality of CPUs, and a second cache memory. When the cache memory is accessed, the comparison means compares the CPU number of the request source with the contents of the copy destination information field, and the access to the second cache memory is a read access. Are different CPU numbers, the contents of the copy destination information field are updated to the contents indicating that they have been copied to a plurality of CPUs, and when the second cache memory is accessed, the contents of the copy destination information field are requested. Copy destination information field updating means for updating the original CPU number, and the second cache memory Access is a store access and the comparison result of the comparison means is the same CPU number, a match processing request is issued. The access to the second cache memory is a store access and the comparison is performed. When the comparison result of the means is a different CPU number, a cache matching processing request is issued to the CPU registered in the copy destination information field, and the copy destination information field indicates that copying is performed to a plurality of CPUs. A second device of the present invention including a cache matching process control means for issuing a cache matching process request to the CPU of the first device, the CPU of the first device is divided into a plurality of groups, and the CPU is set in the copy destination information field. The information indicating whether or not the same information as the group number has been copied to a plurality of CPU groups is stored. The comparing means compares the CPU group numbers when the second cache memory is accessed, and the cache matching processing control means is such that the access to the second cache memory is a store access and the comparing means is the CPU. As a result of comparing the group numbers, when it is determined that the request source CPU and the copy destination CPU belong to the same group, a cache matching process request is issued to all CPUs in the group other than the request source CPU, and the copy destination CPUs are plural. When a group is indicated, a matching process request is issued to all CPUs, and the copy destination information field updating means updates the copy destination information field to the request source CPU group number.

According to a third device of the present invention, the CPU is divided into a plurality of groups in the first device, and the same information as the CPU number and the CPU group number is copied to the plurality of CPU groups in the copy destination information field. Information indicating whether or not the cache number is stored in the cache memory, and the comparison unit compares both the CPU number and the CPU group number when the second cache memory is accessed, and the cache matching process control unit stores the information. When the access of the second cache memory is a store access and the comparing unit detects the same CPU number, the cache matching processing request is not issued and the comparing unit has a different CPU number but the same CP.
When it is determined that the U group number is issued, a cache matching processing request is issued to all CPUs in the group other than the requesting CPU, and when the comparison means determines that the CPU group numbers are different, all CPUs in the registered group A cache matching process request is issued to all CPUs, and a matching process request is issued to all CPUs only when the copy destination information indicates that the same information is copied to a plurality of CPU groups. The updating means is characterized by updating the copy destination information field to the request source CPU number and the CPU group number.

[0007]

An embodiment of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, in one embodiment of the present invention, ten CPUs (1-0 to 1-9) are connected to a memory controller (2). Also, CPU0 (1-0) ~
CPU4 (1-4) is group 0, CPU5 (1-5)
~ CPU9 (1-9) is divided into groups such as group 1. Although not shown in the figure, each CPU has a first cache memory therein. The second cache memory is provided in the memory controller (2). In the directory (2-2) of the second cache memory, a copy destination information field (2-2) for storing data copy destination CPU number group number or information indicating whether the same information is held across a plurality of CPU groups is stored. -1) is provided. When the memory control device (2) accesses the request processing unit (2-1) or the second cache memory, the CPU number of the request source from the request processing unit (2-1) and the copy destination information. Comparison means for comparing with the contents of the field (2
-5), when the access of the second cache memory is a read access, and the comparison result from this comparing means is a different CPU number, the contents of the copy destination information field have been copied to a plurality of CPUs. When the contents are updated to the contents shown and the access to the second cache memory is a store access, the contents of the copy destination information field are changed to the request source CP.
The copy destination information field updating means (2-3) for updating to at least one of the U number and the CPU group number, and the case where the access to the second cache memory is a store access and the comparison result of the comparing means is the same. CP
If it is a U number, no match processing request is issued, and if the access to the second cache memory is a store access and the comparison result of the comparing means is a different CPU number, it is registered in the copy destination information field. Is C
A cache matching process control means for issuing a cache matching process request to all CPUs when a cache matching process request is issued to a PU and the copy destination information field indicates that copying is being performed to a plurality of CPUs ( Two
-4) is included.

Next, the operation of one embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIGS. 1 and 2, the CPU0 is now
As a result of the access to the memory controller (2) from (1-0), C is stored in the second cache in the memory controller.
The operation when PU0 has registered data having a copy will be described. At this time, "0000" is written in the copy destination information field (2-2-1) in the second cache to indicate that the copy destination is CPU0.

First, the case where a read request to the second cache is issued will be described. When a read request is issued to the second cache, the request processing unit (2-1) sends the request source to the comparator (2-5). When the request source is the CPU 0, the comparator (2-5) detects that the contents of the copy destination information field match, and as a result, the copy destination information field updating means (2-3) causes the copy destination information field to be updated. It is determined that updating of is unnecessary.

Next, when the request source is the CPU 1, the comparator (2-5) notifies the copy destination information field update means that the request source and the copy destination information field do not match, and the update means are in the same group. Since the same data is held in the CPU 0 and the CPU 1 which are the same, the copy destination information field is "1011" indicating the group 0.
To update. Next, when the request source is the CPU 5, the copy destination information field updating means (2-3) holds the same information over different groups, and therefore the copy destination information fields indicate a plurality of groups. "1
111 "is updated.

Next, a case where a write request for the second cache memory is generated will be described.

When there is a write request to the second cache memory, the request processing section (2-1) sends the request source to the comparator (2-5). If the request source is the CPU 0, the comparator (2
-5), and as a result, the matching processing control means (2-4) judges that the cache matching processing request is dependent. Next, when the request source is the CPU 1, the comparator (2-5) detects that the request source and the copy destination do not match, and the matching processing control means (2-4) issues a cache matching processing request to the CPU 1. Then, the copy destination information field updating means updates it to "0001" to show that CPU0 has only one copy. Even when the request source is the CPU 5, the matching processing control means (2-4) issues a matching processing request to the CPU 0, and the copy destination information field updating means (2-3) indicates that the copying destination is the CPU 5. Therefore, it is updated to "0101".

Next, the copy destination information field is group 0.
That is, the operation when there is an access request to the second cache memory when it is "1011" will be described. First, when a read request is issued, the copy destination information field updating means needs to be updated when a read request is issued from a CPU in group 0, that is, any one of CPUs 0, 1, 2, 3, and 4. Judge not to.

CPU in group 1, ie CPU
When a read request is issued from any one of 5, 6, 7, 8 and 9, the copy destination information field updating means indicates that the copy destinations are spread over a plurality of groups, and therefore, "11".
11 ". Next, when there is a write request, a match processing request is issued to all CPUs of group 0 other than the requesting CPU regardless of which CPU is the requesting source,
The copy destination information field updating means (2.3) updates the request source CPU number to indicate that the request source is the only copy destination.

Finally, the operation when there is an access request to the second cache memory when the copy destination information field is "1111" indicating that there are copies in a plurality of groups will be described.

First, when there is a read request, the copy destination information field updating means (2-3) determines that there is no need to update the copy destination information field regardless of which CPU has issued the read request. When a write request is issued next, the match processing control means (2-4) issues a match processing request to all CPUs other than the request source regardless of which CPU is the request source, and the copy destination information field. The updating means (2-3) updates the CPU number of the request source, which indicates that the request source CPU is the only copy destination.

[0019]

As described above, according to the present invention, C is stored in the second cache directory in the memory control device.
By efficiently holding the copy status of the first cache in the PU with a small hardware investment, it is possible to prevent unnecessary cache matching processing requests from being issued to the CPU. It has the effect of preventing deterioration.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a copy destination information field according to an embodiment of the present invention.

[Explanation of symbols]

 1-0 to 1-9 CPU0 to CPU9 2 Memory control device 2-1 Request processing unit 2-2 Directory of second cache memory 2-2-1 Copy destination information field 2-3 Copy destination information field updating unit 2- 4 coincidence processing control means 2-5 comparator 3 memory device

Claims (3)

[Claims] 1. A central processing unit having a first cache memory, and a copy storing the central processing unit number to which data is copied or information indicating whether or not the same information is copied to a plurality of central processing units. A second cache memory having a directory containing a destination information field; and comparing means for comparing the central processing unit number of the request source with the contents of the copy destination information field when the second cache memory is accessed, When the access to the second cache memory is a read access and the comparison results from the comparing means are different central processing unit numbers, the contents of the copy destination information field are copied to a plurality of central processing units. When the access to the second cache memory is a store access, the copy destination information file is updated. The copy destination information field updating means for updating the contents of the field to the requesting central processing unit number and the access to the second cache memory are store access, and the comparison result of the comparing means is the same central processing unit number. If no match processing request is issued, the access to the second cache memory is a store access, and the comparison result of the comparison means is a different central processing unit number, it is registered in the copy destination information field. When a cache matching process request is issued to the central processing unit and the copy destination information field indicates that copying is performed to a plurality of central processing units, a cache matching processing request is issued to all central processing units A cache coincidence processing control device comprising: a control unit. 2. The central processing unit is divided into a plurality of groups, and the copy destination information field includes a central processing unit group number and information indicating whether or not the same information is copied to the plurality of central processing unit groups. The first-stage comparison means for storing compares the number central processing unit group number that has accessed the second cache memory, and the cache coincidence processing control means determines that the access to the second cache memory is a store access. As a result of the comparison means comparing the central processing unit group numbers, when it is determined that the request source central processing unit and the copy destination central processing unit belong to the same group, all of the groups other than the requesting central processing unit When a cache matching processing request is issued to the central processing unit and the copy destination central processing unit indicates multiple groups Claim, characterized in that the said copy destination information field updating means issues a coincidence processing request to all the central processing unit for updating the destination information field to the requesting central processing unit group number 1
The cache coincidence processing control device described. 3. The central processing unit is divided into a plurality of groups, and whether or not the central processing unit number and the same information as the central processing unit group number are copied to the plurality of central processing unit groups in the copy destination information field. And the comparison means compares both the central processing unit number and the central processing unit group number when the second cache memory is accessed, and the cache coincidence processing control means When the access to the second cache memory is a store access and the comparing means detects the same central processing unit number, the cache matching processing request is not issued and the comparing means has different central processing unit numbers but the same central processing unit number. When it is judged to be the central processing unit group number All central processing units in the group other than the requesting central processing unit In the case where a cache matching processing request is issued to the central processing unit group numbers different from each other by the comparing unit, the cache matching processing request is issued to all the central processing units in the registered group, and the copy destination information field 2. The cache coincidence processing control device according to claim 1, wherein the updating means updates the copy destination information field to a requesting central processing unit number and a central processing unit number.