JPH07160540A - Runaway detector - Google Patents

Abstract

PURPOSE:To make a pattern area narrow and small and to reduce the load of a hardware by performing the runaway detection of an integrated circuit by using a software without using any timer. CONSTITUTION:This device is provided with a switching circuit 1 for switching, outputting the control instruction inputs of positive and negative values, shift register 2 composed of two bits for storing and transferring a control instruction input from the switching circuit 1 while shifting its digits one by one, and data shift means 3 for performing the data shift of the shift register 2 even when the control instruction input of the positive or negative value is generated at the shift register 2, and a runaway detecting means 4 judges the abnormality of the circuit corresponding to whether the data at the first bit and the second bit of the shift register 2 are matched or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a runaway detecting device for detecting runaway of a semiconductor integrated circuit without using a timer.

[0002]

2. Description of the Related Art FIG. 14 is a block diagram of a conventional microcomputer incorporating a watchdog timer as a runaway detecting means. In the figure, 101 indicates the inside of the CPU of the microcomputer. Reference numeral 102 denotes a program counter, which serves to indicate the address of the ROM 109 described later.

Reference numeral 103 denotes a stack register, a register for saving the value of the program counter 102 at the time of processing a subroutine call instruction or interrupt, and 104 an instruction control circuit for each functional block of the CPU 101 according to the instruction code read from the ROM 109. It works to control.

Reference numeral 105 denotes an accumulator, which calculates,
A register for performing data processing such as transfer and input / output, and 106 is an arithmetic logic unit, which performs arithmetic processing of data under the control of the instruction control circuit 104. An address bus 107 serves to output the contents of the program counter 102 to peripheral circuits.

Reference numeral 108 denotes a data bus, which is the ROM 109.
From the instruction code to the CPU 1. 10
9 is a ROM, and the microcomputer is a ROM 10.
It operates according to the instruction code (program) written in 9. Reference numeral 118 is a watchdog timer as one of the runaway detecting means.

Reference numeral 119 is an 8-bit up counter which counts up by a clock signal input via the signal line z. Reference numeral 120 denotes a reset circuit, which outputs a signal for resetting the CPU 101 by the overflow signal of the up counter 119 input through the signal line y through the signal line q.

Next, the operation will be described. The watchdog timer 118 detects a runaway of the CPU 101 and resets it. The initial value "00H" is set in the up counter 119, and when the reset of the microcomputer is released, the up counter 119 counts up according to the clock signal input via the signal line z.

When the up counter 119 continues to count up and overflows, an overflow signal is output to the reset circuit 120 via the signal line y, and the reset circuit 120 resets the CPU 101 via the signal line q. Generate a signal.

When the instruction control circuit 104 executes an instruction to initialize the watchdog timer 118, a signal for clearing the up counter 119 is generated via the signal line x,
The up counter 119 is initialized to "00H".

In the conventional microcomputer,
The runaway of the CPU 101 is monitored by arranging an instruction for initializing the watchdog timer 118 at a certain interval in the program, that is, arranging so that the up counter 119 does not overflow during normal operation.

[0011]

Since the conventional watchdog timer is constructed as described above, the upcounter 119 for the watchdog timer is necessary for detecting the runaway, and the presence of the upcounter 119 causes the microcounter 119 to operate. There is a problem that the pattern area of an integrated circuit of a computer or the like becomes very large and one timer is dedicated to a watchdog timer and cannot be used for other operations, which is uneconomical.

The invention of claim 1 has been made to solve the above-mentioned problems, and the pattern area can be narrowed by detecting the runaway of the integrated circuit by software without using a timer. An object of the present invention is to obtain a runaway detection device that can be implemented and can reduce the load on hardware.

It is an object of the invention of claim 2 to obtain a runaway detecting device which can reduce the pattern area by using the JK flip-flops and the D flip-flops and thereby economically perform the desired runaway detection. To do.

According to a third aspect of the present invention, a runaway detection device capable of performing a runaway detection according to a bit state of a shift register by determining whether a positive value or a negative value of three control command inputs is determined according to a combination condition. Aim to get.

According to a fourth aspect of the present invention, by using three sets of JK flip-flops and D flip-flops, it is possible to obtain a runaway detecting device which can reduce the pattern area and can surely and economically perform the desired runaway detection. The purpose is to

According to a fifth aspect of the present invention, by determining whether the positive or negative value of four or more control command inputs is a positive value or a negative value according to a combination condition, a runaway judgment can be performed according to the bit state of the shift register. The purpose is to obtain a possible runaway detection device.

It is an object of the present invention to provide a runaway detecting device capable of performing a runaway detection using four or more sets of JK flip-flops and D flip-flops.

According to the invention of claim 7, the shift register is controlled without using a special control command input and with a normal command used in the integrated circuit, that is, without increasing the number of commands, whereby the desired control is performed. It is an object of the present invention to obtain a runaway detecting device capable of detecting runaway of.

[0019]

According to another aspect of the present invention, there is provided a runaway detecting device which stores and transfers a control command input corresponding to a positive value and a negative value from a switching circuit while shifting the input by one digit.
A shift register having a bit structure and data shift means for performing data shift regardless of whether a positive or negative control command input occurs in the shift register are provided, and the first bit and the second bit of the shift register are provided. The circuit abnormality is judged based on whether or not the data of (1) match.

According to another aspect of the present invention, there is provided a runaway detecting device having first and second control command inputs of positive and negative values as clock pulses, and outputs a divided signal thereof and an inverted signal of the divided signal. 2 J-K flip-flops, a first exclusive NOR gate that receives the two divided signals, the inverted signal of the first J-K flip-flop, and the second J-K flip-flop First and second D flip-flops for temporarily holding respective outputs of the second exclusive NOR gate which receives the frequency-divided signal as input, and for data-shifting using the positive and negative control command inputs as clock pulses. And are provided.

The runaway detecting apparatus according to the invention of claim 3 is 3
Condition determining means is provided for determining whether one of the control command inputs is a positive value or a negative value based on a combination condition, and the control command input from the condition determining means is stored and transferred by shifting one digit by a shift register. The shift register is made to shift data when any of the three control command inputs occurs.

A runaway detecting apparatus according to a fourth aspect of the present invention has three control command inputs for which a positive value or a negative value is determined, as clock pulses, and a divided signal thereof and this divided signal. 1st, 2nd, 3rd which outputs the inversion signal of
J-K flip-flops, first, second, and third exclusive NOR gates that receive the outputs of the first, second, and third J-K flip-flops, and these first and second The first, second, and third D flip-flops are provided for temporarily holding the outputs of the second and third exclusive NOR gates and for shifting the data using the control command input as a clock pulse.

The runaway detecting device according to the fifth aspect of the present invention is 4
Condition determining means for determining which of one or more control command inputs is to be a positive value or a negative value is provided, and the control command inputs from the condition determining means are stored and transferred while shifting by one digit by a shift register. When any one of the control command inputs occurs, the shift register is made to shift data.

According to another aspect of the present invention, there is provided a runaway detecting device which has a plurality of positive or negative control command inputs as clock pulses, and outputs a divided signal of the clock pulses and an inverted signal of the divided signal. The above J-K flip-flops and four or more exclusive NOR gates to which the selected divided signal and inverted signal are input are provided, and four positive and negative control command inputs are used as clock pulses. The data is shifted to the above D flip-flop.

A runaway detecting device according to a seventh aspect of the present invention is a shift register, or a JK flip-flop and a D-type flip-flop.
Instead of the control command input for controlling the flip-flop, the command used in the integrated circuit is used.

[0026]

In the runaway detecting apparatus according to the present invention, the shift register is controlled by the control command input, the bit of the shift register is judged, and the first bit and the second bit of the shift register changed by the control command input. Are compared, and if they match, it is determined to be a runaway.

The runaway detecting device in the invention of claim 2 is
The JK flip-flop has a control command input as a clock pulse, and outputs a divided signal of the control command input and an inverted signal of this divided signal. Further, another JK flip-flop having the control command input as a clock pulse outputs a frequency division signal of the control command input.

Then, the exclusive NOR gate having the frequency-divided signal as an input signal outputs an output signal, and the exclusive NOR gate having an inverted signal and a frequency-divided signal as an input signal also outputs the output signal in the same manner as described above. To do.

Therefore, the D flip-flop having each output signal as an input has a control command input as a clock pulse, outputs a determination signal, and outputs a runaway detection signal by using these as inputs of a NAND gate.

The runaway detecting device in the invention of claim 3 is
The shift register is controlled by three control command inputs, the bit determination of the shift register is performed with high accuracy, the first bit and the second bit of the shift register changed by the control command input are compared, and if they match, Judged as a runaway.

The runaway detecting device according to the invention of claim 4 is
Each of the three JK flip-flops has one control command input as a clock pulse, and outputs each divided signal.

Further, the 3-input exclusive NOR gate determines whether or not each signal is matched, and these outputs are used as the input of each D flip-flop, and the control command input is used as the clock pulse of these three D flip-flops. When the control signal is input, a control signal is output, and the runaway detection signal is output by using this control signal as an input of a 3-input NAND gate.

The runaway detecting device according to the invention of claim 5 is
The positive or negative value of four or more control command inputs is determined by a combination condition, the shift register determination is performed with higher accuracy, and the runaway determination according to the bit state is performed.

The runaway detecting device in the invention of claim 6 is
Runaway detection can be performed using four or more sets of JK flip-flops and D flip-flops.

The runaway detecting device in the invention of claim 7 is
Without using special control command inputs, with the normal commands used in integrated circuits, that is, without increasing the number of commands,
It controls the shift register so that the desired runaway can be detected.

[0036]

【Example】

Example 1. An embodiment of the invention of claim 1 will be described below with reference to the drawings. In FIG. 1, 1 is a switching circuit, 2 is a shift register connected to the switching circuit 1, 3 is an OR gate, 4
Is a runaway detection circuit (runaway detection means), L1 and L2 are control command inputs to the NOR gates 1a and 1b and the OR gate 3 which constitute the switching circuit 1, L3 is a reset signal of the NOR gate 1b and the shift register 2, and L4 is a runaway detection signal. Is.

Next, the operation will be described. First, when "H" is input as the control command input L1, "H" is output from the switching circuit 1 and "H" is set to the first bit of the shift register 2. When the control command input L1 is “L” and the control command input L2 is “H”, the switching circuit 1 outputs “L” and sets the first bit of the shift register 2 to “L”. To be done.

The shift register 2 has control command inputs L1,
Since the output of the OR gate 3 having L2 as an input is used as a clock pulse, data shift is performed at the rising edge of either one of the control command inputs L1 and L2. Also, by inputting the reset signal L3, the first bit is "H", 2
Set the bit to "L".

Here, the runaway determination method will be described. The above-described operation is performed to shift the first bit and the second bit of the shift register 2.
The value of the bit is determined by the runaway detection circuit 4, and if they match, the runaway detection signal L4 is set to "H".

Next, the runaway determination method will be described with reference to the timing chart of FIG. First, the reset signal L
3, the switching circuit 1 and the shift register 2 are initialized.

Subsequently, when the control command input L1 is inputted, the input a of the shift register 2 becomes "H", but the data "L" at the time of initialization is inputted to the first bit of the shift register 2. To be done.

At this time, the second bit of the shift register 2 is set to "H" by shifting this data from the data of the first bit being "H" by initialization. Here, "L" is output as the runaway detection signal L4 from the first bit "L" and the second bit "H" of the shift register 2.

Next, when the control command input L2 is input,
The input a of the shift register 2 is set to "L", the first bit data "L" is data-shifted to the second bit of the shift register 2, and the control command input L1 is input to the first bit. Input a of shift register 2 when
“H” is input.

Here, when the first bit and the second bit of the shift register 2 are compared, since they do not match, "L" is output as the runaway detection signal L4. That is, in the case of normal operation, the above operation is repeated.

The operation when the control command input L1 is continuously input is the same as the operation when the control command input L1 is first input, but next when the control command input L1 is input again. , The input a of the shift register 2 is set to “H”, the first bit data “L” is data-shifted to the second bit of the shift register 2, “H” is input to the first bit, and the runaway occurs. The detection signal L4 is "L".

Next, when one of the control command inputs is input, the data "H" of the input a of the shift register 2 is input.
Is set to the first bit, the data of the first bit is data-shifted to the second bit, and "H" is set to the second bit. Here, when the first bit and the second bit are compared, since they match, the abnormality detection signal L4 becomes "H" and it is determined that the runaway.

Example 2. FIG. 3 shows an embodiment of the invention of claim 2, wherein 5a is a JK flip-flop (first JK flip-flop), and this JK flip-flop 5a is a control command as a clock pulse. It has an input L1 and outputs a divided signal L5 of the control command input L1 and an inverted signal L6 of this divided signal L5. Further, the JK flip-flop (second JK flip-flop) 5b having the control command input L2 as a clock pulse outputs the divided signal L7 of the control command input L2.

Next, the divided signals L5 and L7 are input signals.
An exclusive NOR gate (a first exclusive NOR gate) 6a having an output signal L8 outputs an output signal L8, and an exclusive NOR gate (second exclusive NOR gate) having an inverted signal L6 and a divided signal L7 as an input signal. 6b
Also outputs the output signal L9 in the same manner as above.

Therefore, the D flip-flop 7c as the first D flip-flop and the D flip-flop 7d as the second D flip-flop, which have the output signals L8 and L9 as their inputs, respectively, receive the control command as clock pulses. L1 and L2, and a determination signal L1
0 and L11 are output. When the reset signal L3 is "H", the D flip-flops 7c and 7d are "H". Then, the above determination signals L10 and L11
Is input to a NAND gate (runaway detection means) 8 and a runaway detection signal L12 is output.

In order to perform the above operation, the control command inputs L1 and L2 must be alternately input. In the normal operation, the runaway detection signal L12 is "L", but the control command input is If L1 and L2 are not input alternately, the runaway detection signal L12 becomes "H", and it can be determined that the runaway.

This will be described with reference to the timing chart shown in FIG. When "H" is input to the reset signal L3, the initialization of all the JK flip-flops 5a and 5b and the D flip-flops 7c and 7d is performed,
"L" is set to the JK flip-flops 5a and 5b, and "H" is set to the D flip-flops 7c and 7d.

Next, when the control command input L1 is input,
The output of the JK flip-flop 5a becomes "H", and J
The output of the -K flip-flop 5b remains "L" because it remains unchanged from the initial setting. Then, by inputting these output data to the exclusive NOR gates 6a and 6b,
The input L8 of the D flip-flop 7c becomes "L", and the input L9 of the D flip-flop 7d becomes "H".

Here, the output L of the D flip-flop 7c
Reference numeral 10 is a clock pulse from the control command input L1 and the data "H" in the initial setting is data-shifted to "H"
Becomes Further, the output L11 of the D flip-flop 7d has no clock pulse from the control command input L2, and therefore remains the initial setting value "H". Therefore, NAND gate 8
The output L12 from is L.

On the other hand, in the next operation, the control command input L2
, The output L5 of the JK flip-flop 5a does not change, but the output of the JK flip-flop 5b does not change.
Output L7 becomes "H", and input L8 and L9 data become "H" and "L", respectively. Here, the output L10 of the flip-flop 7c does not change data, but the output L11 of the D flip-flop 7d is set to "H" by the clock pulse from the control command input L2. Therefore, the runaway detection signal L12 becomes "L", and it is determined that the operation is normal.

Next, regarding the operation at the time of runaway, when the control command input L1 is again provided next to the operation when the control command input L1 has been described above, the divided signal L5 From FIG. 4, "H" changes to "L", and the divided signal L7 remains "L".

Therefore, the input L8 becomes "H" and the input L
9 becomes "L". Here, the output of the D flip-flop 7c is data-shifted from the data "L" before the data is input from the control command input L1 by the clock pulse as the control command input, and the output L10 becomes "L". As a result, the output of the runaway detection signal L12 becomes "H", and it is determined that the runaway is occurring.

Example 3. FIG. 5 shows an embodiment of the invention of claim 3, in which L1, L2 and L13 are control command inputs, and 1 of the shift register 2 is controlled by the control command input L1.
When the value of the bit is set, the input of the control command input L2 is permitted, and the control command input L13 is treated the same as the control command input L1.

Similarly, when the value of the first bit of the shift register 2 is set by the control command input L2, the input of the control command input L13 is permitted, and the control command input L1 is treated the same as the control command input L2. . When the value of the first bit of the shift register 2 is set by the control command input L13, the input of the control command input L1 is permitted, and the control command input L2 is treated the same as the control command input L13. Here, P inputs each control command input L1, L2, L13, and outputs the inverter I
It is a condition determination means for inputting a condition determination output to the shift register 2 via V.

Further, the clock pulse of the shift register 2 is used as the output of the OR gate (data shift means) 3A for the above three control command inputs, and the data shift of the shift register 2 is performed if any of the three control command inputs occurs. . The runaway determination method is performed by the same operation as that of the first embodiment, and this operation is as shown in the timing chart of FIG. 6, and since the details are the same as those of the first embodiment, the duplicate description thereof will be omitted here. .

Example 4. FIG. 7 shows an embodiment of the invention of claim 4. Reference numerals 5e, 5f, and 5g denote JK flip-flops as first, second, and third JK flip-flops, which have control command inputs L1, L2, and L13 as clock pulses, and divide the respective frequencies. Signal L5
Outputs L7 and L15.

Further, 9e, 9f, and 9g are three-input exclusive-nor gates as the first, second, and third exclusive-nor gates, which are used to determine the matching of the respective signals. The outputs of the exclusive NOR gates 9e, 9f, 9g are input to the D flip-flops 7e, 7f, 7g as the first, second, and third D flip-flops, respectively, and these three D flip-flops 7e, 7f, The control command inputs L1, L2 and L13 are input as 7 g clock pulses and the control signals L16, L17 and L18 are output.

Further, the control signals L16, L17, L
18 is input to a 3-input NAND gate (runaway detection means) 10 to output a runaway detection signal L12. FIG. 8 shows a timing chart of the actual operation of this embodiment, JK
Since the operations of the flip-flops 5e, 5f, 5g and the D flip-flops 7e, 7f, 7g are the same as those in the second embodiment, the duplicated description will be omitted here.

Example 5. FIG. 9 shows an embodiment of the invention of claim 5, which sets the value of the first bit of the shift register 2 by inputting the control command inputs L19-1 to L19 of the shift register.
19-n. For example, when the control command input L19-1 is set, the control command input L1
Inputs 9-2 to L19- (n-1) are permitted, and the input of the control command input L19-n is the same as that of L19-1.
When the control command inputs L19-2 to L19-n are set, the same operation as described above is performed. 3B
Is an OR gate as a data shift means for inputting N control command inputs, and Q is each control command input L19-1.
.About.L19-n, and a condition determining means for inputting a condition determining output to the shift register 2 via the inverter IV.

The runaway detection method is performed by the same operation as that of the first embodiment, and in FIG. 10, the control signal L19-n is n.
The timing chart shows the operation when = 4. Here, since the initial setting and the operation of the shift register 2 are the same as those in the first embodiment, the duplicated description will be omitted here.

When a runaway occurs as shown in FIG. 10, the input a of the shift register 2 becomes the same data for two clocks and is input to the shift register 2. As a result, the same operation as that of the first embodiment is performed, "H" is output as the runaway detection signal L12, and the runaway is determined.

Example 6. FIG. 11 shows an embodiment of the invention of claim 6 in which control command inputs L19-1 to L1 are input.
9-n is input as a clock pulse of the J-K flip-flops 5h to 5n and the D flip-flops 7h to 7n, and each of the determination signals is output from the D flip-flops 7a to 7n, and a multi-input NAND gate (runaway detection). Means 12 to output a runaway detection signal L12.

The difference between this embodiment and the other embodiments 1 and 2 is that the control command inputs L19-1 to L19-n have priority, and for example, the control command input next to the control command input L19-1 is L19. -2 and L19-3 are good points. Therefore, even in the circuit configuration, the control command input L19
D flip-flop 7 having -3 as a clock pulse
The input of j is the output of the multi-input exclusive NOR gate 11j excluding the control command input L19-2.

The operation timing is shown in the timing chart of FIG. Here, since the individual operation timings of the J-K flip-flops 5h to 5n and the D flip-flops 7h to 7n are the same as those in the second embodiment, the duplicate description thereof will be omitted here.

Example 7. FIG. 13 shows an embodiment of the invention of claim 7. Although the operation described in each of the first to sixth embodiments depends on the input of the control instruction, the operation described above can be performed by replacing the control instruction with the instruction originally used in the integrated circuit. This makes it possible to reduce the increase in the number of instructions.

[0070]

As described above, according to the first aspect of the present invention, the shift register having a 2-bit structure stores and transfers the control command input corresponding to the positive value and the negative value from the switching circuit while shifting the input by one digit. And a data shift means for performing data shift regardless of whether a positive or negative control command input occurs in the shift register, and the first bit data and the second bit data of the shift register match. Since it is configured to judge the circuit abnormality based on whether or not it is possible to reduce the pattern area and reduce the load on the hardware by detecting the runaway of the integrated circuit by software without using a timer. There is an effect that what can be obtained.

According to the second aspect of the present invention, the first and second J's having positive and negative control command inputs as clock pulses and outputting the frequency-divided signal and the inverted signal of the frequency-divided signal. A K flip-flop, a first exclusive NOR gate which receives the two divided signals, and an inverted signal of the first JK flip-flop,
Each output of the second exclusive NOR gate, to which the frequency-divided signal of the second JK flip-flop is input, is temporarily held, and data is shifted by using the positive and negative control command inputs as clock pulses. First and second
Since it is configured to include the D flip-flop of
By using the JK flip-flops and the D flip-flops, the pattern area can be reduced, and this has the effect of obtaining the desired runaway detection economically.

According to the invention of claim 3, condition determining means for determining whether the three control command inputs are positive values or negative values by a combination condition is provided, and the control command inputs from the condition determining means are provided. The shift register stores and transfers the data while shifting it by one digit, and when any of the three control command inputs occurs, the shift register is configured to perform data shift. By deciding which of the negative values is used in combination, there is an effect that a runaway detection can be performed with higher accuracy according to the bit state of the shift register.

According to the fourth aspect of the present invention, three control command inputs for which a positive value or a negative value is determined are provided as clock pulses, and a divided signal thereof and an inverted signal of the divided signal are provided. For outputting the first, second, and third JK flip-flops, and the first, second, and third J-K flip-flops for receiving the outputs of the first, second, and third JK flip-flops, respectively. The first, second, and third Ds that temporarily store the output of the exclusive NOR gate and the first, second, and third exclusive NOR gates, and shift the data using the control command input as a clock pulse. Since the flip-flops are provided, three sets of JK flip-flops and D flip-flops can be used to reduce the pattern area and to reliably and economically perform the desired runaway detection. There is an effect to be.

According to the invention of claim 5, condition determining means for determining which of four or more control command inputs is a positive value or a negative value is provided, and the control command inputs from the condition determining means are shifted. The shift register stores and transfers the data while shifting it by one digit, and when any of the three control command inputs occurs, the shift register is configured to perform data shift. Therefore, four or more control command inputs are positive values. By deciding which one of the negative values is to be used, it is possible to obtain the one capable of performing the runaway judgment according to the bit state of the shift register.

According to the invention of claim 6, four or more J's having a plurality of positive or negative control command inputs as clock pulses and outputting a divided signal thereof and an inverted signal of the divided signal. -K flip-flops and four or more exclusive NOR gates to which the selected frequency-divided signal and inverted signal are input are provided, and four or more D-values are used with the positive and negative control command inputs as clock pulses. Since it is configured to shift data to the flip-flop, 4
It is possible to obtain the one capable of performing the runaway detection by using the JK flip-flops and the D flip-flops of more than one set.

According to the seventh aspect of the present invention, the instruction used in the integrated circuit is used instead of the control instruction input for controlling the shift register or the JK flip-flop and the D flip-flop. It is possible to control the shift register without using the control command input and with the normal commands used in the integrated circuit, that is, without increasing the number of commands, and thereby to obtain the desired runaway detection. It is effective.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a runaway detecting device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing signals of respective parts of the circuit in FIG.

FIG. 3 is a circuit diagram showing a runaway detecting device according to an embodiment of the invention of claim 2;

FIG. 4 is a timing chart showing signals of various parts of the circuit in FIG.

FIG. 5 is a circuit diagram showing a runaway detecting device according to an embodiment of the invention of claim 3;

6 is a timing chart showing signals of various parts of the circuit in FIG.

FIG. 7 is a circuit diagram showing a runaway detecting device according to an embodiment of the invention of claim 4;

8 is a timing chart showing signals of various parts of the circuit in FIG.

FIG. 9 is a circuit diagram showing a runaway detecting device according to an embodiment of the invention of claim 5;

10 is a timing chart showing signals of various parts of the circuit in FIG.

FIG. 11 is a circuit diagram showing a runaway detecting device according to an embodiment of the invention of claim 6;

12 is a timing chart showing signals of various parts of the circuit in FIG.

FIG. 13 is a block diagram showing a runaway detecting device according to an embodiment of the invention of claim 7;

FIG. 14 is a block diagram showing a conventional watchdog timer.

[Explanation of symbols]

1 switching circuit 2 shift register 3, 3A, 3B OR gate (data shift means) 4 runaway detection circuit (runaway detection means) 5a, 5e JK flip-flop (first JK flip-flop) 5b, 5f JK Flip-flop (second JK flip-flop) 5g JK flip-flop (third JK flip-flop) 5h to 5n JK flip-flop 6a, 9e Exclusive NOR gate (First exclusive NOR Gate) 6b, 9f Exclusive NOR gate (second exclusive NOR gate) 9g Exclusive NOR gate (exclusive NOR gate 3) 7c, 7e D flip-flop (first D flip-flop) 7d, 7f D Flip-flop (second D flip-flop) 7g D flip-flop (Third D flip-flop) 7H～7n D flip-flop 8,10,12 NAND gate (runaway detection means) P, Q condition determining means 11h~11n EXCLUSIVE cycle Shiv NOR gate

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[Procedure amendment]

[Submission date] June 30, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 4

[Correction method] Change

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[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

[Procedure 3]

[Document name to be corrected] Drawing

[Correction target item name] Figure 9

[Correction method] Change

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[Figure 9]

Claims (7)

[Claims] 1. A switching circuit for switching and outputting positive and negative control command inputs, and a control command input from the switching circuit.
A shift register having a 2-bit structure for storing and transferring while shifting by digits, and a data shift means for performing data shift of the shift register regardless of whether a positive or negative control command input occurs in the shift register. , A runaway detecting device provided with a runaway detecting means for judging an abnormality of a circuit depending on whether the first bit data and the second bit data of the shift register match. 2. A first JK flip-flop which has a positive-valued control command input as a clock pulse and outputs a frequency-divided signal thereof and an inverted signal of the frequency-divided signal, and a negative-valued control command input. A second JK flip-flop which has a clock pulse and outputs a divided signal of the clock pulse, a first exclusive NOR gate which receives the two divided signals as an input, and the first JK flip-flop. Output of the second exclusive NOR gate, the first exclusive NOR gate, and the second exclusive NOR gate, which receive the inverted signal of the second flip-flop and the frequency-divided signal of the second JK flip-flop. While holding the
A first D flip-flop and a second D flip-flop for data-shifting with the positive and negative control command inputs as clock pulses, and outputs to the first D flip-flop and the second D flip-flop, respectively. A runaway detection device including a runaway detection means for determining an abnormality in a circuit. 3. Condition determining means for determining whether the three control command inputs are positive values or negative values by a combination condition,
A shift register having a 2-bit structure for storing and transferring the control command input from the condition determining means while shifting the input by one digit;
Regardless of which of the three control command inputs occurs, the data shift means for causing the shift register to perform data shift and the circuit of the circuit depending on whether the first bit data and the second bit data of the shift register match. A runaway detecting device comprising a runaway detecting means for judging an abnormality. 4. A clock pulse having three control command inputs, which is determined by a combination condition, to be either a positive value or a negative value, and outputs a divided signal thereof and an inverted signal of the divided signal, respectively. A first JK flip-flop, a second JK flip-flop, a third JK flip-flop that outputs only a divided signal, and a first excursion that receives the three divided signals as an input. A bunoa gate, the inverted signal of the first JK flip-flop, the second JK flip-flop, and the third JK flip-flop.
A second exclusive NOR gate that receives the divided signal of the -K flip-flop, the above-mentioned inverted signal of the first JK flip-flop, the second JK flip-flop, and the third JK A third exclusive NOR gate having a frequency-divided signal of a flip-flop as an input;
The first D flip-flop and the second D flip-flop that temporarily hold the outputs of the second exclusive gate, the second exclusive NOR gate, and the third exclusive NOR gate of A D flip-flop and a third D flip-flop, and a runaway detecting means for judging a circuit abnormality based on each output of the first D flip-flop, the second D flip-flop and the third D flip-flop are provided. Runaway detection device. 5. A condition determining means for determining whether a positive value or a negative value of four or more control command inputs is a combination condition, and a control command input from the condition determining means is stored while shifting by one digit. , A 2-bit shift register for transferring, a data shift means for causing the shift register to shift data when any of the three control command inputs occurs, and a first bit and a second bit of the shift register. Runaway detection device provided with a runaway detection means for judging an abnormality of the circuit depending on whether or not the data of the above are matched. 6. Four or more JK flip-flops which have a plurality of positive or negative control command inputs as clock pulses, and which output a divided signal of the clock pulses and an inverted signal of the divided signal, and a selection. Four or more exclusive NOR gates that receive the divided signal and the inverted signal that have been input,
Based on four or more D flip-flops for temporarily holding the output of each of the exclusive NOR gates and data-shifting the positive and negative control command inputs as clock pulses, and each output of the D flip-flops. A runaway detecting device comprising a runaway detecting means for judging a circuit abnormality. 7. The runaway detection according to claim 1, wherein an instruction used in an integrated circuit is used instead of the control instruction input for controlling the shift register or the JK flip-flop and the D flip-flop. apparatus.