JPH0715893A - On/off circuit for switch - Google Patents

Abstract

PURPOSE:To prevent the erroneous turning-on and erroneous turning-off of a switch for a distribution system due to the nim away, noises, etc., of a CPU. CONSTITUTION:The turn-on command and turn-off command of a switch 21 are made in dual operations as turn-on 1, 2 and turn-off 1, 2 while each coincidence of turn-on 1, 2 or turn-off 1, 2 is detected by AND gates 2B1, 2, only turn-on 1, 2 or only turn-off 1, 2 can be decided by OR gates 2B3, 4 and an exclusive OR circuit 2B5, and an output from the exclusive OR circuit 2B5 is delayed output by a timer 2B6, thus preventing response to erroneous turn-on and erroneous turning-of commands.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a closing and opening circuit of a switch which does not respond to a wrong closing and opening command.

[0002]

2. Description of the Related Art FIG. 4 is a schematic diagram showing a general power distribution system. That is, this type of power distribution system includes a distribution automation control device (master station) 1 installed at a sales office, a slave station 2 installed on a pole and controlling and monitoring a switch 21 by a command from the master station 1, and It is composed of a communication line 3 for connecting the two. Further, the slave station 2 is installed on a pillar together with the switch 21, the control transformer 22, the power switch 23, the communication terminal box 24, etc., and functions as a terminal device of the distribution automation system. Reference numeral 4 indicates a distribution line. In FIG. 4, only one slave station and its peripheral devices are denoted by reference numerals and the others are omitted, but it goes without saying that other parts are also the same.

The slave station 2 is provided with a closing / opening circuit for controlling closing / opening of the switch 21 as shown in FIG. The closing / opening circuit is composed of a command receiving unit 2A for receiving a command from a master station (not shown), a relay circuit unit 2B, and the like. In addition, C1, C2, T1, T
2 and X indicate the relay and its contacts. Further, 4 is a distribution line, and 21 is a switch.

The operation will be described. For example, if a closing command is given while the switch 21 is open,
Since the relay and its contacts C1 and C2 operate, the switch 21 is closed and the relay X operates via the contacts C1 and C2 and T1 and T2, and the contact X holds the relay X by itself. Further, when an opening command is given in this state, the self-holding circuit of the relay X causes the contacts T1, T2
And the operating path of the switch 21 is also opened.

In such a circuit, when a CPU (not shown) runs out of control, the watchdog timer (WDT) which normally operates as shown in FIG. 6A cannot be reset as shown in FIG. 6B. As a result, if the logic circuit outputs an erroneous output as in (c) and operates the relays T1 and T2 as in (d), the self-operation of the relay X is performed as in (e). Since the holding circuit is opened and restored, the switch 21 is erroneously opened as shown in (f).

Further, noise is generated, for example, as shown in FIG.
As in (a) and (b), C1, C2 and T1, T2
When the operation command of the relay is given, the self-holding circuit of the relay X is opened and restored as shown in (c), so that the switch 21 is erroneously opened as shown in (c). Although the case of erroneous opening has been described above, the same applies to the case of erroneous insertion.

[0007]

As described above, when the CPU runs away or generates noise, the switch 21 may be erroneously opened or erroneously turned on by an erroneous command. In particular, erroneous opening must be avoided in order to maintain a normal power supply to the equipment at the subsequent stage. Therefore, an object of the present invention is to prevent the switch from being accidentally opened or accidentally closed even if the CPU goes out of control or noise occurs.

[0008]

In order to solve such a problem, according to the present invention, a distribution line is provided in a slave station connected to a master station via a communication line and receives an instruction from the master station. In the closing and opening circuit of the switch for controlling the switches respectively connected to the predetermined positions of the switch, the closing and opening commands for the switch are duplicated and output from the central processing unit (CPU), and the CPU There are a monitoring means for timely monitoring the runaway, a closing command match detecting means for detecting that two closing commands match, an opening command matching detecting means for detecting that two opening commands match, and two closing commands. An interlock means for outputting an output according to each command when the two coincide with each other or when two opening commands coincide with each other, and an interlock means for maintaining the state until then, and the interlock means. Provided a timer means for outputting the output of al delayed a predetermined time, by longer than the monitoring time of said monitoring means monitoring time by the timer means,
The feature is that it does not respond to erroneous input and erroneous opening commands.

[0009]

[Function] In addition to providing the interlock means, the WDT
By providing a timer for monitoring for a time longer than the overflow time, it is possible to reliably prevent erroneous closing and opening of the switch due to CPU runaway or noise.

[0010]

1 is a circuit diagram showing an embodiment of the present invention. In this embodiment, as is clear from the figure, an AND gate 2B is provided in the relay circuit section 2B as compared with that shown in FIG.
1, 2B2, OR gates 2B3, 2B4, an exclusive OR (EOR) circuit 2B5, a timer 2B6, etc. are added. Although not shown, it is assumed that a monitoring unit (WDT or the like) for monitoring the time of the CPU is also provided.

That is, the AND gate 2B1 detects whether or not the two closing commands (closing 1, 2) match, and the AND gate 2B2 checks whether or not the two opening commands (open 1, 2) match. To detect. The inputs 1 and 2 and the releases 1 and 2 are input to the OR gates 2B3 and 2B4, and the exclusive OR (EOR) circuit 2B5 performs the EOR operation. Therefore, for example, if the two inputs 1 and 2 match, the output of the AND gate 2B1 becomes high, and if the openings 1 and 2 are low, the output of the EOR circuit 2B5 becomes high. Also, for example, when there are either one of the two inputs 1 and 2, if the outputs 1 and 2 are low, the output of the EOR circuit 2B5 becomes high, but at this time, the output of the AND gate 2B1 remains low. is there.

That is, when the two injections 1 and 2 coincide with each other, the injection command is validated, and when only one of the injections 1 and 2 is output, an output for maintaining the current state is output. This relationship is the same as in the case of the open command. When the open commands are the same as the open command, the open command is valid, and when there is only one of the open commands 1 and 2, the output for maintaining the current state is output. ing.

From this, OR gates 2B3 and 2B4
It can be said that the EOR circuit 2B5 forms an interlock circuit having a kind of interlock function. The output from the interlock circuit is output by the timer 2B6 for a certain period of time, for example, the watchdog timer W.
The relay P is driven by the output of 25 mS for detecting the overflow of DT, delayed by about 30 mS with a slight allowable value added.

Next, the operation of the circuit of FIG. 1 when the CPU runs away will be described with reference to FIG. This is because the watchdog timer (WDT), which normally operates as shown in (a), is not reset as in (b) as in the case of FIG. It is assumed that an erroneous output (opening 1, 2) is output.

In this case, while the relay T operates by opening and closing 1, the output of the interlock circuit becomes high, but this output is delayed by the timer 2B6, and the output is delayed by 30 m.
It is not output until S has elapsed. However, when 30 ms has elapsed, it is considered that the CPU runaway has been detected and the logic output has returned to normal, so the P relay does not operate as shown in FIG. )
The operating state is maintained as described above, and the accidental opening of the switch does not occur. In other words, a normal command is usually 30 ms
Since it continues even after the passage of time, this distinguishes between normal time and abnormal time.

FIG. 3 is a waveform diagram for explaining the operation when noise is generated in FIG. This is the same as in the case of FIG. 7, noise is generated, and for example, (a), (b)
As described above, it is assumed that an operation command for the C and T relays is generated. In this case as well, the P relay does not operate as in (c), so the X relay also maintains the operating state as in (d), and erroneous opening of the switch as in (e) does not occur. become.

[0017]

According to the present invention, since the interlock circuit is provided and the timer for monitoring the time longer than the time when the WDT overflows is provided, it is possible to reliably prevent erroneous closing and opening of the switch. Therefore, there is an advantage that the protection can be achieved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining an operation when the CPU of FIG. 1 runs out of control.

FIG. 3 is an explanatory diagram for explaining an operation due to noise in FIG.

FIG. 4 is a schematic diagram showing a general example of a power distribution system.

FIG. 5 is a circuit diagram showing a conventional example.

FIG. 6 is an explanatory diagram for explaining an operation when the CPU of FIG. 5 runs out of control.

FIG. 7 is an explanatory diagram for explaining an operation due to noise in FIG.

[Explanation of symbols]

1 ... Parent station, 2 ... Slave station, 2A ... Command receiving section, 2B ... Relay circuit section, 2B1, 2B2 ... AND gate, 2B3, 2B
4 ... OR gate, 2B5 ... Exclusive OR (EOR) circuit, 2B6 ... Timer, 3 ... Communication line, 4 ... Distribution line, 21 ...
Switch, 22 ... Control transformer, 23 ... Power switch, 2
4 ... Terminal box, C, C1, C2, T, T1, T2, P, X
…relay.

Claims (1)

[Claims] 1. A switch which is provided in a slave station connected to a master station via a communication line, and which receives a command from the master station and controls switches respectively connected to predetermined locations of a distribution line. In the closing / opening circuit, the central processing unit (C
PU) and output each in duplicate, and CP
A monitoring means for timely monitoring the runaway of U, a closing command match detecting means for detecting that two closing commands match, an opening command matching detecting means for detecting that two opening commands match, and two closing commands. When the commands match or when the two opening commands match, an output corresponding to each command is output, and if not, an interlock means for maintaining the state up to that time and an output from the interlock means for a predetermined time. A timer means for delaying the output is provided, and the monitoring time by this timer means is made longer than the monitoring time by the monitoring means so that it does not respond to an erroneous input or erroneous opening command. Switch on / off circuit.