JPH0715452A - Multiplex transmission method and its multiplex transmitter - Google Patents

Abstract

PURPOSE:To enhance the safety of the transmitter by detecting a fault of a communication control section, a fault of an oscillation stop of a clock generating section or a fault of a transmission line and an abnormal state such as collision of signals on the transmission line. CONSTITUTION:In the multiplex transmitter connecting to a bus MB, having a communication control circuit 12 receiving sequentially data from the bus, storing data received sequentially in a reception buffer 19 and outputting the data to a load from an output port 16 via an output circuit 15, a port control circuit 17 monitoring data sent to the output port 16 controls the output port so that a load connecting to the output port is fixed safely when at least part of the data is not changed in a predetermined way corresponding to the data received precedingly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex transmission method and a multiplex transmission apparatus connected to a multiplex transmission line for transmitting a data frame, and more particularly to a multiplex transmission method and a multiplex transmission apparatus for receiving data.

[0002]

2. Description of the Related Art Conventionally, a multiplex transmission device in this type of multiplex transmission method is connected to a transmission line (bus) composed of paired wires or the like. Then, in the multiplex transmission device, the communication control unit (LSI) writes the data of the frame structure received from this bus into the reception buffer memory (hereinafter referred to as “reception buffer”). Next, the port controller
The output port is appropriately changed according to the content of the written data, and this data is output to a desired controlled load (hereinafter simply referred to as “load”).

These multiplex transmission devices are connected to a bus to build a network, and the transmission method is CSMA.
/ CD (Carrier Sense Multiple Access / Collision Detect
ion) transmission method is used. These multiplex transmission devices are used, for example, in a local area network (LAN) for multiplex transmission of data in an automobile.

[0004]

However, in this multiplex transmission device, when the oscillation of the clock generation unit that supplies the clock for operating the communication control unit stops or the communication control unit itself fails, There was a problem that this could not be detected, unexpected data appeared at the output port, and the load connected to this output port became abnormal in some cases.

The present invention has been made in view of the above problems, and detects an abnormal state such as a failure of a communication control circuit, a stop of oscillation of a clock generation unit, a failure of a transmission line, or a signal collision on the transmission line. It is an object of the present invention to provide a multiplex transmission method and a multiplex transmission apparatus capable of increasing the safety of the apparatus.

[0006]

In order to solve this object, the present invention has a communication control circuit which is a communication control means which is connected to a transmission line (bus) and receives data from the bus. In the multiplex transmission device for outputting from the output port to the controlled load, the reception buffer memory which is the reception storage means for storing the received data, and the data sent from the reception storage means to the output port are monitored, There is provided a multiplex transmission device comprising a port control circuit which is a port control means for controlling the output port to a predetermined state when at least a part of the data does not change in a predetermined manner.

[0007]

Function: For example, the received predetermined data (specific data)
The least significant bit of is composed of a pattern that repeats at a predetermined interval, and when this least significant bit does not change in this pattern, the port control circuit causes the load connected to the output port to be safely fixed. Control this output port as described.

Therefore, even if unexpected data is written in the reception buffer due to a failure of the communication control circuit or the oscillation of the clock generator, the output port is controlled to a predetermined state, so that the load is abnormal. Will disappear.

[0009]

Embodiments of the present invention will be described with reference to the drawings of FIGS. FIG. 1 is a configuration diagram showing an example of the configuration of a multiplex transmission system used in the multiplex transmission method according to the present invention. Referring to FIG. 1, the multiplex transmission system includes a plurality of multiplex transmission devices (hereinafter referred to as “nodes”) 1 to 5.
And a transmission path (bus) MB to which the nodes 1 to 5 are connected. These nodes are connected to a bus MB via a bus interface circuit, which will be described later, and transmit frame-structured data to other nodes on the bus MB. In the multiplex transmission system according to the present invention, any topology such as a bus type, a ring type, or a star type can be applied to the transmission line topology.

As a concrete example of the multiplex transmission system according to the present invention, it is used, for example, for controlling an electric system in an automobile, and a switch, a sensor, and an actuator are arranged from their respective locations via a harness (electric wire in the automobile). Connected to the appropriate node and configured. That is, the instrument panel (hereinafter, referred to as “instrument panel”) node 1 is arranged in the vicinity of the meters ME1.
For example, the meter ME1 is driven by the data from the vehicle speed sensor S1 from the engine node 4, and the ON / OFF signal of the door switch SW1 from the door node 5 lights the indicator lamp in the meter ME1. Further, the instrument panel node 1 has a power window switch SW for driving the power window motor M1.
2 is connected.

The front node 2 is arranged on the front surface of the vehicle and has a headlamp switch SW from the cowl node 3.
3. The headlight R1 and the turn signal lamp R2 on the front of the vehicle are driven by the ON / OFF signal of the turn signal switch SW4. The cowl node 3 is arranged in the vicinity of the cowl portion, and is connected to a headlamp switch SW3, a turn signal switch SW4, and a door lock switch SW5 for driving the door lock motor M2.

The engine node 4 is arranged in the vicinity of the engine and is connected to a vehicle speed sensor S1 to control the engine / transmission. This control is performed by the microcomputer in the node based on the data of the vehicle speed sensor S1 and the like. Further, the engine node 4 has a vehicle speed sensor S1.
The data of the sensor is transmitted to each node, such as by encoding the data of (1) and transmitting it to the instrument panel node 1.

The door node 5 is arranged near the door,
The door switch SW1, the power window motor M1 and the door lock motor M2 are connected. The door switch SW1 is turned on when the door is open, and this on signal is transmitted from the door node 5 as a signal for lighting the indicator lamp in the instrument panel node 1.
Further, in the door node 5, the power window motor M1 is driven by the ON / OFF signal of the power window switch SW2 from the instrument panel node 1 to raise and lower the window. Further, the door node 5 is the cowl node 3
Door lock motor M2 is driven by the ON / OFF signal of door lock switch SW5 from
Unlocked.

In the above-mentioned multiplex transmission system, one node usually corresponds to a physical address on a one-to-one basis. In this embodiment, this address corresponds to 4-bit data (A
3, A2, A1, A0). For example, the instrument panel node 1 has an address 0 (0000), the front node 2 has an address 4 (0100), and the cowl node 3 has an address 8 (1000). Address 12 (1100) is assigned to the engine node 4, and address 15 (1111) is assigned to the door node 5. The address allocation is not limited to that of this embodiment, and any other address can be set as long as the system is optimally allocated.

FIG. 2 is a diagram showing an example of a format of a data frame transmitted between nodes via the bus MB. Referring to FIG. 2, this data frame is
SOF (Start Of Frame) indicating the beginning of the frame,
Priority (PRI) that determines the priority when data is sent to the bus MB by multiple nodes at the same time
And a control data area (CONT) containing data indicating the data length, an ID indicating the content of each subsequent data (DATA), and a data area having a length (variable length) indicated by CONT, for example, 8 for each. DATA1 to D for each bit
ATA4, CRC of error check code, EOD (End Of Data) indicating end of data, and reception confirmation signal (hereinafter referred to as "ACK signal") corresponding to bits from all nodes.
Say. 24 bit AC for sending back)
A 1-bit A indicating that the K signal area and ACK signals have been returned from all registered nodes and data transmission has ended
CK fixed bit area and EOF indicating the end of frame
(End Of Frame).

As such a node, two types of configurations shown in FIGS. 3 and 5 below can be considered. Referring to FIG. 3, the node 10 of the first embodiment realizes a data input / output control function by hardware and does not require a micro computer. This node 1
0 is a bus interface circuit 11 and a communication control circuit 1
2, an input circuit 13, an input port 14, an output circuit 15, an output port 16, a port control unit 17, a transmission buffer memory (hereinafter, referred to as "transmission buffer") 18 for storing transmission data, a reception for storing received data Buffer 1
It is composed of 9 and 9.

The input circuit 13 takes in an input signal from a load such as various switches SW as a parallel signal and outputs the parallel signal to the input port 14. The port control unit 17 monitors the value indicated by various input signals input to the input port 14, and sends a value of this input signal to the communication control circuit 12 when a part or all of this value changes. The communication control circuit 12 stores the value of the input signal as input data in the transmission buffer 18, generates a frame based on the data, and transmits the frame to the bus MB via the bus interface circuit 11. Note that here, input port 1
4 is 1 of input port A and input port B of 8 bits each
It has a 6-bit configuration.

In the concrete transmission frame thus generated, as shown in FIG. 4A, each bit of the input port 14 is made to correspond one-to-one with each bit of the data area of the transmission frame. . That is, in this example, bits 7 to 0 of the input port A are bits 7 to 7 of DATA3.
0, each of bits 7 to 0 of input port B is DAT
It corresponds to bits 7 to 0 of A4, respectively.

The communication control circuit 12 also receives a signal on the bus MB via the bus interface circuit 11. Then, by detecting the start bit, it is recognized that the received frame is transmitted to the transmission path, and this data is temporarily stored in the reception buffer 19. Upon recognizing the received frame, the communication control circuit 12 causes the CONT and ID
Determines whether the received frame is necessary for the node itself. Here, if this reception frame is necessary for the own node and reception is completed without error, the data fetched in the reception buffer 19 is transferred to the port control circuit 1.
Send to 7.

The port control circuit 17 outputs this data to the corresponding output port 16 and outputs it to a desired load such as the motor M or the lamp R via the output circuit 15 to drive this load. Here, the output port 16 has a 16-bit configuration of the output port A and the output port B each having 8 bits. In the specific received frame thus received, as shown in FIG. 4B, each bit of the output port 16 is made to correspond one-to-one with each bit of the data area of the received frame. That is, in this example,
Bits 7 to 0 of the output port A correspond to bits 7 to 0 of DATA3, and bits 7 to 0 of the output port B correspond to bits 7 to 0 of DATA4.

The communication control circuit 12 detects a failure of the bus MB, a collision of signals on the bus MB, and the like, and performs appropriate control.
As a result, the node 10 is configured so that unexpected data will not be written to the reception buffer 19 and unexpected data will not be output to the output port 12 via the port control circuit 13. Has been done.
Further, specific data is repeatedly transmitted from at least one other node (transmission side node) connected to the bus MB at a predetermined fixed time interval. When the communication control circuit 12 receives and correctly interprets this specific data correctly transmitted on the bus MB, this specific data is output to the output port 16 via the reception buffer 19 and the port control circuit 17. It

In this embodiment, for example, the most significant bit (MS) of DATA3 (specific data) shown in FIG.
B), that is, the 7th bit data consists of data in which "1" and "0" are repeated at 100 ms intervals, and the 7th bit of the output port A corresponding to this data is 10
The pattern of high level “H” and low level “L” is repeated at 0 ms intervals.

In this case, the port control circuit 17 controls the following ports. That is, the port control circuit 1
Reference numeral 7 monitors the specific data stored in the reception buffer 19, and if the specific data forms a predetermined pattern (for example, a repeating pattern of "1" and "0"), the reception buffer 19 Output data contents of port 1
Output to 6 as is. In addition, the port control circuit 17
When this specific data does not form a predetermined pattern, a part or all of the output port 16 is immediately changed to a predetermined state. Here, it is desirable that the port control circuit 17 sets this predetermined state so that the load connected to the output port 16 is safely fixed.

Therefore, in this embodiment, since the port control circuit monitors the MSB of DATA3 which is repeated at a predetermined interval, the communication control circuit fails, the clock generator stops oscillating, and the transmission line is interrupted. When unexpected data is written in the reception buffer due to an abnormal state such as a failure of the device or a collision of signals on the transmission line, and an abnormality occurs in this MSB, it is possible to control the output port to a predetermined state. it can. As a result, in this embodiment, the load is safely fixed and no abnormality occurs in the load.

In this node 10, the communication control circuit 12,
Input port 14, output port 16 and port control circuit 1
7 is an example in which it is composed of one communication IC. Since this node 10 does not have a microcomputer for communication control (hereinafter referred to as "I / O node"), the transmission frame and the reception frame read the value input from the address setting input terminal or the like, Those that can be easily generated are desirable. Specifically, the priority is
The number of terminals is reduced by deciding the physical address etc. and not providing a dedicated priority setting terminal.
The scale of 2 has been reduced.

If the ID of the transmission frame and the ID of the reception frame are the same, the transmission frame of the own node and the transmission frame of another node cannot be distinguished. For this reason, it is possible that the transmission data of its own node is received and the load is driven. Therefore, the logical value of the final bit of the ID is changed, and the ID to be inserted into the frame at the time of transmission and the data to be received. Different IDs are used to determine that.

That is, referring to FIG.
D is 8-bit data, and the 0th bit of ID is
The transmission frame of FIG. 4 (a) is set to logic "0", and the reception frame of FIG. 4 (b) is set to logic "1". Further, in the 4th to 1st bits of the ID, the address values A3, A2, and
A1 and A0 correspond. The 7th to 5th bits of ID are
For example, it is conceivable that all are fixed to logic "1" to distinguish between transmission / reception frames of I / O nodes.

Since the I / O node does not have a microcomputer, it is not a node for performing complicated control of a meter or the like, and does not require control functions such as input of switch on / off data and signal output for lighting a lamp. It is suitable to use as a node dedicated to various input / output. In FIG. 1, the front node 2 and the engine node 4 correspond to this I / O node.

Referring to FIG. 5, the node 20 of the second embodiment includes a bus interface circuit 21, a communication control circuit 22, an input circuit 23, an input port 24, an output circuit 25,
Output port 26, CPU core 27, transmission buffer 28,
It is composed of a reception buffer 29. This node 2
In 0, the communication control circuit 22, the input port 24, the output port 26, and the CPU core 27 are configured by one communication IC.

The CPU core 27 reads the signal of the switch SW via the input port 24 and sends it to the communication control circuit 22 as data. Then, when a transmission start signal is input from the CPU core 27, the communication control circuit 22 sends this data to the bus interface circuit 21 in a frame format. When the communication control circuit 22 receives a frame from the bus interface circuit 21,
The data in the frame is stored in the reception buffer 29, and the CPU core 27 is notified that the frame has been received. Upon receiving this notification, the CPU core 27 takes in the data stored in the reception buffer 29 and stores the CO in the frame.
Based on NT and ID, it is judged whether this frame is necessary for the own node. Here, the CPU core 27
When receiving the frame necessary for its own node without any error, the node controls the load connected to the output circuit 25 according to the received data.

Also in this embodiment, since the port control circuit monitors the MSB of DATA3 which is transmitted by the communication control circuit of the transmission side node and is repeated at a predetermined interval, unexpected data is stored in the reception buffer. When the data is written and an abnormality occurs in this MSB, the output port can be controlled to a predetermined state. A node that controls communication by such a microcomputer (hereinafter referred to as "Ba
sic node ". 20), it is possible to store the ID corresponding to the transmission frame or the reception frame of its own node in the RAM of the microcomputer or the like by providing a dedicated storage area as an initial setting when the node starts. As a result, the Basic node 20 can communicate in a plurality of frames, that is, frames with different IDs, can increase the number of signals to be transmitted and received, and can be used for a node that needs a control function for controlling a plurality of meters or the like. Is suitable.
In FIG. 1, the instrument panel node 1, the cowl node 3 and the door node 5 correspond to this Basic node.

Next, FIG. 6 shows a concrete example of a transmission / reception frame in the multiplex transmission system shown in FIG. In this multiplex transmission system, as described above, the instrument panel node 1, cowl node 3 and door node 5 are the basic nodes having the configuration shown in FIG. 5, and the front node 2 and the engine node 4 are those having the configuration shown in FIG. I / O node.

Although the engine node 4 performs complicated control of the engine and transmission, such control may be performed by a dedicated microcomputer. In that case,
Instead of the input circuit 13 and the output circuit 15 shown in (1), it is possible to configure an I / O node for input / output control by connecting a microcomputer between the load and the communication IC. That is, in this I / O node, the input terminal of the input port 14 is connected to the output port of the microcomputer, and the output port 16 and the vehicle speed sensor S1 are connected to the input port of the microcomputer.

Since this I / O node is composed of a communication control circuit for transmitting a frame in response to a change in the input port, the microcomputer is required to transmit a frame in response to a change in the input signal from the vehicle speed sensor S1. It enables frame transmission by changing its own output port. In this case, since the microcomputer can arbitrarily change the input port value of the input port 14, the data transmission interval can be freely set. This I / O
At the node, the microcomputer calculates the period of the pulse output from the vehicle speed sensor S1, and the value is encoded here as 4-bit data, and the data is output from the output port of the microcomputer and input to the input port 14 of the communication IC. Let me send it.

Referring to FIG. 6, (a) is a frame transmitted from the cowl node 3 to the front node 2 by DATA.
The 6th bit of 3 corresponds to the data of the headlamp switch SW3, and the 5th bit corresponds to the data of the turn signal switch SW4. Since this frame is a reception frame of the front node 2 which is an I / O node, the ID is "11101001" as described with reference to FIG.

FIG. 6 (b) is a frame transmitted from the engine node 4 to the instrument panel node 1, and corresponds to the data of the vehicle speed sensor S1 encoded in 4 bits from the 6th bit to the 3rd bit of DATA3. I am letting you. The signal of the vehicle speed sensor S1 is a signal for driving the meter ME1, and the vehicle speed is a continuous signal, and therefore needs to be frequently transmitted cyclically at intervals of, for example, several 100 ms. Since this frame is a transmission frame of the engine node 4 which is an I / O node, the ID is “1111”.
It becomes 1000 ".

FIG. 6 (c) shows a frame transmitted from the cowl node 3 to the door node 5, and the data of the door lock switch SW5 is associated with the 7th bit of DATA3.
Although this frame is a transmission / reception frame between Basic nodes, the address value of the door node 5, which is the receiving node, is inserted in the ID to be "00011111". Since the frame of this ID is necessary for the node itself in the node 5, the ID is stored in the RAM of the microcomputer in advance.

FIG. 6 (d) is a frame transmitted from the instrument panel node 1 to the door node 5, and the data of the power window switch SW2 is associated with the sixth bit of DATA3. Since the data of the power window switch SW2 is a signal of the door control system like the data of the door lock switch SW5, the ID of this frame is shown in FIG.
Like the frame of (c), it is set to "00011111".

The instrument panel node 1 and the cowl node 3
Transmits a frame with the same ID, therefore, in this frame, DATA1 indicates valid / invalid indicating that data is valid / invalid.
An invalid bit function (hereinafter referred to as "V / I") is introduced. This V / I is DAT for each bit of DATA3.
Each bit of A1 is made to correspond. That is, this V /
For I, D corresponding to the bits required for DATA3 control
The logical value of the bit of ATA1 is set to “0”, and the logical value of the bit of DATA1 corresponding to the bit unrelated to the control of DATA3 is set to “1” to determine which data bit of the frame is for control at the receiving node. It was made possible.

In the frame of FIG. 6 (c), the 7th bit is data necessary for control, but the 6th bit is irrelevant data. Therefore, the 7th bit of DATA1 is set to logic "0". , And the sixth bit is a logic "1". In the frame of FIG. 6D, the sixth bit is data necessary for control, but the seventh bit is irrelevant data. Therefore, the seventh bit of DATA1 is set to logic "1". , The 6th bit is set to logic "0".

If this V / I is not introduced, for example, the instrument panel node 1 sends an ON signal of the power window switch SW2, and the cowl node 3 sends an OFF signal of the door lock switch SW5 while the window is open. It is possible to send it. In this case, cowl node 3
Has no data of the power window switch SW2, the sixth data of DATA3 in the frame of FIG.
The bit data is not always transmitted with the correct value. Nevertheless, the door node 5 performs control based on this transmission frame because the ID of the transmission frame of the cowl node 3 is also the ID indicating the self node which is the receiving node. Therefore, this open window may be closed. Therefore, it becomes necessary to assign different IDs to these signals.

Therefore, if V / I is introduced as in this embodiment, the door lock switch SW is switched from the cowl node 3 to the door lock switch SW.
If the sixth bit of DATA3 is designated invalid when transmitting 5, it is possible to prevent malfunction even when transmitting a frame with the same ID. FIG. 6 (e) is a frame transmitted by the door node 5 to the instrument panel node 1, and the data of the door switch SW1 is associated with the 7th bit of DATA3. This frame is a transmission / reception frame between Basic nodes, but here, by inserting the address value of the instrument panel node 1 which is the receiving node into the ID, “0000000” is inserted.
In the instrument panel node 1, since the frame of this ID is a frame necessary for its own node, this ID is stored in the RAM of the microcomputer in advance.

In the multiplex transmission system of this embodiment, the signal of the headlamp switch SW3 and the signal of the power window switch SW2 can be considered to be particularly important signals. Therefore, in this embodiment, the cowl node transmits the seventh bit of DATA3 in the frame of FIG. 6A at 100 ms intervals by repeating "1" and "0". The front node 2 receiving this frame outputs the output port A corresponding to the 7th bit of DATA3.
Since the data is output to the 7th bit of
The 7th bit of is high level "H" at 100ms intervals
And the low level “L” pattern is repeated.

FIG. 7 is a configuration block diagram showing the configuration of the third embodiment of the node according to the present invention. In FIG. 7, the bus interface circuit 31, the communication control circuit 3
2, input circuit 33, input port 34, output circuit 35, output port 36, port control circuit 37, transmission buffer 3
8. The receiving buffer 39 is the same as the component having the same name shown in FIG.

Referring to FIG. 7, in this embodiment, at least one specific data of the plurality of output data output from the output port 36, for example, the 7th bit of the output port A shown in FIG. The output data corresponding to is output to the watch dog timer (hereinafter, simply referred to as "timer") 40 as a timer reset signal, the timer is reset, and the timer time is returned to the initial value. There is.

As shown in FIG. 8B, the timer 40 is normally used.
Outputs, for example, "H", but the timer 40 changes the output to "L" unless the reset signal is input within the timer time set in advance by a resistor or a capacitor. To reset the timer 40, as shown in FIG. 8 (a), the output data corresponding to the 7th bit of the output port A is taken out, and the output, for example, from "H" to "L".
This is done by entering the falling edge to. That is, the timer 40 is reset every 200 ms.

The timer 40 sets the timer time to, for example, 20.
If preset to 250 ms, which is sufficiently longer than 0 ms, the output of the timer will not change. As a matter of course, the optimum values of the timer time and the transmission interval may differ depending on the system. However, if any of the transmission line, bus interface circuit, communication control circuit, port control circuit, output port, etc. fails and normal communication cannot be performed, normal output cannot be performed to the output port. Will be fixed at "H" or "L". In this case, the reset signal of the timer is not output within 250 ms, so the output of the timer changes from "H" to "L". The output of the timer is input to the port control circuit 37 via the fail-safe input terminal 41 of the communication IC, as shown in FIG.

When the port control circuit 37 detects that the output from the timer 40 has become "L", the port output has a predetermined pattern (here, "0", "1" at predetermined time intervals). It is determined that the "repeating pattern" is not formed, and immediately part or all of the output port 36 is changed to a predetermined state. Here, at least the state of the output port input to the timer 40 is set so as to hold the normal port output. This is an output port that inputs to the timer (in this case, when it is possible to communicate after a short time when normal communication is temporarily stopped due to the influence of external noise etc.).
If the 7th bit of output port A) is also changed to a predetermined state, the reset signal will not be input to the timer even when communication is restored, so this node will be disabled and the vehicle performance will be degraded. It depends on the reason why it is left.

Here, it is desirable that the port control circuit 37 sets this predetermined state so that the load connected to the output port 36 can be safely fixed. In the front node 2, it is considered safe to turn on the headlamp R1.
It is desirable that the bit bit is fixed to ON. In addition,
The setting of the predetermined state may be, for example, setting the “H” state or the “L” state for each output port,
Also, some or all of the output ports may be set to a high impedance state. However, when setting this output port to the high impedance state, it is necessary to pull up or pull down the required output port according to the load state. Since it can be set with, the degree of freedom increases.

The output port 36 thus set in the predetermined state holds the data input from the port control circuit 37 in the latch circuit 41 and outputs this data to a plurality of outputs, as shown in FIG. 9, for example. It is considered that the data is output via the buffer 42. When setting the state of the output port 36 to the high impedance (floating) state, it is conceivable that the output buffer 42 is configured by a 3-state buffer connected to the port control circuit 37 (see FIG. 9). However, the output buffer 42p, unlike the other output buffers 42, sends its output to the timer 40 as well.

Then, the port control circuit 37 uses the timer 4
When it detects that the output from 0 has changed to the “L” state,
By controlling the operation of the output port 36, the output value of the output buffer 42 can be brought into a floating state. Further, since the port control circuit 37 does not control the operation of the output buffer 42p in the floating state, the output value of the output buffer 42p is output in the level state in which the data from the port control circuit 37 is fetched. Become.

Therefore, in this embodiment, when an abnormality occurs in the 7th bit data of the output port A input to the timer, the port control circuit can control the output port to a predetermined state. it can. The data to be monitored is not limited to the data shown in this embodiment,
For example, when there is data that constantly changes the output port (data of speedometer, blinker, etc.), it is possible to use the changed portion of the data.

As another embodiment of the output port 36, as shown in FIG.
A configuration in which the output of the timer 40 is directly input to the output port 36 by connecting to 0 is also considered. When the output of the timer 40 changes to the "L" state, the output value of the output port 36 can be set to the floating state.

Therefore, in this embodiment, when an abnormality occurs in the 7th bit data of the output port A input to the timer, the timer can control the output port to a predetermined state. Next, the reception buffer, the port control circuit, and the output port will be described in detail based on an example of the partial configuration diagram of FIG.

Referring to FIG. 11, the reception buffer 39 for storing the data input from the communication control circuit may be, for example, a shift register for sequentially storing the data serially. The shift registers 39a to 39p send the stored data to the port control circuit 37 in parallel bit by bit. The shift registers 39a to 39p
Is composed of the number of bits corresponding to the number of output ports, and here, for example, a 16-bit structure is used.

The port control circuit 37 loads the input data according to the output logic of the timer 40 into the output port 36. The output port 36 uses this shift register 39
a-39p corresponding to latch circuits 41a-41p and output buffers 42a-42p for fetching the data from the latch circuits 41a-41p. The data fetched from the port control circuit 37 is output to the load. ing. Further, in this embodiment, the output port for outputting data to the timer 40 is the 7th bit of the output port A which is a port corresponding to the 16th bit shift register 39p which is the final stage. The reason for setting in this way is not only when the control of data communication is abnormal, but also when the shift register fails, the timer 40 is not reset and its output can be changed to the “L” state. Because.

When such a node receives a frame, the data of the frame is sequentially shifted from the first bit shift register 39a. And
If the third-bit shift register 39c fails and the output data is stuck in the "H" state, all the output data from the third to 16th-bit shift registers 39c to 39p become the "H" state. , The output port corresponding to the 16th bit shift register 39p remains in the "H" state. Therefore, the timer 40 is not reset, and the output of the timer changes to the "L" state.

That is, for example, when the output data from the shift register of the third bit is monitored here,
Although only the failures of the first to third bits can be detected, if the bit monitored by the timer 40 is the last bit of the shift register as in this embodiment, the failure of all the bits of the shift register can be detected. Further, in this embodiment, when the abnormality is recovered and the data transmission between the nodes is normally performed, the output data of the state a of the output port A becomes "L" at this predetermined interval. The state of "H" is repeated. Then, the timer 40 is reset at the trailing edge of the output data, and the output of the timer 40 becomes the "H" state again. As a result, the operation of the port control circuit 37 returns to the normal state, and the data transmitted on the bus MB is output from the output port 36 to the load.

Therefore, in this embodiment, the watchdog timer detects the output port that outputs the data that is repeated at the predetermined interval, and notifies the port control circuit of the output port. If unexpected data is written to the receive buffer due to an abnormal condition such as oscillation stoppage of the generator, and this output becomes abnormal, this port control circuit should control the output port to a predetermined state. You can This allows
In this embodiment, the load is safely fixed and the load does not become abnormal.

In addition to the above-described embodiment, if it is desired to selectively perform the abnormality detection operation, it is possible to provide, for example, a watch dog timer with an enable input indicating the necessity of detection. Further, the communication control circuit and the port control circuit shown in this embodiment may each be composed of a logic circuit or may be controlled by a computer. Furthermore, the send buffer and the receive buffer are
It may be a part of a communication control circuit including an LSI or the like.

Further, in the embodiment of the frame of FIG. 6 (a),
Originally, frames that do not need to be cyclically transmitted are transmitted at 100 ms intervals, which causes congestion of the transmission path. So, like the frame in Figure 6 (b),
If the frame that is cyclically transmitted exists in the multiplex transmission system, the signal can be used to carry out the transmission line without congesting the original system.

That is, the engine node 4 transmits the frame of FIG. 6 (b) at 100 ms intervals while repeating "1" and "0" for the seventh bit of DATA3 not assigned to the transmission data. The engine node 4 is I
Although it is an / O node, the data connecting the output port of the microcomputer to the input port can be freely changed. This frame is originally intended for the instrument panel node, but the door node to which the power window motor is connected is Basi
Since it is the c node, the door node can store the ID in the RAM of the microcomputer in advance so as to receive this frame. Also, by programming with a microcomputer, when this frame is received,
It is also possible to set only the 7th bit of DATA3 to be valid.

Further, the door node drives the motor by monitoring the output port corresponding to the 7th bit of DATA3 and opening the output port in a predetermined state when there is no change, for example, opening the power window. can do. At the Basic node, changes in output ports can be monitored by a microcomputer, so there is no need to install a new timer.

Further, as in this embodiment, the frame for driving the load connected to the output port is not monitored in order to bring the output port into a predetermined state. In the present invention, communication is performed. If it is determined that the frame cannot be normally processed, it is not necessary to set a limiting condition on the frame to be monitored. Further, in this embodiment, although not shown, if there is data that is cyclically transmitted by repeating "1" and "0" with the original control data, the bit of the control data can be monitored. For example, it is possible to monitor the abnormal state of data without changing the congestion degree of the transmission line or the load of the microcomputer in each node.

In the above embodiments, one node transmits a frame in which "1" and "0" are repeated in a part of the data area, but the present invention is not limited to this, and two frames are used. It is also possible. For example, in FIG.
In the case of a frame received by a door node like the frame of (d), in the frame of FIG.
The fifth bit of is fixed to "1" for transmission, and in the frame of FIG. 6 (d), the fifth bit of DATA3 is fixed to "0" for transmission. In this case, when the timer time of the timer is set to 250 ms as in the above-described embodiment,
Both frames (c) and (d) may be transmitted at cyclic intervals of 200 ms.

Therefore, in this case, although the congestion degree of the transmission line does not change, the load on the microcomputer per node can be reduced, which is effective when the original microcomputer load on each node is heavy. In particular, it is more effective if the frames of FIGS. 6 (c) and 6 (d) are cyclically transmitted frames in the original multiplex transmission system of an automobile.

Further, in the node shown in this embodiment, the input port, the output port, the communication control circuit, the port control circuit or the CPU core is constituted by one IC, but the present invention is not limited to this. Not limited to this, the same effect can be obtained even if these constituent parts are configured by different ICs.

[0068]

As described above, according to the present invention, in the multiplex transmission method for performing frame-structured data transmission between multiplex transmission devices mutually connected via a transmission line, the multiplex transmission device on the transmission side is provided. Among the data in each frame to be transmitted, at least a part of the predetermined data is set so as to make a predetermined change, the frames are sequentially transmitted, and the multiplex transmission device on the receiving side is Each frame transmitted from the transmitting side multiplex transmission device is sequentially received, the data in each frame is output from the output port to the controlled load, and the predetermined data in each frame is monitored to Controlling the output port to a predetermined state when at least part of the data does not undergo a predetermined change corresponding to the predetermined data in the previously received frame. Since, it is possible to increase the oscillation stop, and safety devices to detect an abnormal condition such as a collision of a signal failure or transmission line of a transmission line failure or the clock generator communication control circuit. Especially if you monitor the output of the output port,
Since it is possible to monitor all operations from the signal reception from the transmission path to the output of the output port, the reliability can be further improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a multiplex transmission system using a multiplex transmission method according to the present invention.

FIG. 2 is a diagram showing an example of a format of a data frame transmitted between the nodes shown in FIG.

FIG. 3 is a configuration block diagram showing a configuration of a first embodiment of a node according to the present invention.

FIG. 4 is a diagram showing a specific example of the data frame shown in FIG.

FIG. 5 is a configuration block diagram showing a configuration of a second exemplary embodiment of a node according to the present invention.

6 is a diagram showing a part of each data frame transmitted / received between the nodes shown in FIG. 1. FIG.

FIG. 7 is a configuration block diagram showing a configuration of a third exemplary embodiment of a node according to the present invention.

FIG. 8 is a waveform chart showing an example of temporal changes in specific data and a watch dog timer output.

9 is a partial configuration diagram showing an example of the output port, port control circuit, and watch dog timer of FIG. 7. FIG.

10 is a partial configuration diagram showing another example of the output port, the port control circuit, and the watch dog timer of FIG.

11 is a partial configuration diagram showing an example of a reception buffer, a port control circuit, and an output port of FIG. 7. FIG.

[Explanation of symbols]

 11,21,31 Bus interface circuit 12,22,32 Communication control circuit 13,23,33 Input circuit 14,24,34 Input port 15,25,35 Output circuit 16,26,36 Output port 17,37 Port control circuit 18, 28, 38 Transmission buffer memory 19, 29, 39 Reception buffer memory 27 CPU core 40 Watch dog timer MB Transmission path (bus)

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Hideki Kimura 2-6-1, Marunouchi, Chiyoda-ku, Tokyo Furukawa Electric Co., Ltd. (72) Inventor Hiroaki Sakamoto 3-3 Shinchi, Fuchu-cho, Aki-gun, Hiroshima Prefecture Mazda Co., Ltd. (72) Inventor Yoshikazu Nobutoki 3-1, Shinchi, Fuchu-cho, Aki-gun, Hiroshima Mazda Co., Ltd.

Claims (11)

[Claims] 1. A multiplex transmission method for performing frame-structured data transmission between multiplex transmission devices connected to each other via a transmission line, wherein the multiplex transmission device on the transmission side is configured to transmit data in each frame to be transmitted. Among them, at least a part of predetermined data is set so as to change in a predetermined manner, and each of the frames is sequentially transmitted, and the multiplex transmission device on the reception side is transmitted from the multiplex transmission device on the transmission side. Each of the frames is sequentially received, the data in each of the frames is output from the output port to the controlled load, and the predetermined data in each of the frames is monitored. A multiplex transmission method characterized in that the output port is controlled to a predetermined state when a predetermined change corresponding to predetermined data in a received frame does not occur. 2. Multiplexing, which is connected to a transmission line, has a communication control means for sequentially receiving data from the transmission line, and sequentially outputs at least a part of each received data from an output port to a controlled load. In a transmission device, a reception storage unit that stores the sequentially received data, and at least a part of each data sent from the reception storage unit to the output port is monitored, and at least one of the monitored data items is monitored. Multiplex transmission, characterized in that the unit has a port control means for controlling the output port to a predetermined state when the unit does not make a predetermined change corresponding to the previously received data. apparatus. 3. Multiplexing, which is connected to a transmission line, has communication control means for sequentially receiving data from the transmission line, and sequentially outputs at least a part of each received data from an output port to a controlled load. In a transmission device, a reception storage unit that stores the sequentially received data, and at least a part of the data output from the output port is monitored, and at least a part of each monitored data is A multiplex transmission device, comprising: port control means for controlling the output port to a predetermined state when the predetermined change is not made in correspondence with the received data. 4. The multiplex transmission device according to claim 2, wherein the port control means does not control at least an output port of the output ports where data monitoring is performed to a predetermined state. 5. The reception storage means stores serially the data received from the transmission line, and the port control means monitors the data corresponding to the last bit stored in the reception storage means. Claims 2 and 3 characterized
Alternatively, the multiplex transmission device according to item 4. 6. A multiplex transmission apparatus connected to a transmission line, comprising communication control means for sequentially receiving data from the transmission line, and sequentially outputting at least a part of each data from an output port to a controlled load. A receiving and storing means for storing the sequentially received data, and sequentially receiving at least a part of the data transmitted from the receiving and storing means to the output port, and corresponding to a part of the previously fetched data And a change detecting means for detecting a change of the partial data, and a port control means for controlling the output port to a predetermined state according to the detection result. . 7. A multiplex transmission device, which is connected to a transmission line, has communication control means for sequentially receiving data from the transmission line, and which sequentially outputs at least a part of each data from an output port to a controlled load. A receiving / storing means for storing the sequentially received data, and sequentially capturing at least part of the data output from the output port, and corresponding to the partially captured data before the part. 2. A multiplex transmission apparatus comprising: a change detection unit that detects a change in the data of 1. and a port control unit that controls the output port to a predetermined state according to the detection result. 8. The reception storage means serially sequentially stores the data received from the transmission path, and the change detection means fetches the data corresponding to the last bit stored in the reception storage means. Claim 6 or 7
The described multiplex transmission device. 9. The port control means does not control at least an output port of the output ports, in which at least the change detection means detects a data change, to a predetermined state. 7. The multiplex transmission device according to 7 or 8. 10. The multiplex transmission device according to claim 2, wherein the port control means controls the output port to a predetermined high impedance state. 11. The port control means controls the output port to a predetermined state so that the controlled load can be safely fixed.
The multiplex transmission device according to any one of claims 9 and 10.