JPH07153676A - Designing method and direct drawing apparatus of circuit pattern for semiconductor device - Google Patents

Abstract

PURPOSE:To provide the designing method and the direct drawing apparatus, of a circuit pattern for a semiconductor device, which correct a part causing the production of a false defect contained in the circuit pattern because the circuit pattern containing the false defect lowers the yield of a mask formation process and increases the operating time. CONSTITUTION:In a designing method which includes a semiconductor-circuit- pattern generation process which generates a semiconductor-circuit pattern to be drawn by a drawing means, a generated circuit pattern is provided with an oblique pattern part having an oblique outer-shape part with reference to the drawing direction of the drawing means and with rectangular pattern parts coming into contact with the oblique pattern part. When the oblique pattern part is a definite size or lower, it is identified. The oblique pattern part is converted so as to be replaced by rectangular patterns 9 which have expanded the rectangular pattern parts.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a circuit pattern of a semiconductor device which can be used in the field of manufacturing semiconductor devices such as semiconductor integrated circuits. Further, the present invention relates to a direct drawing device that can be used when manufacturing a semiconductor device. INDUSTRIAL APPLICABILITY The present invention can be used, for example, as a semiconductor integrated circuit pattern generation method (photomask pattern, wafer direct writing pattern generation method) used in a semiconductor device manufacturing process, and a direct writing apparatus for these generated circuit patterns.

[0002]

2. Description of the Related Art In the field of semiconductor devices, further miniaturization and
Integration is progressing. For example, in the field of semiconductor integrated circuits, submicron level processing has already been realized in mass production plants, and quarter level processing is required at the research level.

In the semiconductor integrated circuit pattern design, a pattern obtained by reducing the size of a part of a conventional pattern is used, a new pattern shape is created, or a pattern is automatically created by an automatic placement line program. .

These pattern data are usually created in CAD format. For example, Calma's GD
It is created in an industry standard CAD format called SIISTREAM format. These CA
The D data is subjected to processing such as logical operation and sizing, then becomes an actual semiconductor integrated circuit pattern, and subsequently converted into the format of the electron beam drawing apparatus.

Next, a circuit pattern is drawn on the photomask substrate by an electron beam drawing apparatus, and the photomask is completed through development, post-baking, etching, resist peeling, inspection, correction and shipping cleaning.

[0006]

In electron beam lithography, when the patterns are close to each other due to the phenomenon of proximity effect due to scattering of electron beams, the patterns are connected to each other, or in the case of an isolated minute pattern, the pattern is connected. Is known to be smaller than the design size. Various means have already been proposed to solve these proximity effect phenomena.

However, if the pattern circuit includes a portion smaller than the resolution of the drawing device, it cannot be corrected even by the proximity effect correction processing. Therefore, in such a portion, the shape of the pattern actually formed and the shape of the pattern actually formed are slightly different from each other, and are regarded as defects in the inspection process.
However, this defect is not a fatal defect that causes wire breakage or the like and does not cause any problem in circuit operation. Therefore, it is generally called a pseudo defect.

Generally, for example, a variable shaping type electron beam drawing apparatus does not have an aperture for shaping an arbitrary oblique line, so that the oblique line is usually divided into rectangles for drawing (see FIG. 4). (Detailed below). For this reason, since division is not properly performed on a minute diagonal line, the minimum size specification of the diagonal line of the drawing apparatus is larger than that of the rectangular pattern drawing. Therefore, more pseudo defects occur in the minute diagonal line portion than in the rectangular pattern.

When circuit patterns containing these pseudo defects are repeatedly arranged like a memory circuit, many pseudo defects are picked up, resulting in a significant increase in defect confirmation work time. Alternatively, if the defect inspection apparatus exceeds the number of stored defects, the inspection becomes impossible and it is necessary to change the parameters of the inspection apparatus and perform the defect inspection again. Even if the parameters of the inspection machine are reset, if the inspection is impossible, the mask becomes defective, and it may be necessary to start over from the design change of the circuit pattern.

The pseudo defect will be further described below. First, a process of generating a pseudo defect will be described. The cause of the pseudo defect is caused by the use of a device having a poor drawing accuracy of the diagonal line pattern and the curling of the diagonal line pattern at the connection of the rectangular diagonal lines.

First, a case where a pseudo defect occurs due to a poor drawing accuracy of a diagonal line pattern will be described with reference to FIG. For example, in the case of a variable shaping type electron beam drawing apparatus, a shaping aperture that corresponds to an arbitrary oblique line is not provided, and rectangular shaping is performed to a height of 0.5 μm as shown in the principle diagram of FIG. The trapezoidal pattern 14 is drawn by shifting the electron beam 15 by 0.05 μm and drawing it while superimposing it on the irradiation amount of 1 / n.

However, when there is no other pattern around, the total amount of exposure does not reach n at the upper and lower parts of the pattern, and the amount of exposure becomes insufficient. Furthermore, since the upper and lower portions are exposed by 0.25 μm each, the contact portion with the rectangular pattern is overexposed when the rectangular pattern is in contact.

FIG. 5 (d) shows a shape in which the pattern is actually distorted when the rectangular pattern and the diagonal line contact each other. In such a case, since the rectangular and trapezoidal contact portions 22 in FIG. 5D are formed (solid line) beyond the designed pattern (broken line), they are detected as defects. If the amount of protrusion is small, there is no problem in circuit operation, so it is regarded as a pseudo defect.

Next, the generation of pseudo defects due to the rounding of the ends of the diagonal lines will be described. In electron beam lithography, it is known that a proximity effect phenomenon occurs due to electron beam scattering. The proximity effect phenomenon can be corrected by changing the irradiation amount of the electron beam for each pattern, and it is already in practical use. However, in this case, the midpoint of the pattern is as designed, but the corner portion of the pattern is rounded due to the internal proximity effect.

For example, when the pattern 11 shown in FIG. 3A is drawn, the corner portion of the pattern 11 is rounded like the pattern 12 shown in FIG. 3B due to the internal proximity effect. . In the defect inspection apparatus, an algorithm is set so that even if the corners of the rectangular pattern in FIG. 3B are rounded and become the shape indicated by reference numeral 13, the algorithm is not detected as a pseudo defect, and the rounding amount is set as a parameter. You can do it.

Therefore, even if the corners of the rectangular pattern are rounded, they are not detected as pseudo defects. On the other hand, with respect to the end portion of the diagonal line, the rounding amount and the like differ depending on the pattern and cannot be obtained without complicated calculation. Therefore, there is no function for setting the rounding amount of the end portion of the diagonal line. For this reason, in the portion where the rectangle and the diagonal line are combined, the rounded portion of the diagonal line portion is detected as a defect when the detection sensitivity of the defect inspection apparatus is increased because it corresponds to, for example, quarter micron.

The circuit pattern including such a pseudo defect causes a decrease in yield and an increase in working time in the photomask making process. Therefore, there is a demand for a circuit pattern design method that does not generate pseudo defects. Therefore, an object of the present invention is to provide a circuit pattern designing method for a semiconductor device and a direct writing apparatus for correcting a portion included in an integrated circuit pattern which causes a pseudo defect.

[0018]

The invention according to claim 1 of the present application is a circuit pattern design method for a semiconductor device, which includes a semiconductor circuit pattern generation step of generating a semiconductor circuit pattern to be pattern-drawn by a drawing means. The circuit pattern has an oblique pattern part having an outer shape part oblique to the drawing direction of the drawing means, and a rectangular pattern part in contact with the oblique pattern part, and the oblique pattern part has a certain size or less. In this case, a method for designing a circuit pattern of a semiconductor device, characterized in that the conversion is performed by identifying this and replacing the diagonal pattern portion with a rectangular pattern obtained by enlarging the rectangular pattern portion,
This achieves the above object.

According to a second aspect of the present application, in a circuit pattern designing method for a semiconductor device, which includes a semiconductor circuit pattern generation step of generating a semiconductor circuit pattern to be pattern-drawn by a drawing means, the generated circuit pattern is the drawing. A conversion is provided which includes an oblique pattern portion having an outer shape portion oblique to the drawing direction of the means, and when the oblique pattern portion has a certain size or less, identifies it and deletes the oblique pattern portion. A method for designing a circuit pattern of a semiconductor device, characterized in that the above-mentioned object is achieved.

According to the invention of claim 3 of the present application, the step of reading the pattern data, the step of extracting a minute pattern which is a pattern having a rectangular pattern and an oblique outer shape in the pattern data, and the extracted pattern are
A pattern having an oblique outer shape is converted or replaced with one or more rectangular patterns according to the size of the pattern or is deleted, and the rectangular pattern is directly or deleted depending on the size of the pattern or whether it is a slit or not. The method for designing a circuit pattern of a semiconductor device according to claim 1 or 2, further comprising the step of performing a conversion to achieve the above object.

According to a fourth aspect of the present invention, in a direct drawing apparatus that creates a semiconductor circuit pattern and draws the created circuit pattern by a drawing means, the created circuit pattern is in a drawing direction of the drawing means. On the other hand, when a pattern portion having an oblique outer shape portion is provided and the pattern portion is smaller than a certain size, this is identified, and the pattern portion having the oblique outer portion is converted into one or more rectangular patterns. A direct drawing apparatus characterized by performing conversion for replacement or deletion, and performing pattern drawing according to the converted pattern, thereby achieving the above object.

According to the invention of claim 5 of the present application, the size of the outer shape portion which is oblique with respect to the drawing direction is identified, and when this size is larger than a predetermined value, it is replaced with the one or more rectangular patterns. The direct drawing apparatus according to claim 4, wherein the conversion is performed, and the conversion is performed when the value is smaller than the specified value.

[0023]

The cause of the pseudo defects as described above is that the process in the photomask making process is not well known at the design stage, and that the pattern rule checker does not include the item regarding the occurrence of the pseudo defects in the photomask. It can be mentioned.

However, it is practically difficult to take all the process conditions of the photomask making process into consideration at the design stage, and even if the designer adds a pseudo defect generation item to the pattern rule checker, the photo If the user is not familiar with the mask making process, the process of checking with the pattern rule checker and redesigning must be repeated several times.

On the other hand, according to the present invention, in the pattern generation technique of the photomask, by adopting the above-mentioned constitution, the portion where the pseudo defect occurs is extracted, and the pattern is automatically corrected or deleted. .

According to the present invention, it is possible to extract a minute pattern which may be a pseudo defect from a semiconductor integrated circuit pattern generated by a conventional pattern generation method, and to automatically replace it with a pattern shape suitable for the process capability. Becomes

For example, the use of the present invention makes it possible to reduce the occurrence of pseudo defects in the inspection process for producing a photomask, improve the yield in producing a photomask, reduce the cost, and significantly improve the rusupout. it can. Further, by using the pattern designing method of the present invention, the total number of patterns can be reduced, so that the capital investment of the data processing system (computer) can be suppressed. In addition, it is possible to reduce the data transfer time over the network.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings. However, as a matter of course, the present invention is not limited to the following examples.

Example 1 FIG. 2 shows an example of a pattern in which a pseudo defect is generated (the same applies to other minute patterns). In FIG. 2, undersizing (reduction) is performed on the basis of a pattern group 1 (FIG. 2A) including two rectangles 3 and 4 and one triangle 2, and two newly reduced rectangles 7 are formed. , 8 and one triangle 6 are shown as an example of creating a pattern group 5 (FIG. 2B).

Since the pattern group 1 of FIG. 2A has a large design rule, the inspection sensitivity can be reduced and the drawing accuracy of the diagonal line portion (triangle) 2 has a margin, so that no pseudo defect occurs. However, in the pattern group 5 newly created by reducing the pattern group 1, the diagonal line portion (triangle) 6 exceeds the specifications of the diagonal line drawing of the drawing apparatus.
Even if the proximity effect correction is performed, the shape of the pattern 6 is distorted. For example, distortions indicated by reference numerals 6a and 6b occur. Therefore, it is detected as a defect. Even if the pattern 6 is slightly distorted, there is no problem in the circuit operation of the pattern formed on the wafer using this mask, but the mask defect inspection result device detects it as a mask defect.
In order to avoid this, conventionally, a visual defect confirmation work by a person is performed and it is regarded as a pseudo defect, and a true defect (6c, 6
It was necessary to distinguish it from the defect shown by d).

In the present invention, the pattern group 5 shown in FIG.
Is converted into a rectangular pattern group 9 as shown in FIG. In the pattern group 9, there are no minute patterns (as a result of making the rectangle rectangular, in particular, minute diagonal line patterns disappear), and the number of patterns is also reduced. Even if such conversion is performed, the pattern obtained by exposure is obtained as a desired pattern as shown by reference numeral 10 in FIG. 1B (described later).

The structure of the photomask substrate used will be described with reference to FIG. Reference numeral 23 in FIG. 10 is a synthetic quartz substrate, on which a light shielding film 24 (formed of a chromium film and a chromium oxide film) is sputtered with a thickness of 0.105 μm, and a resist 25 such as a photosensitizer 25, for example, is further formed thereon. A positive resist for electron beam EBR-9 (manufactured by Toray Industries, Inc.) is spin-coated with a thickness of 0.5 μm, for example.

Using the photomask substrate shown in FIG. 10, the pattern shown in this embodiment (FIG. 1A) is drawn by an electron beam drawing apparatus (acceleration voltage 20 keV) manufactured by JEOL Ltd. It was The electron beam dose at this time is 3.0 μC /
It was cm ² .

After drawing, development was carried out for 2 minutes by spray development using a dedicated developing solution, followed by rinsing with the dedicated developing solution, and then sequentially on a hot plate 70 ° C. → 140 ° C. →
Baking was performed at a temperature of 140 ° C. → 70 ° C. → 23 ° C. in steps of 2 minutes each. After that, the light shielding film 24 was etched, and then the resist 25 was peeled off. As a result,
The pattern of (b) was formed.

That is, in the obtained pattern, the rounding of the pattern occurs due to the influence of the internal proximity effect.
The pattern 10 is completed as shown by the solid line in FIG. This shape is almost the same as the pattern group 5 of FIG. 2B at the design stage (the error is 0.05 μm or less with respect to the design dimension, and 0.01 μm or less on the wafer as the exposed material). , There is no problem in circuit operation. Further, as described above, in the defect inspection apparatus, since the algorithm is set so as not to detect the pseudo defect even if the corners of the rectangular pattern are rounded, there is no problem of detecting the pseudo defect. Further, although a positive type electron beam resist is used in this embodiment, the same result can be obtained by using a negative type resist.

Further, the proximity effect correction by individually changing the irradiation amount of the electron beam given to the pattern cannot correct the rounding of the corner portion of the above rectangular pattern. Therefore, the pattern generated by the present invention is
Since it can be used preferably in combination with proximity effect correction, it is highly practical.

In the drawing apparatus in which the drawing accuracy of the oblique line is solved, pseudo defects do not occur in terms of drawing accuracy, but the advantage of using the present invention in reducing the number of patterns is great. That is, in the case of FIG. 2, it is necessary to draw three patterns, but in the case of FIG. 1 using the present invention, two patterns are sufficient. Even in a drawing apparatus with improved drawing accuracy, diagonal lines are drawn using a plurality of rectangles. Therefore, by using the present invention, the number of patterns can be reduced and the drawing time can be remarkably improved. .

Embodiment 2 FIG. 5A shows an example in which a contact hole pattern 17 is newly designed. Since this pattern 17 is close to the pattern 16 existing in another layer, the pattern rule checker checks that the originally rectangular patterns are close to each other, and based on this, Some of the corners of the design rectangle are cut off as indicated by reference numeral 18, and the pattern 17 is formed.

FIG. 5B is an enlarged view of the cut-out portion of the pattern 17. As shown in this figure,
A minute pattern 19 is generated. When such a pattern is drawn, the pattern 19 portion becomes a pseudo defect due to the problem of the accuracy of drawing the oblique line of the drawing apparatus or because the corner rounding of the oblique line cannot be handled by the defect inspection apparatus. Also, the number of patterns is increased from 1 to 3.

On the other hand, in this embodiment, as shown in FIG.
When the contact hole pattern of (a) is designed to have a photomask size of 2 μm, a part of the corner of the pattern is cut off as described above, and a minute pattern of 0.25 μm in triangle height is formed. In the case of being included in the design pattern, the following measures were taken.
That is, since this minute dimension is not much different from the corner rounding due to the inner proximity, it is replaced with one contact hole pattern in this embodiment. That is, the code 1
The original contact hole pattern itself is used without cutting as shown in FIG. In this way
A photomask substrate similar to that of the first embodiment is used to draw the pattern of the present embodiment and the designed pattern of FIG. 5A, and a photomask is formed by the photomask forming process described in the first embodiment. did. In the pattern according to this example, the distance from the pattern 16 was secured by the corner rounding, and no pseudo defect was generated.
However, in the pattern of FIG. 5A, the minute triangular portion is detected as a pseudo defect.

In this embodiment, in consideration of the rounding amount of the pattern described above, the distance between the pattern 17 and the pattern 16 can be covered by the rounding amount. Therefore, the simple rectangular pattern is replaced, but the rounding amount is changed. If it cannot be covered by the above, it is replaced with two rectangular patterns as shown by reference numeral 18 'in FIG. 5C, or two or more rectangular patterns. In this embodiment, the check is not performed as described above.

Embodiment 3 FIGS. 6 and 7 show an example in which the pattern shape of an actual device circuit pattern is changed by using the present invention. FIG. 7 shows a comparison case, in which the designed original pattern is converted into a shape for an electron beam writing apparatus. FIG. 6 is FIG.
Shows an example in which the pattern is replaced by using the present invention (the other patterns can be replaced in the same manner,
There is no problem). In the circuit pattern of FIG. 6, it can be seen that the pattern is simple and the number of patterns is reduced as compared with the original design pattern of FIG. 7.

Here, the photomask substrate (quartz / chromium / resist) was subjected to an electron beam drawing apparatus manufactured by JEOL Ltd. in exactly the same manner as in the photomask forming step shown in Example 1, and as shown in FIG. Drawing was performed by repeatedly arranging the pattern of FIG. After that, a development process, post-baking, etching, resist stripping, and cleaning were performed, and then a 0.5 μm defect inspection was performed using an inspection device of KLA. As a result, FIG.
A lot of pseudo defects occurred in the micro pattern part of
Pseudo defects did not occur in the region in which FIG. 6 according to the present example is arranged.

Here, when embodying the present embodiment, the current corner rounding amount of the rectangular pattern will be described with reference to FIG. A simulation was performed to find out what the shape would be when the widths of S and L of the stepwise pattern as shown in FIG. 8 were changed. As a result, the simulation result as shown in FIG. 9 was obtained. It has been found that S is optimally 0.5 μm (5 times the size of the photomask). It was also confirmed that these were actually drawn to form a photomask, and that S was 0.5 μm and no pseudo defects occurred.

This value is 0.25μ for the defect inspection device.
It can be easily understood from the fact that the defect is judged in the size of a unit (0.5 * 0.5 μm) in which four m-th eyes are combined, which is the minimum unit in which the pseudo defect is not picked up.

Example 4 This example will be described with reference to FIGS. 11 to 13. FIG. 11 shows a flowchart when the contents shown in the first, second, and third embodiments are programmed. By incorporating the program based on this flowchart into the EB data conversion device or the drawing device,
The contents shown in 2 and 3 can be automatically executed.
Further, FIG. 14 shows an example incorporated in the EB device.

The flowchart of FIG. 11 will be described. First, read the pattern data in STEP1,
Next, in STEP 2, a minute pattern is extracted. In this example, the trapezoid has a height of 3 μm or less and the rectangle has a height of 0.1 μm.
Detected for m or less. However, the value may vary depending on the device pattern rule, the resist material used, and the like, and the value is not limited to this value. At STEP 3, the processing routine is jumped to the rectangular pattern and trapezoidal pattern processing routines. After the processing in each routine is completed, STEP
In step 4, it is judged whether or not the processing has been completed for all the minute figures, and if not completed, the procedure returns to STEP 1,
Similarly, the process is performed up to STEP4. After finishing all patterns, the process ends in STEP5.

If the trapezoidal process is determined in STEP 3, the process jumps to STEP 6 (FIG. 12). ST
In EP7, it is determined whether the height of the trapezoid is 0.7 μm or less. When it is 0.7 μm or less, the rectangle is replaced by the rectangle by the rectangle replacement routine in STEP8. Height is 0.
When it is larger than 7 μm, in STEP 9, rectangular trapezoidal diagonal lines are arranged on the stairs. For example, the pattern of FIG. 2 (b) described above is converted as shown in FIG. 1 (a). Then, in STEP 10, the process returns to STEP 4 of the main routine.

If the rectangular process is determined in STEP 3, the process jumps to the rectangular pattern routine in STEP 11 (FIG. 13). In STEP 12, the pattern is deleted. However, what is deleted and becomes a slit is deleted so as not to become a slit, or is not deleted. Therefore, the process of determining whether or not it is a slit is performed in advance. Next, in STEP 13, the main routine S
Return to TEP4.

FIG. 14 shows the EB apparatus II in which the pattern generating routine of the present invention (pattern generating apparatus I) is incorporated. By incorporating it in the EB device, it is convenient because minute figures are automatically replaced in advance before drawing. Therefore, in the design stage, it is not necessary to design in consideration of the difference in characteristics between the drawing devices, which is advantageous. )

[0051]

As described above, according to the present invention, if a semiconductor integrated circuit pattern generated by a conventional pattern generation method is used as it is to form a photomask, a large number of pseudo defects are generated. It is possible to extract a pattern and automatically replace it with a pattern shape that matches the lithography capability of the photomask process. By using the pattern generation method according to the present invention, the generation of pseudo defects is reduced to zero or suppressed in the inspection step of the photomask formation, the yield is improved by the photomask formation, the cost is reduced, and the throughput is significantly improved. Can be realized. Furthermore, by using the pattern generation method of the present invention, the total number of patterns is reduced, so that it is possible to suppress the capital investment of the data processing system (computer) and shorten the data transfer time by the network. Moreover, the direct drawing apparatus of the present invention can realize drawing having the above advantages.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of pattern generation according to the present invention (a), and an image (b) of an actual pattern thereof.

FIG. 2 is a diagram showing a problem and is a diagram showing an example of a pseudo defect occurring in a photomask.

FIG. 3 is a diagram showing an example of rounding of a corner portion of a rectangular pattern.

FIG. 4 is a diagram showing an example of a trapezoidal pattern drawing method.

FIG. 5 is a diagram showing an example of a pseudo defect generated in a photomask and a solution thereof. It also describes the pseudo defects.

FIG. 6 is a diagram showing an example in which actual patterns are replaced with patterns according to the present invention.

FIG. 7 is a diagram showing a comparative example in which an actual pattern is replaced.

FIG. 8 is a diagram illustrating confirmation by simulation.

FIG. 9 is a diagram showing a result of simulation.

FIG. 10 is a diagram showing a structure of a photomask substrate.

FIG. 11 is a flowchart in the fourth embodiment.

FIG. 12 is a flowchart in Example 4.

FIG. 13 is a flowchart in Example 4.

FIG. 14 is a flowchart in Example 4.

[Explanation of symbols]

1 pattern group 2 triangular pattern 3 rectangular pattern 4 rectangular pattern 5 reduced pattern group 1 pattern group 6 small pattern (pseudo defect occurrence place) 7 rectangular pattern 8 rectangular pattern 9 rectangular pattern 10 actual pattern image 11 rectangular pattern 12 actual Pattern image 13 Rounded corners 14 Desired trapezoidal pattern 15 Rectangular pattern 1 divided to draw a trapezoid
16 Diagonal line of other layer 17 Target contact hole pattern 18 Portion of pattern 17 that has been cut due to the influence of pattern 16 18 'Converted into a rectangular pattern 19 Micro pattern (Pseudo defect occurrence) Location) 20 rectangular pattern 21 rectangular pattern 22 pseudo defect 23 synthetic quartz substrate 24 light-shielding chromium film 25 resist

[Procedure amendment]

[Submission date] February 14, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

[0012] However, the top and bottom of the pattern in the absence of other pattern around the lack of exposure because the total is not a n number of exposures. Furthermore, since the upper and lower portions are exposed by 0.25 μm each, the contact portion with the rectangular pattern is overexposed when the rectangular pattern is in contact.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction content]

By using the photomask substrate shown in FIG. 10, the pattern (FIG. 1A) shown in this embodiment is variably adjusted.
Drawing was performed with a beam-shaped electron beam drawing apparatus (accelerating voltage 20 keV). The electron beam dose at this time is 3.0 μC
Was / cm ² .

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction content]

Here, in the same manner as in the photomask forming process shown in the first embodiment, the variable shaped beam type electron beam drawing apparatus is used for the photomask substrate (quartz / chrome / resist) as shown in FIGS. The pattern was repeatedly arranged and drawn. After that, a development process, post-baking, etching, resist stripping, and cleaning were performed, and then a 0.5 μm defect inspection was performed using an inspection device of KLA. As a result, many pseudo defects were generated in the minute pattern portion of FIG. 7, but no pseudo defects were generated in the region in which FIG. 6 according to the present example was arranged.

Claims (5)

[Claims] 1. A method for designing a circuit pattern of a semiconductor device, comprising a semiconductor circuit pattern generating step of generating a semiconductor circuit pattern to be drawn by a drawing means, wherein the generated circuit pattern is oblique to a drawing direction of the drawing means. An oblique pattern part having an outer shape part, and a rectangular pattern part in contact with the oblique pattern part,
In addition, when the diagonal pattern portion is smaller than a certain size, the diagonal pattern portion is identified, and conversion is performed to replace the diagonal pattern portion with a rectangular pattern obtained by enlarging the rectangular pattern portion. Circuit pattern design method. 2. A circuit pattern designing method for a semiconductor device including a semiconductor circuit pattern generating step of generating a semiconductor circuit pattern to be drawn by a drawing means, wherein the generated circuit pattern is oblique to a drawing direction of the drawing means. An oblique pattern part having an outer shape part of
A method for designing a circuit pattern of a semiconductor device, wherein when the diagonal pattern portion is smaller than a certain size, the diagonal pattern portion is identified and conversion is performed to delete the diagonal pattern portion. 3. A step of reading pattern data, a step of extracting a minute pattern which is a pattern having a rectangular pattern and an oblique outline in the pattern data, and a pattern having an oblique outline of the extracted pattern The method further comprises a step of performing conversion for replacing or deleting one or more rectangular patterns according to the size, and for the rectangular pattern, performing conversion as it is or for deletion depending on the size of the pattern or whether the pattern is a slit or not. The circuit pattern designing method for a semiconductor device according to claim 1 or 2. 4. A direct drawing apparatus for creating a semiconductor circuit pattern and drawing the created circuit pattern by a drawing means, wherein the created circuit pattern has an outer shape portion oblique to the drawing direction of the drawing means. If the pattern portion has a pattern portion and is smaller than a certain size, the pattern portion is identified, and the pattern portion having the diagonal outer portion is identified as 1
Alternatively, a direct drawing apparatus characterized by performing conversion for replacing or deleting with two or more rectangular patterns and performing pattern drawing according to the converted pattern. 5. A size of an outer shape portion which is oblique to the drawing direction is identified, and when the size is larger than a predetermined value, conversion is performed to replace with the rectangular pattern of 1 or 2 or more, and from the specified value. The direct drawing apparatus according to claim 4, wherein the direct drawing apparatus is configured to perform a conversion to delete it when it is smaller.