JPH0715349A - Encoding system - Google Patents

Abstract

PURPOSE:To obtain the inexpensive encoding/decoding device with high compression performance when multivalent signals are encoded or decoded. CONSTITUTION:Markov state is separated and data are encoded based on a signal representing whether or not plural destination symbols (reference symbols) are taken notice of or based on the number of kinds of multilevels generated in the reference symbol. A coincidence detector 9 detects the data in which a reference symbol pattern 102 is coincident. A symbol rearrangement device 10 uses a coincidence detection signal 112 to rearranged reference symbol patterns not duplicated with each other, a multivalent binary converter compares rearranged reference symbols 113 and information source symbols 101 sequentially and provides an output of the result of comparison as a binary encoded symbol 106. Then the rearranged reference symbol 113 and the information source symbol 101 are dissident, a specific information generator 11 and a specific information encoder 12 are used to code the information source symbol 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding / decoding apparatus for multilevel signals, and more particularly to a coding method used in a coding / decoding apparatus for image information.

[0002]

2. Description of the Related Art In coding a Markov information source, a target symbol to be coded is predicted from a reference symbol which has already been coded for an output symbol sequence of the information source, and the prediction error signal is used as a reference symbol pattern. Thus, each prediction error signal is classified into several groups according to the predictive predictive value, and coding is performed using a code suitable for each. Here, the creation of this prediction error signal
Predictive conversion, classification into groups is called integration, and group identifiers are called orders. Further, the prediction error signal to be encoded will be called a prediction error symbol.

In the case where the signal of interest is a binary information source, as a method for this predictive conversion and order selection, there is a technique for performing adaptive processing in order to deal with a local change in the statistical properties of the information source. It is disclosed in Japanese Patent No. 305225. As for the coding method of the prediction error symbol, the subtraction type arithmetic coding method is described in IBM Research and Development Information 1988 11
Mon, Vol. 32, No. 6 (IBM Journal of Reserch and Dev
elopment, Vol.32, No.6, Nov.1988), "An overview of the basic principle of a binary coder for Q-coder" (An overview of
the basic principle of the Q-Coder adaptive-binar
y arith-metic coder) and JP-A-2-202267. These are a kind of number line display coding method that maps a symbol sequence between 0.0 and 1.0 on the number line and encodes the coordinates as a code word. When splitting
It is performed only by addition and subtraction.

In the case of encoding a binary information source, highly efficient encoding close to the entropy of the information source can be realized by these methods. In the case of a multivalued information source, in order to use these binary arithmetic codes, the multivalued signal is converted into a plurality of binary signals and encoded. Hereinafter, a conventional process of predictive conversion, integration and encoding will be described with reference to the drawings. FIG. 23 is a block diagram of a conventional 8-bit image signal encoding device for one pixel. The reference symbol is shown in Figure 2 for simplicity.
The signal at the position A immediately before on the same scan line having the strongest correlation with the target symbol is selected from the 5 pixels of 4. The number of integrations is 16.

In FIG. 23, 1 is a reference symbol generator for selecting and outputting a reference symbol from a sequence of information source symbols 101, and 2 is a reference symbol pattern 102 which is an output thereof, and generates an address 103 of a degree / predicted value memory described later An address generator 3 for outputting an order / predicted value memory for outputting the order 104 and the predicted value 105 of the target symbol after binarization,
4 is a multi-valued binary converter for binarizing the symbol to be encoded,
5 is the output of this converter 4 based on the predicted value 105 2
A predictive converter that creates a prediction error symbol 107 of the value-encoded symbol 106, 6 is an order / predicted value memory third order 10
An area width table for outputting the area width 108 of the arithmetic code based on 4, an arithmetic encoder 7 and an order / predicted value control circuit 8 for controlling reading and updating of the order / predicted value memory.
Here, since the number of reference symbols is 1, the order / prediction value table (contents of the order / prediction value table memory 3)
As shown in FIG. 25, 2 ⁸ × 255 kinds are required. Regarding the order value, the integration is made into 16 groups, and therefore this is identified. Here, the higher the predictive predictive ratio, the higher the order.

Next, the operation will be described. The information source symbol 101 (image signal) generated from the information source is stored in the reference symbol generator 1 and the signal of the pixel shown in A of FIG.
It is output as 2. Based on this, the address generator 2 generates a memory address corresponding to the encoding target bit MSB in the reference symbol pattern shown in FIG. 25, and the order / code memory 3 corresponds to the relevant bit (MSB) of the target symbol. The predicted value 105 and the order 104 are output, and the order 104 information is the area table 4 shown in FIG.
Is converted and output as the area width 108.

On the other hand, the MSB of the information source symbol 101 is selected by the multi-level binary converter 4 and is output as the binary coded symbol 106. In the prediction converter 5, the prediction value 105 and the binary coded symbol 106 are exclusive-ORed to create a prediction error symbol 107. Therefore, this prediction error symbol is 0 (MPS: More Proba
ble Symbol), 1 if not matched (LPS: Less Proba
ble Symbol).

In the arithmetic encoder 7, the prediction error symbol 107 is mapped on the number line based on the region width 108 signal, and coding is executed. Then for the 2nd MSB,
The address generator 2 uses the reference symbol pattern 102 and the MSB pattern of the coded symbol to generate 2nd.
A memory address corresponding to the MSB bit is generated,
The predicted value 105 and the order 104 are output from the order / code memory 3. On the other hand, as the binary coded symbol 106, the second MSB of the generated symbol 101 is selected by the multilevel binary converter 4 and the image / encoding on the number line similar to the above is executed. Similarly, when the coding up to the LSB is completed, the next coding symbol is coded.

The details of arithmetic coding will be touched upon here.
Now, assuming that the i-th symbol in the prediction error symbol sequence is a _i and the LPS mapping range (allocation region) at the i-th time point is S, if the MPS region is located below the effective region, Mapping range of symbol series at the time (effective area)
Ai and its lower bound coordinate Ci are: Ai = Ai-1 −S Ci = Ci-1 when symbol a _i is MPS, Ai = S Ci = Ci-1 + (Ai-1) when symbol a _i is LPS -S).

When the effective area Ai becomes 1/2 or less, the power is multiplied by 2 to increase the calculation accuracy. At this time, overflow of coordinates Ci (portion above the decimal point)
Minutes are output as a code bit sequence. Hereinafter, this exponentiation process is called normalization. Ai update value = Ai * 2 ^m (1/2 <Ai update value ≦ 1) Ci update value = Ci * 2 ^m

In the arithmetic code, it is known that high efficiency coding extremely close to the information source entropy can be performed by setting S to the appearance probability (= prediction error probability) of LPS. Therefore, arithmetic coding can be performed by the above processing by selecting an S value suitable for the predictive predictive value corresponding to the order. FIG. 26 is an example of a correspondence table between the degree and the area width S. The values in the table are the values in the above formula multiplied by 2 ¹⁶ . In this example, the area calculation on the number line is performed with a precision of 16 bits, and Ai and Ci have a decimal precision of 16 bits or less.

Next, the prediction and integration adaptive processing will be described. As this adaptive processing method, there are a method of controlling by counting the number of consecutive MPS and LPS from the output symbol sequence, and a method of controlling the symbol by the MPS or LPS when the above normalization occurs. Here, the latter method will be described as an example. The order / predicted value control circuit 8 determines whether the output symbol of the predictive converter 5 is MPS or LPS during normalization.

In the case of LPS, the order / predicted value memory 3 subtracts 1 from the order value corresponding to the reference symbol pattern at that time. This is an operation of adapting the order / predicted value to the information source that is the current encoding target by lowering the order indicating the accuracy of the prediction because the prediction in the state is wrong. When the order reaches the lowest order and the order cannot be reduced any more, the predicted value is inverted. By this operation, the predicted value with extremely bad hit rate is rewritten.

In the case of MPS In the order / prediction value memory 3, the order value corresponding to the reference symbol pattern at that time is incremented by one. This is an operation of adapting the order / predicted value to the information source that is the current encoding target by increasing the order indicating the accuracy of the prediction because the prediction in the state is correct. If the degree has already reached the highest degree, no addition is performed. When the prediction is extremely accurate by this operation, the S value is reduced by increasing the order, and the code amount output from the arithmetic encoder 5 can be suppressed.

By the above operation, the order / predicted value control circuit 8
Can rewrite the order / predicted value table according to the property of the information source, and realize the arithmetic coding with high coding efficiency.

[0016]

However, in the case of a multivalued information source, the number of Markov states is much larger than that in the case of a binary signal, and it is practically difficult to realize these methods. For example, in the case of the above example, the number of reference symbols is set to one pixel in A of FIG. 24 for simplification, but even if this is to be implemented as a device, as shown in FIG. 256 (2 ⁸ or 0-2
55) There are various types, 255 types (1 + 2 + 4 + 8 + 16 +)
32 + 64 + 128 = 255) and each table requires order 4 bits and prediction value 1 bit, and therefore 256 × 255 × (4 + 1) bits = 6528
A capacity of 0 × 5 bits is required, and a memory needs to be a separate chip to form an LSI. Also, the same memory space is required to realize the S / W. If the number of reference symbols is set to 3, for example, in order to further improve the coding efficiency, and the information source is an 8-bit image signal, the size of the order / prediction value memory 3 is 2 ²⁴ × 255 × (4 + 1).
It becomes a bit and cannot be realized.

The present invention has been made in order to solve the above-mentioned problems, and is capable of widely incorporating reference symbol information and highly efficient code capable of significantly reducing the order / prediction value memory. The purpose is to obtain a system.

[0018]

The encoding system according to the first aspect of the present invention focuses on a plurality of preceding symbols (reference symbols) having a predetermined positional relationship and detects whether they are equal to each other or not. And means for separately encoding the Markov state based on this information.

In the encoding system according to the second aspect of the invention, attention is paid to a plurality of preceding symbols (reference symbols) having a predetermined positional relationship, and the number of types of multi-valued levels occurring in the reference symbols is detected. And means for separately encoding the Markov state.

In the encoding system according to the third aspect of the present invention, a means for rearranging symbols in a predetermined order after deleting symbols having overlapping levels in the reference symbols and the rearranged encoded symbols are arranged. Multi-value binary conversion means for generating a signal indicating whether or not each symbol is equal,
It is provided with a means for sequentially encoding this with a binary arithmetic code.

In the coding method according to the fourth aspect of the present invention, when the level of the coded symbol does not occur in the reference symbol, means for generating information for specifying the level of the coded symbol and this information are provided. An encoding means for encoding is provided separately from the binary arithmetic code.

In the coding method according to the fifth aspect of the present invention, when the level of the coded symbol does not occur in the reference symbol, a signal sequence including the level signals other than the rearranged reference symbol is generated. Means and a multi-valued binary conversion means for generating whether or not the coded symbol is equal to each level signal of this signal sequence. .

In the encoding system according to the sixth aspect of the present invention, when the level of the coded symbol does not occur in the reference symbol, means for generating information of the number of bits necessary for specifying the level of the coded symbol. And this specific information
It is provided with a means for selecting bit by bit.

The encoding system according to the seventh aspect of the present invention uses 2 for each binary arithmetic encoding step of each Markov state.
It is provided with means for updating the value symbol appearance probability during encoding.

The encoding system according to the eighth aspect of the present invention comprises means for generating a signal for identifying a binary symbol appearance probability for each step of each binary arithmetic encoding of each Markov state.

In the encoding system according to the ninth aspect of the present invention, the level of the reference symbol and the level of the encoded symbol having a predetermined positional relationship are compared with each other, and the encoded symbol is converted based on the comparison result. It is equipped with means.

[0027]

In the encoding system according to the first aspect of the present invention, the information source is integrated by the information indicating which reference symbols are equal (or not equal) to each other, so that the information compression is performed with high compression performance. Is possible.

The encoding system according to the second aspect of the present invention enables information compression with high compression performance by integrating the information sources according to how many kinds of multi-valued levels are in a plurality of reference symbols. It is a thing.

In the encoding method according to the third aspect of the present invention, the information compression is performed with high compression performance by binary-encoding the signal indicating whether the level value occurring in the reference symbol is equal to the encoded symbol. Is possible.

In the coding method according to the fourth aspect of the present invention, when the level of the coded symbol does not occur in the reference symbol, the information for specifying the level is separately coded to compress the information with high compression performance. It is possible.

In the coding system according to the fifth aspect of the present invention, when the level of the coded symbol does not occur in the reference symbol, it is determined whether the level signal other than the level occurring in the reference symbol is equal to the coded signal. Binary arithmetic coding enables information compression with high compression performance.

In the coding method according to the sixth aspect of the present invention, when the level of the coded symbol does not occur in the reference symbol, the signal specifying this level is binary-coded bit by bit to achieve high compression. It enables information compression with performance.

The encoding system according to the seventh invention is 2
In value arithmetic coding, the binary symbol appearance probability is updated according to the signal sequence that actually occurs, thereby enabling information compression with high compression performance.

The encoding system according to the eighth invention is 2
In the value arithmetic coding, it is possible to compress information with a high compression performance by presetting a binary symbol appearance probability considered appropriate in the coding of the information source, and then performing an actual coding process. Is.

In the encoding system according to the ninth aspect of the present invention, the conversion means compares the reference symbol and the encoded symbol, and the encoding means performs the encoding based on the comparison result. If it often takes the same value as the reference symbol, efficient encoding is possible. In particular, when encoding image information such as animations and computer graphics created by computer programs, etc., a specific pattern is often repeated or displayed in a limited color. Is likely to take the same value as the reference symbol, and when encoding such information, the reference symbol and the encoded symbol are compared and the comparison result indicating whether or not they match is encoded. By doing so, efficient encoding can be performed.

[0036]

EXAMPLES Example 1. Hereinafter, the present invention will be described based on illustrated embodiments. FIG. 1 is a block diagram of a coding device for an image signal consisting of 8 bits per pixel in the present invention. The difference from the conventional coding device in FIG. 23 is that reference symbol pattern 1 is used.
02, the coincidence detector 9 for detecting the coincidence relationship between the reference symbols, the symbol rearranger 10 for rearranging the level values of the reference symbol pattern 102 based on the output 112, the attention source symbol 101 Information generator 11 for identifying this level when it does not occur in this reference symbol, the encoder 12 for encoding this specific information signal 115, and the output 11 of the arithmetic encoder 7.
4 and the output 116 of the specific information encoder 12 to switch the output 116 to the code output 109.

Next, the operation of this embodiment will be described.
Here, a case where the number of reference image elements is 5 will be described. Here, reference pixels (also referred to as reference symbols) are five pixels A, B, C, D, and H shown in FIG. Also,
Since one pixel is expressed by 8 bits, the signal level (also referred to as a level value) of each reference symbol is assumed to be any of 0 to 255. Symbol 10 generated from the information source
1 (image signal) is stored in the reference symbol generator 1 and the signal of 5 pixels shown in FIG. 24 is selected and output as the reference symbol pattern 102. The coincidence detector 9 detects the coincidence relationship between the reference symbols.

Since the number of reference pixels is 5, there are 52 matching patterns as shown in FIG. 2, from the case where all 5 pixels match to the case where only 1 pixel differs ... There will be a combination. Here, in # 1 to # 5, the reference symbols are arranged in the order of A, B, C, D, and H, and the level newly generated among the level values (0 to 255) of the reference symbol is sequentially numbered from # 1. Numerical values are shown when the items are marked with. For example, A, B, C,
When the D and H levels are all equal, the generated levels are # 1, # 1, # 1, # 1, and # 1. Also, A,
When the levels of B, C and D are the same and the levels of H are different, the generated levels are # 1, # 1, # 1, # 1 and # 2.
Becomes When the A, B, C, and H levels are the same and the D levels are different, the generated levels are # 1, # 1,
It becomes # 1, # 2, # 1. The coincidence signal 112 is a 6-bit signal for identifying the 52 patterns. The symbol rearranger 10 receives the coincidence signal 112 and outputs the newly generated level value as the rearranged reference symbol 113 when the reference symbols are arranged in the order of A, B, C, D, and H. For example, when the levels of A, B, C, D, and H are all the same, since the level that has occurred is only # 1, the symbol rearranger 10 uses A as the rearrangement reference symbol.
The level value of is output to the multi-value binary converter 4. When the levels of A, B, C, and D are the same and the level of H is different, the generated levels are # 1 and # 2, and the level value of A and the level value of H are rearranged.
Is output to the multi-valued binary converter 4. Similarly,
When the levels of A, B, C, and H are equal and the level of D is different, the generated levels are # 1 and # 2, and the level value of A and the level value of D are multivalued as the rearrangement reference symbol 113. Output to the binary converter 4.

The multi-valued binary converter 4 detects whether or not the symbol 101 to be coded and the rearrangement reference symbol 113 match and creates a binary coded symbol 106, which is then processed in the same manner as the conventional device. To perform binary arithmetic coding. if,
When none of the reference symbols matches, the specific information encoder 12 Huffman-encodes the encoding target symbol itself as the specific information signal 115.

The case where the levels of the five reference symbols are all different and the levels are the same will be described below.
In the following description, the left and right sides of "=" indicate the symbol level. Further, “! =” Indicates not =, and the left side and the right side thereof similarly indicate the level of the symbol. For example, when the levels of the five reference symbols are different from each other (1) When X = # 1, “0” is arithmetically coded, and X! == 1, "1" is arithmetically coded, and to (2) (2) When X = # 2, "0" is arithmetically coded, and X! == # 2, "1" is arithmetically coded, and to (3) (3) When X = # 3, "0" is arithmetically coded, and X! If # = 3, "1" is arithmetically coded, and to (4) (4) When X = # 4, "0" is arithmetically coded, and then X! If # = 4, "1" is arithmetically coded, and to (5) (5) If X = # 5, "0" is arithmetically coded, and X! In the case of = # 5, "1" is arithmetically coded, and (6) to (6) X is coded by the specific information encoder 12 and the process to the next coding target symbol is performed.

On the other hand, when all five reference symbols match (1) When X = # 1, "0" is arithmetically coded, and X! In the case of = # 1, "1" is arithmetically coded, (2) to (2) X is coded by the specific information encoder 12, and the process to the next coding target symbol is performed. The same processing is performed when the number of occurrence levels in the reference symbol is other than 1.

FIG. 3 is a diagram showing an example encoded by this embodiment. FIG. 3A shows a case where the level of the encoding target symbol X matches the level of any reference symbol. For example, 31 is the encoding target symbol X
Shows the case where matches with # 1. Reference numeral 32 indicates a case where the encoding target symbol X matches # 2.
33 shows the case where the encoding target symbol X matches # 3. 34 shows the case where the encoding target symbol X matches # 5. FIG. 3B shows an example in which the levels of the five reference symbols are different, and the level of the encoding target symbol X does not match any level of the five reference symbols. In this case, 5 indicating that the reference symbols did not match 5
The bit "1" and the specific information signal 36 are output. Figure 3
(C) shows a case where all five reference symbols match, and the target symbol X does not match the level of the reference symbol. In this case, 1-bit "1" and the specific information signal 38 are output. FIG. 3D shows a case where the above-described information shown in FIGS. 3A to 3C continuously occurs.

The binary coded symbols 106 generated by the multi-valued binary converter 4 are input to the predictive converter 5 as a sequence as shown in FIG. 3D, and then coded by the arithmetic encoder 7. . On the other hand, the specific information signal 115 created by the specific information creator 11 is input to the specific information encoder 12,
It is encoded and output.

As is clear from the above description, in the binary arithmetic coding step, the binary coded symbol 10 to be coded is processed according to the number of levels occurring in the reference symbol.
The number of 6 will be different. Therefore, in order to perform efficient encoding for each of them, separate numerical values (tables) are prepared for the order and the predicted value stored in the order / predicted value memory 3. The total number of tables is 151, as shown in FIG. FIG. 4 shows an example of the contents of this table.

For example, as shown in FIG. 3, A, B, C,
When the levels of D and H are all the same, it has one kind of table as to whether the level of the symbol X to be coded is equal to the level of the reference symbol A. Further, when the level of the reference symbol H is different from other levels, the table referred to when the level of the encoding target symbol X is equal to the reference symbol A, and the level of the encoding target symbol X is the reference symbol. Two tables are prepared to be referred to when the level is equal to the H level.

The specific information signal 115 can be encoded by performing Huffman encoding according to the symbol appearance probability of the information source. Alternatively, more simply, the encoding target symbol X itself may be encoded with 8 bits. The switch 13 switches between the arithmetic code 114 encoded by the arithmetic encoder 7 and the specific information code 116 encoded by the specific information encoder 12 and outputs the code 109. In the switching operation of the switch 13, the two codes 114 and 116 may be switched by time division, or when the two codes 114 and 116 are multiplexed and output as one code 109. It doesn't matter. The arithmetic encoder 7 and the specific information encoder 12 respectively generate the arithmetic code 114 and the specific information code 116, store the generated codes 114 and 116 in a memory (not shown), and the switching unit 13 separately in the memory. The stored arithmetic code 114 and specific information code 116 are read out to generate and output code 109.

According to the above method, a highly efficient coding device using the information of 5 pixels in FIG. 24 as the reference symbol information can be realized. Moreover, the capacity of the order / prediction value memory 3 used for learning can be realized by an extremely small circuit of 151 × (4 + 1) bits.

As described above, this embodiment can efficiently perform encoding when the level of the symbol X to be encoded has the same level as the reference symbols A, B, C, D and H. For example, computer graphics,
When encoding an image signal such as animation, the same color or limited colors are often used continuously, and thus such an encoding method is well suited. Compared with the case of encoding the image information that displays infinite colors such as natural images, the encoding efficiency in the case of encoding the image information by computer graphics as described above or the image information such as animation is higher. improves.

Example 2. FIG. 5 shows a block configuration of a decoding apparatus which is another embodiment of the present invention. In the figure, 13
Is a switch that reads separately stored arithmetic code data and specific information coded data according to the request of each decoder described later,
14 is an arithmetic decoder that reproduces a prediction error symbol from the arithmetic code bit sequence 114 based on the region width 108, 15 is a specific information decoder that reproduces the specific information signal 115 from the specific information code bit sequence 116, and 16 is the above prediction A predictive inverse converter that reproduces the binary coded symbol 106 by performing an exclusive OR operation of the error symbol 107 and the predicted value 105, and 17 is an encoder based on the rearrangement reference symbol 113 and the binary coded symbol. A binary multi-valued converter that reproduces the source symbol when the symbol is the same as the level in the reference symbol, 1
Reference numeral 8 is a specific information inverse converter that reproduces the information source symbol based on the specific information signal 115 when the level of the coded symbol does not occur in the reference symbol, and 19 selects the signals of these two converters and outputs the information. It is a switcher for use as a source symbol, and the other part has the same circuit as the encoding device of FIG.

The switch 13 may be the same as the switch 13 shown in FIG. In this case, switch 13
Does not generate the code 109, reads the arithmetic code output 114 and the specific information code output 116 from the respective memories, and outputs them to the arithmetic decoder 14 and the specific information decoder 15. Also,
The switch shown in FIG. 5 and the switch shown in FIG. 1 may be connected to each other by a line or the like and arranged at a remote place. In this case, the switch 13 of the decoding device has a function of time-divisionally separating the arithmetic code and the specific information code from the transmitted code 109 or separating the multiplexed data.

The operation of this embodiment will be described below. First, the coded data sequence 109 is subjected to 1-symbol arithmetic decoding by an arithmetic decoder. In decoding the arithmetic code, C
Let Ci be the relative coordinates that are the contents of the register and S be the region width of the LPS at the time of the i-th prediction error symbol a _i . If Ci-1 <(Ai-1 -S), then a _i is MPS Ai = If Ai-1 -S Ci = Ci-1 Ci-1 ≥ (Ai-1 -S), then _ai is LPS Ai = S Ci = Ci-1-(Ai-1 -S). Here, when the effective area Ai becomes 1/2 or less, the power is multiplied by 2 as a normalization process in order to improve the calculation accuracy. At this time, n-bit code data is input to the lowest order of Ci. Ai update value = Ai * 2 ^m (1/2 <Ai update value ≦ 1) Ci update value = Ci * 2 ^m

The prediction inverse converter 16 reproduces the prediction value 105 when the prediction error symbol is the MPS, and when the prediction error symbol is the LPS, the inverted value as the binary coded symbol 106 for each bit. Then, in the binary multilevel converter 17, the information source symbol is reproduced by the rearranged reference symbol, but the level of the information source symbol cannot be specified (that is, when the binary coded symbols for the symbol are all 1s). )
The specific information decoder decodes the specific information, and the specific information inverse converter 18 reproduces the information source symbol.

For example, when the levels of the 5 reference symbols are different, 1-bit arithmetic decoding is performed, and (1) when the binary coded symbol is "0", X = # 1 is set and the binary code is processed. When the coded symbol is “1”, 1-bit arithmetic decoding is performed to (2) (2) When the binary coded symbol is “0”, X = # 2 is set, and the binary coded symbol is “1” for the processing of the next symbol. In case of "1 bit arithmetic decoding to (3) (3) When binary coded symbol is" 0 "X = # 3 and proceed to processing of next symbol When binary coded symbol is" 1 "1 bit Arithmetic decoding to (4) (4) When the binary coded symbol is “0”, set X = # 4, and to the processing of the next symbol When the binary coded symbol is “1” 1-bit arithmetic decoding (5 ) To (5) When the binary coded symbol is “0”, set X = # 5 and proceed to the processing of the next symbol. "When the (6) (6) decrypts X by specific information decoder, the processing of the next symbol.

For example, conversely, when all 5 reference symbols match, 1-bit arithmetic decoding is performed, and (1) When the binary coded symbol is "0", X = # 1 is set, and the binary code is processed to the next symbol. If the symbolized symbol is "1", go to (2) (2) X is decoded by the specific information decoder, and the process for the next symbol is performed. The same processing is performed when the number of occurrence levels in the reference symbol is other than 1.

For example, in the case shown in FIG. 3A, when 0 is decoded in the binary coded symbol 106, the binary multilevel converter 17 is output from the symbol rearranger 10. The source level 101 is generated using the first level of the rearranged reference symbols. Alternatively,
When the binary coded symbol 106 is decoded as 1, 0, the binary multilevel converter 17 rearranges and outputs the rearranged reference symbol 113 rearranged from the symbol rearranger 10.
The second one is generated as the information source symbol 101. Further, as shown in FIG. 3B, when the binary coded symbol 106 is decoded as 1, 1, 1, 1, 1, the binary multilevel converter 17 is the information source symbol 101 is the symbol. It is determined that none of the rearrangement reference symbols output from the rearranger 10 matches. In this case, the switch 19 uses the information from the specific information inverse converter 18 to generate the information source symbol 101. Also, FIG.
As shown in (c), when 1 is decoded as the binary coded symbol 106, the binary multilevel converter 17 outputs the rearrangement reference symbol 113 and the information source symbol output from the symbol rearranger 10. It is detected that 101 has different values. In this case, the switch 19 uses the specific information signal 115 from the specific information inverse converter 18 to generate the information source symbol 101. By these processes, the information source symbol 101 can be reproduced without distortion.

Example 3. In the above embodiment, the order
Although the order / prediction value table stored in the prediction value memory 3 is set individually for all matching states of reference symbols, it is also possible to perform appropriate degeneration in order to reduce the device scale. FIG. 6 shows an example thereof, in which one having the same number of occurrence levels of signals in the reference symbol is 1
Integrated into one. This integration is shown by "type of level in reference symbol" in FIG. As a result, the order / predicted value memory 3 may have 15 × (4 + 1) bits.

Example 4. FIG. 7 shows a case where appropriate degeneration is performed in order to further reduce the device scale. FIG. 7 is a further reduction of the one shown in FIG. 6 to have one table for each level type. That is, the number of occurrence levels of the signal in the reference symbol is 1, 2,
In any case of 3, 4 and 5, only one table is provided. As a result, the order / predicted value memory 3 may have 5 × (4 + 1) bits.

Example 5. Further, FIG. 8 shows a block diagram of an encoding device according to another embodiment. In the present embodiment, the specific information is coded by the same method as the level signal generated in the reference symbol. Therefore, in the block configuration of this embodiment, the specific information generator 11 and the specific information encoder 1 are different from those of the embodiment of FIG.
2. The switch 13 is deleted.

The encoding procedure of this embodiment is, for example,
When the levels of all five reference symbols are different (1) When X = # 1 "0" is arithmetically coded and the next symbol to be coded is processed by X! == 1, "1" is arithmetically coded, and to (2) (2) When X = # 2, "0" is arithmetically coded, and X! == # 2, "1" is arithmetically coded, and to (3) (3) When X = # 3, "0" is arithmetically coded, and X! If # = 3, "1" is arithmetically coded, and to (4) (4) When X = # 4, "0" is arithmetically coded, and then X! If # = 4, "1" is arithmetically coded, and to (5) (5) If X = # 5, "0" is arithmetically coded, and X! If # = 5, "1" is arithmetically coded, and to (6) (6) If X = ## 1, the "0" is arithmetically coded, and then X! == ## 1, "1" is arithmetically coded, and goes to (7) ... (255) X = ## 250 When "0" is arithmetically coded, the next symbol to be coded is processed X! When ## 250, "1" is arithmetically coded, and the process proceeds to the next coding target symbol.

Here, ## 1 to ## 250 are arranged in descending order of appearance probability after deleting those generated in the reference symbol pattern from the 256 kinds of level values of the information source symbol. Here, the comparison of 255 is performed by detecting up to 255 matches and inconsistencies when only 256 kinds of level values exist, and when remaining up to 255 inconsistencies are detected, the remaining 256 This is because the level value of the event is automatically determined.

When all the five reference symbols match, (1) When X = # 1, "0" is arithmetically coded, and X! == # 1 "1" is arithmetically coded, and to (2) (2) When X = ## 1, "0" is arithmetically coded and the next symbol to be processed is processed by X! == # # 1 arithmetically encodes "1" and goes to (3) ... (255) X = ## 254 arithmetically encodes "0" to process the next symbol to be encoded X! In the case of = ## 254, "1" is arithmetically coded and the next symbol to be coded is processed. The same applies when the number of occurrence levels in the reference symbol is other than 1,5.

FIG. 9 shows ## 1 to ## 250 (or ##
It is a figure which shows the method of generating the symbol patterns of 250 to ## 254). FIG. 9A is a pattern table arranged in descending order of appearance probability from 256 possible level values of the information source symbol. A pattern table having the same content is prepared in both the encoding device and the decoding device. This pattern table can be shared by communicating with each other when the power is turned on. Alternatively, when there is a need for a change, they may communicate with each other and update each time. In this way, it is assumed that the pattern table as shown in FIG. 9A is provided in the encoding device and the decoding device. Then, as shown in the figure, when five reference symbols are present at different levels in the pattern table, the ones occurring in the reference symbol pattern are deleted,
A new pattern table as shown in FIG. 9B is generated. The new pattern table shown in FIG. 9B is also arranged in descending order of appearance probability. Note that the case shown in FIG. 9 shows a method of generating a pattern table when all five reference symbols are different. However, when all five reference symbols match, one of 256 level values One level value is removed and a pattern table having 255 new level values is newly generated. The pattern table can be generated in the same manner even when the number of occurrence levels in the reference symbol is other than 1 or 5.

In the case of the present embodiment, if the capacity of the order / prediction value memory 3 is focused only on the number of levels (1 to 5) occurring in the reference symbol as shown in FIG. In both cases, binary arithmetic coding is performed a maximum of 255 times, so that the number of bits is 5 × 255 × (4 + 1) bits.

Example 6. FIG. 11 is a block diagram of a decoding device for decoding the encoded data based on the embodiment of FIG. The configuration is the same as that of the apparatus of FIG. 8 except that 14, 16, 17 are arithmetic decoders, predictive inverse converters, and binary multilevel converters.

Example 7. Further, FIG. 12 shows a block diagram of an encoding apparatus according to another embodiment. In the present embodiment, as a method of encoding the specific information, the numerical value of the encoding target symbol is binary arithmetically encoded one bit at a time starting from the MSB. Therefore, in the block configuration of this embodiment, as compared with the embodiment of FIG. 1, the specific information encoder 12 and the switch 13 are deleted, and the multilevel binary converter 19 for specific information and the binary coded symbol 106 are provided. A switch 20 for switching the specific information binary symbol 117 which is the output of the specific information multi-level binary converter 14 and inputting it to the prediction converter 5 is added.

In this embodiment, except for the coding of the specific information, the same processing as that in the embodiment of FIG. 1 is performed, and the coding of the specific information is performed as in the conventional apparatus of FIG. That is, for example, when the levels of the five reference symbols are different from each other (1) In the case of X = # 1, "0" is arithmetically coded, and X! == # 1 "1" is arithmetically coded, to (2) (2) When X = # 2 "0" is arithmetically coded, and the next symbol to be processed is processed by X! == # 2 "1" is arithmetically coded, and (3) to (3) When X = # 3, "0" is arithmetically coded and the next symbol to be processed is processed into X! == # 3, "1" is arithmetically coded, and (4) to (4) When X = # 4, "0" is arithmetically coded, and the next encoding target symbol is processed by X! == # 4 "1" is arithmetically coded, and to (5) (5) When X = # 5, "0" is arithmetically coded, and the next encoding target symbol is processed by X! When == 5, "1" is arithmetically coded, (6) to (6) X MSB is arithmetically coded, (7) to (7) X 2nd MSB is arithmetically coded, and (8) to ... (13) Arithmetically encode the LSB of X and proceed to the next symbol to be encoded.

On the contrary, when all the five reference symbols match (1) When X = # 1, "0" is arithmetically coded, and X! When == 1, "1" is arithmetically coded, (2) MSB of (2) X is arithmetically coded, (3) is 2nd MSB of (3) X is arithmetically coded, and (4) is ... -(9) The LSB of X is arithmetically coded and the next symbol to be coded is processed. The same applies when the number of occurrence levels in the reference symbol is other than 1,5.

FIG. 13 shows an example of the contents of the order / predicted value memory 3 used in the coding of the specific information in this embodiment. In the present embodiment, the order / predicted value memory 3
As for the capacity of (1
5 + 255) × (4 + 1) bits.

Example 8. FIG. 14 is a block diagram of a decoding device for decoding the encoded data based on the embodiment of FIG. 14, 16, 17, 18, and 21 are arithmetic decoders, predictive inverse converters, binary multilevel converters, specific information inverse converters, and specific information binary multilevel converters. A switch 22 for selecting the signal from the converter 17 and the signal from the specific information inverse converter 18 as the information source symbol 101
The configuration is the same as that of the apparatus of FIG. 12 except that is added.

FIG. 15 shows the number of code bits per pixel when an image signal of 8 bits per pixel is actually coded by the coding method shown in the embodiments of FIGS. 12 and 14. is there. The target image is a natural image or a color signal represented by 8-bit palette data on a menu screen of a personal computer.
For reference, the method based on the multi-valued Markov model with no degeneracy shown in the conventional embodiment, and the 8-bit signal is converted into eight bit plane signals in order from the MSB to form an image vertically connected. On the other hand, the numerical values in the case of applying the binary Markov model coding, that is, the case of applying the MMR coding method 54 which is the standard method of the facsimile to the bit plane image are shown. In the three types of Markov model encoding, the number of reference pixels is 5, 1 and 10 in order, and the table size of the order / predicted value is 15 + 255,25 in order.
It is 6 × 255,2 ¹⁰ .

In this simulation, the binary arithmetic code is
Fumitaka Ono, Masayuki Yoshida, Tomohiro Kimura, Shigenori Kino: "MEL-
Arithmetic Markov Model Coding Using CODE "199
0th IEICE Spring National Convention, SA-6-3,
The arithmetic type MELCODE shown in (1990) was used. Therefore, the code order is different from that shown in the embodiment,
There are 32 species.

As can be seen from the figure, compared with the conventional Markov model coding, the coding performance is 1 even though the order / prediction table is 1/240 or 1 / 3.8.
It has improved by 6% or 44%. In addition, it is possible to improve the compression performance by about 2.3 times as compared with the method using MMR.

Further, the natural image and the palette image will be compared. For natural images, when using the method of the present invention,
Although the coding accuracy is not so high, when the palette image is used, the coding accuracy is further improved as compared with the natural image. From this, it is understood that the compression performance of the method of the present invention is further improved in the case of an image by a computer program such as an image by an animation, a graphic image by a computer, a menu image or the like.
In addition, comparing an 8-bit signal with eight bit plane signals in order from the MSB and applying unknown Markov model coding to an image in which the eight bit plane signals are connected vertically, the method 51 of the present invention is compared. In the case of 53, the number of reference pixels is used, whereas in the method of the present invention, the number of code bits in method 51 is smaller than that of method 53, although the number of reference pixels is 5. Therefore, method 53 is method 5 even though it has many reference pixels.
It can be seen that the coding performance is inferior to that of 1.

Example 9. In each of the above embodiments, no particular setting is made for the initial value of the order / prediction value memory 3 (for example, the order is the minimum value 1 and the prediction value is 0 in each table). It is also possible to measure the statistics of the information source and set an appropriate initial value.
In this case, a method that uses a common initial value between the encoding device and the decoding device on the implicit premise, some typical initial value sets are prepared, and which one of them is encoded / decoded. A method of instructing prior to encoding, a method of specifying all initial values prior to encoding / decoding, and the like are possible.

For example, as a signal for identifying the appearance probability of a binary symbol, the target information source is encoded in advance and the order
The data stored in the prediction value memory 3 can also be used. Encoding the target information source in advance means learning in advance the establishment of the appearance of the symbol possessed by the target information source by prescanning a part of the target information source prior to the actual encoding. There is. For example, as the signal for identifying the appearance probability of the binary symbol, the data stored in the order / predicted value memory 3 by previously encoding the target information source can be used. In this case, the contents of the order / predicted value memory 3 may be downloaded (uploaded) to the host (control device) side, and this data may be downloaded to the decoding device prior to encoding. 16 and 17 show a configuration example in the case of uploading or downloading the contents of the order / predicted value memory 3. 16 and 1
In FIG. 7, 60 is an updater that uploads the contents of the order / prediction value memory 3 and sends it to the host 61, or an updater that receives the contents of the memory from the host 61 and updates the contents of the order / prediction value memory 3. is there. In the case of the embodiment of FIG. 1, the data size is 151 as described above.
× 5 bits.

Example 10. In the above embodiment, the example of updating the contents of the order / prediction value memory 3 for identifying the symbol appearance probability in each step of the binary arithmetic coding is described, but as described above, the order / prediction value is updated. The memory 3 may be provided with a download function so that it is not updated during a single information source encoding process. As a result, the encoding / decoding process can be speeded up. 16 and 17 described above show the configuration of this embodiment. As shown in FIG. 1, since the order / predicted value memory control circuit 8 does not exist, the contents of the order / predicted value memory 3 are coded. It cannot be updated in the process of conversion. However, since the updater 60 is present instead, the order / predicted value memory 3 can be provided with a function of updating the entire contents of the memory.

Example 11. In the above embodiment, the case where the encoding is performed using the arithmetic encoder and the arithmetic decoder has been described, but not limited to the case where the arithmetic encoder and the arithmetic decoder are used, the case where other encoders or decoders are used. It doesn't matter. FIG. 18 shows a case where a block type binary encoder 70 is used instead of the arithmetic encoder. This is a separate volume of the Institute of Electronics and Communication Engineers, "Encoding and compression of binary information sources" (Onishi, Ueno, Ono: Trens.IECE'77 / 12 Vol.60.
-A No.12, pp.1114-1121) is an encoder for encoding the binary information source. FIG. 19 is a diagram showing an example of the encoding method shown in the above-mentioned paper. When the block type binary encoder 70 encodes a binary information source according to the encoding method as shown in FIG. 19, k> k ^m + k ^{m + 1} ≧ 1 where k is the appearance probability of the dominant symbol. Order m to meet
If is selected, the coding is performed by utilizing the fact that the coding efficiency is the highest. M in FIG. 19 corresponds to the degree 104 in FIG. 18, and the notification in FIG. 19 corresponds to the prediction error symbol 107 in FIG.
The block type binary encoder 70 inputs the degree M and the notification 107 to perform encoding according to a code format as shown in FIG. Although not shown, the decoding device is provided with a block type binary decoder and performs an operation reverse to that of the block type binary encoder 70 shown in FIG. Play the symbolized symbol.

Example 12. FIG. 20 is a diagram showing a case where the Huffman encoder 80 is used instead of the arithmetic encoder for the number of encoding. In the figure, 90 is the information source symbol 10.
Level converter that outputs 256 values from 1 level, 8
0 is a Huffman encoder including the Huffman encoder 1 to the Huffman encoder 5, 91 and 92 are selectors for selecting one of the Huffman encoder 1 to the Huffman encoder 5, and 2 is a Huffman for the selectors 91 and 92. A selected address generator that outputs a selected address signal that selects one of the encoders 1 to 5.

Next, FIG. 21 is a diagram for explaining the operation of the coding apparatus shown in FIG. The Huffman encoder 1 is, for example, an encoder that encodes an information source symbol when all levels of five reference symbols match. The Huffman encoder 2 is an encoder that encodes an information source symbol when two levels among the five reference symbols occur. Similarly, the Huffman encoders 3, 4, and 5 have three levels out of five reference symbols, four levels, and five levels.
An encoder that encodes source symbols when one level occurs. The selection address generator 2 receives the match signal 1
By entering 12, it is determined how many levels have occurred in the 5 reference symbols, and which Huffman encoder to select based on the number of levels that have occurred. For example, when the levels of all five reference symbols are the same, the number of levels is 1, and the selection address signal 103 is output so as to select the Huffman encoder 1. Selectors 91 and 92 select the Huffman encoder 1.

On the other hand, the level converter 90 compares the information source symbol 101 and the rearranged reference symbol input from the symbol rearranger 10, and compares which level is the same. For example, if the number of levels is 1, ## 1, #
It is assumed that # 2 and ## 255 are registered in advance as a pattern table in descending order of appearance probability, as in the case shown in FIG. If the level of the source symbol 101 is #
If it matches No. 1, No. Outputs 0. Alternatively, if the level of the information source symbol 101 matches ## 1, No. 1 is output. The Huffman encoder is the No. 1 output from the level converter. 1-No. According to the number of 255, the Huffman code corresponding to the number is output as a code. For example, as shown in FIG. 21, when the number of levels is 1 and the number matches # 1, No. 0 is output, and the Huffman encoder 1 outputs "11" as the Huffman code. When the number of levels is 2 and the information source symbol matches # 2, No. 1 is output, and the Huffman encoder 2 outputs No. "01" as a code corresponding to 1
Is output. As described above, in this embodiment, the case where the Huffman encoder is used instead of the arithmetic encoder described above has been described. As shown in the eleventh embodiment and the twelfth embodiment described above, the encoding system is not limited to the arithmetic encoder, and other encoders may be used. Further, an encoder other than the encoders shown in the eleventh and twelfth embodiments may be used.

Example 13 In the above embodiment, the coincidence detector 9 detects whether or not there is a coincidence in the reference symbol patterns. However, as shown in FIG. 22, even if the coincidence detector does not exist. I do not care. When the coincidence detector 9 does not exist, the symbol rearranger 10 rearranges all the reference symbol patterns 102 output from the reference symbol generator, and the reference symbol 1
Output as 13. For example, when using 5 reference symbols, 5 reference symbols A, B, C, D, H
Is always output to the multi-valued binary converter 4 as the rearrangement reference symbol 113. If the source symbol 101
Is always present in these five reference symbols, the binary coded symbol 106, which is the output from the multi-level binary converter 4, produces a similar output with or without the coincidence detector 9. To do. That is, the length of the binary coded symbol 106 to be output does not change. However, when the information source symbol 101 does not exist in the rearrangement reference symbol 113, in the example shown in FIG.
Will be output. Then, the specific information generator 11
Thus, the specific information signal 115 is output. According to the method shown in FIG. 22, the higher the probability that the information source symbol 101 takes the same level as the reference symbol, the more the disadvantage due to the absence of the coincidence detector 9 disappears. Although not shown, the coincidence detector 9 may not be provided in each of the above-described embodiments.

Example 14 Although the number of reference symbols is five in the above embodiment, the number of reference symbols is not limited to five, and may be one or more.

Example 15 In the above-mentioned embodiment, an example is shown in which H / W is used for encoding, but the same effect can be obtained when this process is realized by S / W programming.

[0084]

As described above, according to the present invention, a plurality of preceding symbols (reference symbols) having a predetermined positional relationship when encoding a multi-valued Marcol information source are used.
, The Markov state is separated and encoded by the signal indicating whether or not they are equal to each other, or the number of types of multi-valued levels occurring in the reference symbol, thereby significantly improving the encoding efficiency. In addition, it is possible to realize an encoding / decoding device having a small device scale.

[Brief description of drawings]

FIG. 1 is a block diagram of an encoding device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the contents of a degree / predicted value memory in the embodiment of FIG.

FIG. 3 is a diagram showing a specific example of a binary coded symbol and a specific information signal in the embodiment of FIG.

FIG. 4 is a diagram illustrating an example of contents of a degree / predicted value memory in the embodiment of FIG.

FIG. 5 is a block diagram of a decoding device according to another embodiment of the present invention.

FIG. 6 is a diagram for explaining another example of the contents of the order / predicted value memory in the embodiment of the present invention.

FIG. 7 is a diagram for explaining another example of the contents of the order / predicted value memory in the embodiment of the present invention.

FIG. 8 is a block configuration diagram of an encoding device showing another embodiment of the present invention.

FIG. 9 is a diagram showing a pattern table creating method according to another embodiment of the present invention.

FIG. 10 is a diagram illustrating the contents of a degree / predicted value memory according to another embodiment of the present invention.

FIG. 11 is a block diagram of a decoding device showing another embodiment of the present invention.

FIG. 12 is a block configuration diagram of an encoding apparatus showing another embodiment of the present invention.

13 is a diagram for explaining an example of the contents of the order / predicted value memory in the embodiment of FIG.

FIG. 14 is a block diagram of a decoding device showing another embodiment of the present invention.

FIG. 15 is a diagram showing compression performance of encoded data according to another embodiment of the present invention and a conventional method.

[Fig. 16] Fig. 16 is a block configuration diagram of an encoding device according to another embodiment of the present invention.

FIG. 17 is a block diagram of a decoding device showing another embodiment of the present invention.

FIG. 18 is a block configuration diagram of an encoding device according to another embodiment of the present invention.

FIG. 19 is a diagram for explaining the coding principle in the embodiment of FIG.

[Fig. 20] Fig. 20 is a block configuration diagram of an encoding device according to another embodiment of the present invention.

FIG. 21 is a diagram illustrating operations of the level converter and the Huffman converter in the embodiment of FIG.

FIG. 22 is a block configuration diagram of an encoding device according to another embodiment of the present invention.

[Fig. 23] Fig. 23 is a block configuration diagram of a conventional encoding device.

FIG. 24 is a diagram showing a positional relationship between a pixel to be encoded and a reference pixel.

FIG. 25 is a diagram illustrating an example of the contents of a degree / predicted value memory according to a conventional technique.

[Fig. 26] Fig. 26 is a diagram illustrating an example of the correspondence between the degree of arithmetic coding and the region width.

[Explanation of symbols]

 1 Reference Symbol Creator 3 Degree / Prediction Value Memory Prediction Value 4 Multilevel Binary Converter 7 Arithmetic Encoder 8 Degree / Prediction Value Control Circuit 9 Reference Symbol Matching Detector 10 Reference Symbol Sorter 11 Specific Information Creator 12 Specific information encoder 14 Arithmetic decoder 15 Specific information decoder 17 Binary multi-value converter 18 Specific information inverse converter 19 Specific information multi-value binary converter 21 Specific information binary multi-value converter 60 Updater 61 Host 70 Block type binary encoder 80 Huffman encoder 90 Level converter 91, 92 Selector

Claims (9)

[Claims] 1. In a coding method for coding a coded symbol from a multi-valued Markov information source, attention is paid to a plurality of preceding symbols (reference symbols) having a predetermined positional relationship, and whether the reference symbols are equal to each other. An encoding method having means for detecting whether or not the Markov state is separated and encoded by this information. 2. The encoding method further comprises means for detecting the number of types of multi-valued levels occurring in a reference symbol, whereby Markov states are separated and encoded. The encoding system according to claim 1. 3. In the symbol coding in each Markov state, means for rearranging the symbols in a predetermined order after deleting symbols having overlapping levels in the reference symbols and the coded symbols are rearranged. The multi-valued binary conversion means for generating a signal indicating whether or not each symbol is equal to each other, and the means for sequentially encoding the same with a binary arithmetic code are provided, and the coded symbol becomes equal to the rearranged symbol. In this case, the coding process of the coded symbol is terminated by this arithmetic coding, and the coding system according to claim 1 or 2. 4. A means for generating information for specifying the level of the coded symbol when the level of the coded symbol does not occur in the reference symbol, and this information is used for the above 2
The encoding system according to claim 3, further comprising an encoding means for encoding separately from the value arithmetic code. 5. A means for generating a signal sequence having a level other than the level of the rearranged reference symbol after the rearranged reference symbol when the level of the encoded symbol does not occur in the reference symbol, and a code. And a multi-valued binary conversion means for generating whether or not the encoded symbol is equal to each level signal of this signal sequence, and the binary signal from this conversion means causes the level of the encoded symbol to occur in the reference symbol. The encoding method according to claim 3, wherein binary arithmetic encoding is performed by a method similar to that of the above. 6. A means for generating information of a necessary number of bits for specifying the level of the coded symbol when the level of the coded symbol does not occur in the reference symbol.
Patent is characterized in that it has means for selecting this specific information bit by bit and, following the signal from the multilevel binary conversion means, performs binary arithmetic coding of the specific information from this selection means bit by bit. The encoding system according to claim 3. 7. The method according to claim 1, further comprising means for updating the binary symbol appearance probability in the encoding for each step of each binary arithmetic encoding of each Markov state. The encoding method according to item 5 or item 6. 8. A means for generating a signal for identifying a binary symbol appearance probability for each step of each binary arithmetic coding of each Markov state is provided, and the appearance probability is calculated prior to the coding of the source symbol sequence. A signal for identifying is set in a memory, wherein the signals are set in a memory.
The encoding method described in the section. 9. In a coding method for coding a multi-level information source symbol, a level of a preceding symbol (reference symbol) having a predetermined positional relationship with the multi-level information source symbol and a level of the multi-level information source symbol are compared. And a conversion means for converting the level of the multilevel information source symbol based on the comparison result,
An encoding system comprising an encoding means for encoding the output converted by the converting means.