JPH0715304A - Pulse width modulation circuit - Google Patents

Abstract

PURPOSE:To obtain a pulse width modulation circuit in which radiation is effectively suppressed with a simple configuration while securing the S/N and a broad dynamic range. CONSTITUTION:The pulse width modulation circuit is provided with an integration circuit 10 integrating an input signal fed to an input terminal with respect to time, a comparator circuit 20 provided to an output of the circuit 10 and having a hysteresis characteristic, a feedback means 30 leading an output of the comparator circuit to an input of the integration circuit, and an amplitude modulation circuit 40 provided in a loop including the integration circuit and the comparator circuit and executing amplitude modulation so that an output of the comparator circuit is frequency-modulated. The output of the comparator circuit may be fed back to the integration circuit via the amplitude modulation circuit or the output of the integration circuit after it is amplitude-modulated by the amplitude modulation circuit may be given to the comparator circuit. A dither signal is given to the amplitude modulation circuit or a signal used to prevent decrease in the frequency of the obtained pulse width modulation signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulation (PWM) circuit for controlling the duty of an output pulse according to the amplitude of an analog input signal, and is particularly suitable for power amplification of a voice signal.

[0002]

2. Description of the Related Art Generally, a pulse width modulation circuit generally has an input terminal for receiving a signal to be pulse width modulated, an integration circuit having its input side connected to this input terminal, an input signal to the input terminal and an input terminal to be compared. Input signal to (output of integrating circuit)
A comparison circuit that has a hysteresis characteristic that outputs the comparison result with, an output terminal that is connected to the output side of this comparison circuit, and a feedback that returns the wave whose pulse width is modulated at this output terminal to the input side of the integration circuit. And a circuit.

In this circuit, when there is no input at the input terminal, the potential change of the integrating circuit capacitance due to the current on the feedback circuit is captured by the comparison circuit, and the direction of the current on the feedback circuit is determined by the polarity of the output of the comparison circuit. The oscillating operation of switching is monotonically repeated. The pulse oscillated at this time becomes a carrier. When an analog input signal is input to the input terminal, the rate of change in the potential of the integrating circuit capacitance is affected by the amplitude of the input signal, which changes the polarity inversion time of the comparison circuit output. That is, the duty of the output pulse signal is changed, which allows pulse width modulation according to the amplitude of the analog input signal.

In addition to the carrier self-oscillation method of such a modulation circuit, there is also a circuit of a method in which a pulse wave serving as a carrier signal is applied to an input terminal of an integration circuit from an oscillation circuit provided separately. By the way, in the conventional pulse width modulation circuit, if the amplitude of the signal at the integrated signal output terminal is increased, it is advantageous in that a high S / N ratio can be secured, that is, the comparison circuit is less likely to malfunction, but the dynamic range is increased. Becomes narrower and LSI
It is not suitable for reducing the voltage source voltage. Moreover, this circuit is disadvantageous because of its low operating speed.

On the contrary, if the amplitude of the signal appearing at the integrated signal output terminal is made small, a wide dynamic range can be secured, and it is advantageous for reducing the power supply voltage, but the high S
It is difficult to secure the / N ratio, that is, the comparison circuit easily malfunctions. Furthermore, when the amplitude of the signal at the integrated signal output terminal is small, that is, when the hysteresis width of the comparison circuit is small, the comparison circuit is likely to malfunction due to noise.

Further, the hysteresis width of the comparison circuit can be changed by the dither signal, but in the conventional pulse modulation circuit, the output level of the integration circuit fluctuates according to the level of the dither signal, so that the S / N ratio and There was a problem that both of the dynamic range were kept low.

Further, in the conventional pulse width modulation circuit, there is a problem that the fundamental wave and harmonic components of the pulse wave which becomes the carrier signal adversely affect radio equipment such as radio as unnecessary radiation (radiation). It was

[0008]

In order to prevent unnecessary radiation, it is necessary to cover the printed circuit board and the entire device with a metal shield plate, but this causes another problem that the size is increased and the cost is increased. Invite.

One proposal for performing two-state modulation is also disclosed in European patent application 85303763.8, published specification 0184280A1. The circuit shown here allows the width of the hysteresis of the comparator to be varied to increase frequency stability. However, this has a drawback that it is likely to cause a malfunction.

The present invention has been made to solve the above problems, and an object thereof is to effectively suppress the radiation with a simple structure while securing a wide S / N ratio and a wide dynamic range. It is to provide a pulse width modulation circuit capable of performing.

[0011]

According to the pulse width modulation circuit of the first invention, an input terminal, an integrating circuit for integrating an input signal supplied to the input terminal with respect to time,
The output signal of the integrating circuit is
Comparator having a threshold value and a second threshold value, an output terminal connected to the output of the comparator circuit, feedback means for guiding the output of the comparator circuit to the input of the integrator circuit, and the integration circuit. Provided in a loop including a circuit and the comparison circuit,
And an amplitude modulation circuit for performing amplitude modulation so that the output of the comparison circuit is frequency-modulated.

Further, according to the pulse modulation circuit of the second invention, an input terminal, an integrating circuit for integrating the input signal supplied to the input terminal with respect to time, and an output of the integrating circuit are connected, A comparison circuit that compares the output of the integration circuit with a first threshold value and a second threshold value, an output terminal connected to the output of the comparison circuit, and an output of the comparison circuit to the input of the integration circuit. First feedback means for guiding, an amplitude modulation circuit for amplitude-modulating the output of the comparison circuit, an output of the comparison circuit to the amplitude modulation circuit, and an output of the amplitude modulation circuit to an input of the integration circuit And two return means.

Further, according to the pulse modulation circuit of the third invention, an input terminal, an integrating circuit for integrating the input signal supplied to the input terminal with respect to time, and an output of this integrating circuit are connected, An amplitude modulation circuit that performs amplitude modulation of the integrator output, and is connected to the output of the amplitude modulation circuit,
A comparison circuit for comparing the output of the amplitude modulation circuit with a first threshold value and a second threshold value, an output terminal connected to the output of the comparison circuit, and an output of the comparison circuit for the integration circuit. And a feedback means for leading to the input.

[0014]

The integrated circuit for integrating the input signal supplied to the input terminal with respect to time, the comparator circuit having the hysteresis characteristic connected thereto, and the loop formed by the feedback means for guiding the output of the comparator circuit to the input of the integrator circuit are provided. In addition to this, an amplitude modulation circuit that performs amplitude modulation so that the output of the comparison circuit is frequency-modulated is provided in the loop that includes the integration circuit and the comparison circuit. Is suppressed. At this time, the S / N ratio and the dynamic range are maintained.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. In addition, the same reference numerals are given to corresponding parts.

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention. In this pulse width modulation circuit, the signal input to the input terminal 1 is input to the integration circuit 10 via the input resistor 2.
The output of the integration circuit 10 is input to the comparison circuit 20, the output is taken out from the output terminal 5, and is fed back to the input side of the integration circuit 10 via the feedback circuit 30. The output of the comparison circuit 10 is input to the amplitude modulation circuit 40 together with the dither signal from the dither signal input terminal 6, and is fed back to the input side of the integration circuit 10 via the resistor 9.

FIG. 2 is a circuit diagram showing in detail the configuration shown in FIG. In the figure, one end of an input resistor 2 is connected to the signal input terminal 1. The other end of the input resistor 2 is connected to the inverting input terminal (-) of the operational amplifier 11. This operational amplifier 11 constitutes an integrating circuit 10 together with the capacitor 12, one end of the capacitor 12 is connected to the inverting input terminal of the operational amplifier 11, and the other end is connected to the output terminal of the operational amplifier 11. A voltage source (not shown) for applying the reference voltage VREF1 is connected to the non-inverting input terminal (+) of the operational amplifier 11, and the output terminal of the operational amplifier 11 is connected to the integral signal output terminal 13.

The inverting input terminal of the operational amplifier 21 is connected to the output terminal of the operational amplifier 11. The operational amplifier 21 constitutes the comparison circuit 20 together with the resistors 22 and 23. Of these, one end of the resistor 22 is connected to the output terminal of the operational amplifier 21, and the other end is connected to the non-inverting input terminal of the operational amplifier 21. Further, one end of the resistor 23 is connected to the other end of the resistor 22, and a voltage source (not shown) for applying the reference voltage VREF2 is connected to the other end of the resistor 23. The output terminal of the operational amplifier 21 is connected to the comparison signal output terminal 24.

The output terminal of the operational amplifier 21 is connected to the input terminal of the inverter 3. The output terminal of the inverter 3 is connected to the inverting input terminal of the operational amplifier 11 via the resistor 4 as a feedback element of the feedback circuit 30. And is directly connected to the PWM signal output terminal 5.

The PWM signal output terminal 5 is connected to one side input terminal 7 of the amplitude modulation circuit 40, and the other side terminal is a dither input terminal 6. An amplitude modulation signal output terminal 8 is provided on the output side of the amplitude modulation circuit 40, and the amplitude modulation signal output terminal 8 is connected to one end of a feedback resistor 9. The other end of the feedback resistor 9 is connected to the operational amplifier 11
Is connected to the inverting input terminal 14.

Next, the operation of this circuit will be described. First,
In order to facilitate understanding, point P shown in FIG. 1, that is, the feedback resistor 9 and the inverting input terminal 14 of the operational amplifier 11 is used.
Consider the case where the space between and is separated. It is assumed that the signal input terminal 1 is open and the potential of the PWM signal output terminal 5 is Vo. Also, reference voltages VREF1 and V
It is assumed that REF2 is kept at the ground potential. At this time, the potential of the input terminal of the inverter 3, that is, the potential of the output terminal of the comparison circuit 20 is -Vo. Therefore, if the resistance value of the resistor 22 is R2 and the resistance value of the resistor 23 is R3, the potential Vp of the non-inverting input terminal of the operational amplifier 21 becomes the value shown in the following equation. Vp = -R3.Vo / (R2 + R3) (1)

On the other hand, if the resistance value of the resistor 4 is R1,
The current I shown in the following equation flows into the capacitor 12. I = Vo / R1 (2)

When the current I flows into the capacitor 12, the output terminal potential of the operational amplifier 11, that is, the output terminal potential of the integrating circuit 10 drops. When the output terminal potential of the integrating circuit 10 becomes lower than the potential Vp of the non-inverting input terminal of the operational amplifier 21, the output terminal potential of the operational amplifier 21 becomes Vo.
And the potential of the PWM signal output terminal 5 is inverted to -Vo. At the same time, the operational amplifier 2
The potential Vp of the non-inverting input terminal of 1 has a value shown in the following equation. Vp = R3.Vo / (R2 + R3) (3)

As described above, when the output state of the operational amplifier 21 is inverted, the current I shown in the following equation is applied to the capacitor 12
Flow into. I = -Vo / R1 (4)

Therefore, contrary to the above, the output terminal potential of the operational amplifier 11, that is, the output terminal potential of the integrating circuit 10 rises. Then, when the output terminal potential of the integrating circuit 10 reaches the potential Vp of the non-inverting input terminal of the operational amplifier 21, the output terminal potential of this operational amplifier 21 is inverted to -Vo, and accordingly the PWM signal output terminal 5 is inverted. Potential is V
flip to o.

The operation described above is repeated, the circuit oscillates, the square wave signal shown in FIG. 3 (a) is output to the PWM signal output terminal 5, and the integrated signal output terminal 13 is shown in FIG. 3 (b).
The triangular wave signal shown in is output.

The oscillation frequency f of this PWM basic circuit is determined by the following equation, where C1 is the capacitance of the capacitor 12. f = (R2 + R3) / (4.C1.R1.R3) (5)

Next, the signal shown in FIG. 4A is applied to the signal input terminal 1, that is, the reference voltage VRE as time passes.
Consider the case where a signal that changes above and below F1 is applied. Here, when the potential of the signal input terminal 1 is lower than the reference voltage VREF1, the rate of fall of the potential of the integrated signal output terminal 13 is slow and the rate of rise thereof is fast. On the contrary, when the potential of the signal input terminal 1 is higher than the reference voltage VREF1, the speed of the fall of the potential of the integrated signal output terminal 13 becomes faster,
The speed of ascending slows down. Therefore, the integrated signal output terminal 1
The potential of 3 changes as shown in FIG. 4 (b), whereby the potential of the PWM signal output terminal 5 has a PWM waveform as shown in FIG. 4 (c).

Further, the square wave signal shown in FIG. 5B, which appears at the PWM signal output terminal 5, is applied to the amplitude modulation circuit 40 via the pulse signal input terminal 7. Then, when the signal shown in FIG. 5A is applied to the dither signal input terminal 6 of the amplitude modulation circuit 40, the square wave signal is amplitude-modulated by the dither signal, and the signal shown in FIG. 5C is obtained. At this time,
The signal shown in FIG. 5D appears at the integrated signal output terminal 13.

Next, the amplitude modulation signal output terminal 8 is connected via the feedback resistor 9 to the integrating circuit 1 without disconnecting point P.
The case of being connected to the inverting input terminal of the operational amplifier 11 in 0 will be described with reference to FIGS. In this case, since the signal appearing at the PWM signal output terminal 5 is amplitude-modulated by the dither signal shown in FIG.
The signal shown in (b) appears at the amplitude modulation signal output terminal 8. This signal is applied to the inverting input terminal of the operational amplifier 11 via the feedback resistor 9.

In this operation, when the amplitude modulation signal level is positive, the falling edge of the output voltage waveform of the integrating circuit becomes faster as the waveform amplitude increases, and conversely, when the amplitude modulation signal level is negative, the waveform amplitude decreases. The larger the value, the faster the rising edge of the output voltage waveform of the integrating circuit. That is,
The output signal frequency of the integrating circuit 10 changes in proportion to the amplitude of the dither signal. Therefore, when the signal shown in FIG. 6B is applied to the integrating circuit 10, the signal shown in FIG. 6C appears at the integrated signal output terminal 13. As a result, FIG.
As shown in (d), the PWM signal is the PWM signal output terminal 5
Appear in. The amplitude modulation circuit 40 outputs the signal shown in FIG. 6B described above by amplitude-modulating the signal shown in FIG. 6D. As a result, the frequency spectrum of the PWM signal can be dispersed while keeping the amplitude of the output signal of the integrating circuit 10 constant. As described above, as a result of frequency modulation, unnecessary radiation can be prevented.

FIG. 7 is a circuit diagram showing the configuration of another embodiment of the present invention. In FIG. 7, the same reference numerals as those in FIGS. 1 and 2 denote the same elements. In this, the output terminal of the comparison circuit 20 is connected to the input terminal of the buffer 3A, and the output terminal of the buffer 3A is connected to the PWM signal output terminal 5A. Further, one end of the resistor 4A is connected to the PWM signal output terminal 5A and the other end is connected to the operational amplifier 11
It is connected to the non-inverting input terminal of. And resistor 4A
The other end is connected to one end of the capacitor 12A, and the other end of the capacitor 12A is connected to a voltage source (not shown) for applying the reference voltage VREF1. Furthermore, one end of the resistor 2A is connected to the other end of the resistor 4A, and a voltage source (not shown) for applying the reference voltage VREF3 is connected to the other end.

The amplitude modulation circuit 40 in this embodiment is P
It is composed of NP type transistors 41 and 42 and NPN type transistors 43 and 44. Here, the emitters of the transistors 41 and 42 are connected to each other, and
It is connected to the current input type dither signal input terminal 6.
Further, a voltage source (not shown) for applying the reference voltage VREF4 is connected to the base of the transistor 41, and the transistor 4
The base of 2 is a pulse signal input terminal 7, and this terminal is connected to the PWM signal output terminal 5. on the other hand,
The collector of the transistor 43 is the collector of the transistor 41, and the collector of the transistor 44 is the transistor 4
It is connected to each of the two collectors. The bases of the transistors 43 and 44 are connected to each other,
It is connected to the collector of the transistor 44, and the emitters of the transistors 43 and 44 are commonly connected to the ground point GND. The collector of the transistor 43 serves as the amplitude modulation signal output terminal 8 and is connected to the inverting input terminal 14 of the integrating circuit 10.

In this amplitude modulation circuit, a differential amplifier circuit is formed by the transistors 41 and 42, a substantially constant current is made to flow through the transistor 41, and a dither signal current is made to flow from the dither signal input terminal 6 The current flowing through 42 is amplitude-modulated. The transistors 43 and 44 form an active load circuit and change the collector current of the transistor 43 having a high output impedance in response to the amplitude modulation signal, thereby causing a current to flow to the inverting input terminal of the operational amplifier 11. As a result, the amplitude modulation signal can be superimposed on the input signal. In this case, the value of the current flowing through the inverting input terminal of the operational amplifier 11 can be appropriately set inside the amplitude modulation circuit 40, so that the feedback resistor 9 shown in FIGS. 1 and 2 can be omitted. .

Next, the operation of the circuit shown in FIG. 7 will be described. This circuit takes out a PWM signal having a polarity opposite to that of the PWM signal output terminal 5 from the PWM signal output terminal 5A via the buffer 3A. Then, the signal generated at the PWM signal output terminal 5A is passed through the CR circuit including the resistors 2A, 4A and the capacitor 12AA to the operational amplifier 1
Negative feedback is applied to the 1's non-inverting input terminal. With this configuration, negative feedback of BTL (balanced transformless) is performed between the integrating circuit 10 and the comparing circuit 20.

As a result, by adopting BTL,
Output can be increased for the same power supply voltage, and PW
It is possible to reduce the distortion of the audio signal component included in the M output signal.

By the way, the output signal level of the amplitude modulation circuit in each of the above-mentioned embodiments should be appropriately determined in consideration of the input signal level applied to the signal input terminal 1. However, even if the output signal level of the amplitude modulation circuit is held at a constant value, if the input signal level falls below the normal value, the output signal level of the amplitude modulation circuit becomes much higher than the input signal level. There are cases.

As described above, when the output signal level of the amplitude modulation circuit becomes much higher than the input signal level, the input signal component added to the signal input terminal 1 in the PWM output signal appearing at the signal output terminal 5 is small, The output signal component of the amplitude modulation circuit increases. As a result, the input signal component may be masked by the output signal component of the amplitude modulation circuit, and only the output signal component of the amplitude modulation circuit may appear in the PWM output signal of the signal output terminal 5.

FIG. 8 is a block diagram showing the construction of another embodiment for positively preventing this situation. In the figure, the same reference numerals as those in FIG. 2 or 7 denote the same elements. Here, the PWM that appears at the signal output terminal 5
The switch circuit 51 has a signal as one input and a dither signal applied to the dither signal input terminal 6 as the other input. A switch circuit in which a signal obtained by inverting the PWM signal appearing at the signal output terminal 5 by the inverter 52 is used as one input, and a signal obtained by inverting the level of the dither signal applied at the dither signal input terminal 6 is used as the other input. 54. These switch circuits take out the PWM signal within a range not exceeding the level of the dither signal.

Further, the input signal applied to the signal input terminal 1 is applied to one terminal of the multiplier 55, and the dither signal selected by the switch circuit 51 is applied to the other terminal, and similarly applied to the signal input terminal 1. The input signal thus obtained is applied to the inverting input terminal on one side of the multiplier 56, and the inverted dither signal selected by the switch circuit 54 is applied to the other terminal.
The output signals of these multipliers are resistors 57 and 5 respectively.
It is superposed on the input signal at the input side of the operational amplifier 11 via 8.

The operation of this embodiment will be described below with reference to FIGS.
This will be described with reference to (h). First, it is assumed that the resistors 57 and 58 and the inverting input terminal of the operational amplifier 11 are separated from each other and no dither signal component is added. Then, as shown by the solid line in FIG. 9A, the signal input terminal 1
When the level of is gradually increased, the PWM signal whose pulse width is gradually narrowed as shown in FIG.
Appear in.

When the PWM signal shown in FIG. 9 (h) and the dither signal shown in FIG. 9 (b) applied to the dither signal input terminal 6 are applied to the switch circuit 51, the positive direction of the PWM signal is detected. A signal shown in FIG. 9C whose level is limited by the dither signal is output. On the other hand, the inverting amplifier 5
3 inverts the input level with respect to the reference signal and outputs it, and the inverter 52 inverts the polarity of the PWM signal and outputs it.
When each of these inversion signals is applied to the switch circuit 54, as shown in FIG. 9D, the portion corresponding to "1" of the PWM signal waveform is "0" and the portion corresponding to "0" of the PWM signal waveform. The corresponding portion is output as a negative value limited by the dither signal magnitude.

Therefore, the multiplier 55 multiplies the signal shown in FIG. 9C by the signal shown in FIG. 9A and outputs the signal shown in FIG. 9E. Further, the multiplier 56 multiplies the signal shown in FIG. 9D by the signal shown in FIG.
The signal shown in (f) is output.

Next, the resistor 57,
If 58 is connected to the inverting input terminal of the operational amplifier 11, the signals output from the multipliers 55 and 56 are combined via the resistors 57 and 58, respectively, and the result is shown in FIG. The current signal shown is applied to the inverting input terminal of operational amplifier 11. When the current signal shown in FIG. 9 (g) is applied to the inverting input terminal of the operational amplifier 11,
The signal waveforms of (a) -9 (c) also change, but the description is omitted for simplification.

The signal shown in FIG. 9 (g) superimposed on the input signal in this manner corresponds to the signal shown in FIG. 5 (c), but the envelope of the signal shown in FIG. 9 (g). Is proportional to the signal level of the signal input terminal 1, whereas the level of the signal envelope shown in FIG. 5C does not change even if the input signal level of the signal input terminal 1 changes. Be different.

As described above, according to the embodiment shown in FIG. 8, it is possible to prevent the situation where the output signal level of the amplitude modulation circuit becomes much higher than the input signal level, and it is possible to prevent radiation. There is an effect that the suppression and the prevention of the malfunction of the comparison circuit due to the noise are further ensured.

FIG. 10 is a circuit diagram showing a concrete circuit configuration example for the embodiment shown in FIG. 61 to 6 in the figure
5, 68 and 69 are PNP transistors, and 66 and 67 are NPN transistors. Here, the transistor 61
Each of the emitters 63 to 63 is commonly connected to a positive reference voltage source (not shown). The collector of the transistor 61 is connected to the dither signal input terminal 6, and the transistors 61 to 61 are connected.
The bases of 63 are commonly connected to the collector of the transistor 61.

The emitters of the transistors 64 and 65 are connected to the collector of the transistor 62,
Of these, the base of the transistor 64 is the signal output terminal 5
The base of the transistor 65 is connected to a voltage source that generates an intermediate voltage with respect to the reference voltage, and the collector thereof is connected to the ground point.

The emitters of the transistors 66 and 67 are connected to the ground point, and the transistors 66 and 6 are connected to the ground point.
The bases of 7 are commonly connected to the collector of the transistor 66 and the collector of the transistor 64. The collector of the transistor 67 is connected to the reference voltage source via the resistor and is also connected to the input terminal of the multiplier 56.

Further, the emitters of the transistors 68 and 69 are commonly connected to the collector of the transistor 63, of which the base of the transistor 68 is connected to the signal output terminal 5 and the collector thereof is connected to the ground point. The base of the transistor 69 is connected to a voltage source that generates an intermediate voltage with respect to the reference voltage, and its collector is connected to the reference voltage source via a resistor and the multiplier 5
5 is connected to the input terminal.

In FIG. 10, transistors 61 to 61
63 constitutes a current mirror circuit, and when a dither signal is applied to the dither signal input terminal 6, the same current as the transistor 61 flows through the transistors 62 and 63. The transistors 68 and 69 form a differential amplifier circuit, which supplies a current passing through the transistor 63 to the transistor 6 and
By applying the PWM signal of the signal output terminal 5 to the base of 8, the amplitude modulation signal shown in FIG. 9C is obtained from the collector of the transistor 69. Similarly, transistor 6
4 and 65 also constitute a differential amplifier circuit, a current passing through the transistor 62 is supplied to the differential amplifier circuit, and the PWM signal of the signal output terminal 5 is added to the base of the transistor 64, whereby a PWM signal with a level inverted is obtained. The transistors 66 and 67 form an inverting amplifier circuit, and by applying this PWM signal to the collector of the transistor 66 connected to each base, the amplitude modulation signal shown in FIG. 9D is obtained from the collector of the transistor 67.

Of these, the amplitude modulation signal obtained from the collector of the transistor 69 is multiplied by the input signal by the multiplier 55, and the amplitude modulation signal obtained from the collector of the transistor 67 is inverted by the multiplier 56. It is multiplied with the signal. In this way, the operation described with reference to FIG. 8 can be performed by the circuit configuration of FIG.

Although the PWM signal output from the comparison circuit is amplitude-modulated by the dither signal as it is in each of the above-described embodiments, a signal whose frequency is proportional to the PWM signal output from the comparison circuit can be used. Of course, the frequency spectrum can be dispersed in the same manner as described above by using a pulse signal having a frequency equivalent to this, without using the PWM signal output from the comparison circuit.

Further, in each of the above embodiments, the voltage comparison type comparison circuit is used, but it goes without saying that a current comparison type comparison circuit may be used instead. Further, instead of the voltage comparison circuit, an amplifier may be used to have the same function as described above.

By the way, in each of the above-mentioned embodiments,
Although the explanation has been given on the premise that the PWM signal is taken out from the PWM signal output terminal 5, it is obvious that the present invention can be applied to the generation of the frequency modulation signal corresponding to the input signal from the integration signal output terminal.

As is clear from the above description, FIG.
According to the embodiment of FIG. 10, according to the dither signal,
Since the frequency spectrum of the PWM signal is dispersed by performing frequency modulation while keeping the amplitude of the output signal of the integrator constant, the radiation is suppressed without affecting both the S / N ratio and the dynamic range. You can Further, it is possible to prevent malfunction of the comparison circuit which is likely to occur due to noise when the amplitude of the output of the integration circuit is small. In this case, the circuit configuration can be simplified by using a signal proportional to the output signal of the comparison circuit as the amplitude-modulated signal.

Next, another application example of the configuration of FIG. 1 will be described. A pulse width modulation circuit (PWM circuit) is often used to drive a low impedance load such as an acoustic speaker or a motor. For this reason, it is necessary to power-amplify the PWM signal output with a power driver circuit having a capability of sufficiently driving a load. At this time, if an element such as a power MOSFET is used in the power driver circuit,
The distortion rate of the audio signal obtained due to the characteristics of the element itself (the rounding of the rising and falling characteristics) deteriorates.

FIG. 11 is a circuit diagram based on the circuit shown in FIG. 2, in which a power driver circuit 70 is inserted between the comparison circuit 20 and the signal output terminal 5, and the signal output terminal 5 is out of the voice band. Low-pass filter 80 for removing components
The configuration is the same as that of FIG. 2 except that the speaker 81 is connected. This power driver circuit is shown in FIG.
As shown in, by including it in the signal loop of the pulse width modulation circuit, it is possible to prevent the distortion rate of the audio signal from being deteriorated by the distortion of the power driver circuit.

FIG. 12 is a circuit diagram showing an embodiment in which a power driver circuit is added to the embodiment shown in FIG. In this embodiment, the inverter 3 has a power driver circuit 70.
However, the power driver 70A is connected to the buffer 3A, and the coils L1 and L2 of the low-pass filter 80 are connected to the respective signal output points, and the other configurations are the same as those in FIG.

FIG. 13 is a circuit diagram showing the structure of an example of the power driver circuit. The output terminal 73 of the inverting pre-driver circuit 72 connected to the input terminal 71 has a P-channel power MOSFET Q1 and an N-channel power MOSFE.
It is connected to the gate common connection point of T Q2, and these drain common connection points are output terminals 74.

In this circuit, when the input terminal 71 is at L level, the output terminal 73 of the inverting predriver circuit 72 is at H level, and the gates of both power MOSFETs are also at H level, so that the transistor Q1 is turned off and the transistor Q2 is turned on. Turn on. At this time, the output terminal 74 is connected to GND via the drain-source resistance (approximately 0Ω) of the transistor Q2. At this time, the resistance between the drain and the source of Q1, which is OFF, is almost infinite. On the other hand, when the input terminal 71 is at H level, the output terminal 73 of the inverting predriver circuit 72 is at L level,
Since the gates of both power MOSFETs Q1 and Q2 are also at the L level, the transistor Q1 turns on and the transistor Q2 turns off. Therefore, the output terminal is connected to VCC through the drain-source resistance (approximately 0Ω) of Q1. At this time, Q2 is OFF
The drain-source resistance of is almost infinite.

As described above, in the power driver circuit of FIG. 13, when the input terminal is at the L level, the output terminal is at the L level, and when the input terminal is at the H level, the output terminal is also at the H level, and the load connected to the output terminal ( Drive current is supplied to the speaker. Further, the inverting pre-driver circuit is provided in order to make the input and output polarities the same as those of the power driver circuit shown in FIGS.

FIG. 14 is a circuit diagram showing another example of the power driver circuit, in which two N-channel power MOSFEs are used.
This is an example using T. The gate of the N-channel power MOSFET Q2 and the input terminal of the inverting predriver circuit 72 are connected to the input terminal 71, and the inverting predriver circuit 7 is connected.
The second output terminal 73 is an N-channel power MOSFET Q3.
The gate of is connected. The source of the transistor Q2 and the drain of Q3 are commonly connected to form an output terminal 74. The drain of the transistor Q2 is connected to the power supply Vcc, and the source of the transistor Q3 is grounded.

In this circuit, when the input terminal 71 is at the H level, the output terminal 73 of the inverting predriver circuit 72 is at the L level and the gate of the transistor Q3 is also at the L level, so that this transistor is turned off. At this time, since the gate of the transistor Q2 is at H level, this transistor is turned on. In this state, the output terminal 74 is connected to VCC via the drain-source resistance (~ 0Ω) of Q2. On the other hand, the drain-source resistance of Q3 which is OFF is almost infinite.

When the input terminal 71 is at the L level, the output terminal 73 of the inverting predriver circuit 72 is at the H level and the gate of the transistor Q3 is also at the H level, so that this transistor is turned on. At this time, the transistor Q2
Since the gate of is at L level, this transistor is turned off. In this state, the output terminal 74 is connected to GND via the drain-source resistance (~ 0Ω) of Q3. On the other hand, the transistor Q2 that is off
The drain-source resistance of is almost infinite.

As described above, in the power driver circuit of FIG. 14, when the input terminal is at the L level, the output terminal is also at the L level, and when the input terminal is at the H level, the output terminal is also at the H level, and the load (speaker) connected to the output terminal. Drive current is supplied to.

Next, another embodiment in which the dither input of FIG. 1 is used for different purposes will be described. In the embodiment described above, as shown in FIG. 6A, a triangular wave signal is shown as an example of the waveform of the dither signal input terminal applied signal. This is a measure against radiation by using a low-frequency signal of, for example, about 20 Hz as a triangular wave signal, and encouraging the PWM output terminal waveform to be frequency-modulated in proportion to the triangular wave signal. On the other hand, in the following embodiment, the dither signal input is used for frequency correction of the PWM output signal waveform, which is different from the radiation countermeasure.

In the circuit shown in FIG. 2, the amplitude modulation circuit 40
In the case of a configuration lacking a feedback loop including this, as the amplitude of the input signal applied to the signal input terminal 1 increases,
There is a drawback that the frequency of the output signal of the PWM circuit becomes low. That is, as shown by the solid line in FIG. 15, the frequency of the output signal (pulse wave) of the PWM circuit is highest when the duty ratio is 0.5 which corresponds to the case where there is no input signal (200 kHz in this example). The frequency of the output signal of the PWM circuit becomes lower as the duty ratio approaches 0 or 1.0.

Here, the duty ratio is expressed as T1 / (T1 + T2) (6) using the times T1 and T2 during which the H level and the L level of the PWM output signal waveform continue, as shown in FIG. . The oscillation frequency f is expressed as f = 4 * (T1 / (T1 + T2) * (1-T1 / (T1 + T2)) * 200 kHz (7).

An amplitude modulation circuit according to the duty ratio of the PWM output signal, that is, the amplitude of the input signal applied to the signal input terminal, as indicated by the broken line in FIG. 15, is applied to the dither input terminal in the circuit shown in FIG. By inputting the correction signal corresponding to the magnification of (the slope of the triangular wave),
The decrease in the frequency of the output signal of the M circuit is offset and can be corrected.

FIG. 17 is a circuit diagram showing the configuration of a circuit which can approximately obtain this correction signal. When a signal similar to the input signal applied to the signal input terminal of FIG. 2 is applied to the correction circuit input terminal 91, the peak detection circuit 92 detects the amplitude of the input signal. The outputs of the peak detection circuit 92 are given to the comparators 93 to 95, respectively.

The comparators 93 to 95 respectively use different threshold voltages Va, Vb, V as comparison inputs.
c is input, and the switch amplifiers 96 to 99 are controlled according to the amplitude by the comparison output with these. Then, the addition result of these outputs by the addition circuit 99 is taken out from the correction circuit output terminal 100. For example, when the amplitude is small, all the switch amplifiers are turned off.
6. Since the switch amplifier 97 and the switch amplifier 98 are turned on, the input voltages V1 and V of these switch amplifiers are
By appropriately selecting 2, V3, it is possible to generate a signal having the magnification shown by the broken line in FIG. 15 at the correction circuit output terminal.

FIG. 18 is a block diagram showing a schematic configuration of a pulse width modulation circuit according to another aspect of the present invention. According to the figure, in this pulse width modulation circuit, the signal input to the input terminal 1 is applied to the integration circuit 10, and the output of the integration circuit 10 is input to the comparison circuit 20 via the amplitude modulation circuit 40, The output is taken from the output terminal 5,
It is fed back to the input side of the integrating circuit 10 via the circuit 30. The dither signal is applied to the dither signal input terminal 6 of the amplitude / amplitude modulation circuit 40. In this embodiment as well, a frequency correction signal may be given to the terminal 6.

FIG. 19 is a block diagram showing almost the same mode as that of FIG. 18. The difference from FIG. 18 is that the dither signal supplied to the amplitude modulation circuit 40 is the dither signal generation circuit 11.
The point is that it is generated at 0. The dither signal generation circuit 110 outputs a dither signal, and the amplitude modulation circuit 40 amplitude-modulates the output signal of the integration circuit 10 by the dither signal. The comparison circuit 20 is shown as an operational amplifier having a hysteresis characteristic, and the output signal of the amplitude modulation circuit 40 is input to its inverting input terminal. Then, this comparison circuit 20
Is output from the output terminal 5 and fed back to the input side of the integrating circuit 10 by the feedback circuit 30.

FIG. 20 is a circuit diagram showing a specific example of the circuit shown in FIG. In this figure, the same components as in FIG. 2 are given the same reference numbers. In the figure, one end of an input resistor 2 is connected to the signal input terminal 1. The other end of the input resistor 2 is connected to the inverting input terminal (-) of the operational amplifier 11. This operational amplifier 11 constitutes an integrating circuit 10 together with the capacitor 12, one end of the capacitor 12 is connected to the inverting input terminal of the operational amplifier 11, and the other end is connected to the output terminal of the operational amplifier 11. Then, a voltage source (not shown) for applying the reference voltage VREF1 is connected to the non-inverting input terminal (+) of the operational amplifier 11, the output of the operational amplifier 11 is input to the multiplication circuit 45, and the output of the operational amplifier 20. It is input to the inverting input terminal.
The output of the operational amplifier 20 is taken out from the output terminal 5 and is also fed back to the inverting input terminal of the operational amplifier 11 of the integrating circuit via the resistor 4 which is a feedback element of the feedback circuit 30.

The signal applied to the input terminal 1 is applied to the peak detection circuit 111, and its output is the dither oscillation circuit 1
The output of 12 is added by the adder circuit 27. Then, this addition output is given to the multiplication circuit 45, and this multiplication circuit 45 amplitude-modulates the output signal of the operational amplifier 11 using the output signal of the addition circuit 113 as a modulation wave.

Next, the operation of this circuit will be described. In the state where there is no analog wave input at the input terminal 1, the comparison circuit 20 captures the potential change of the integrating capacitance element 12 due to the current flowing through the feedback circuit 30. That is, the feedback circuit 30
The current flowing through the capacitor flows into the capacitive element 12, and the output potential of the integrating circuit 11 decreases, and the state continues until the output potential of the comparing circuit 20 becomes equal to or lower than the reference potential. When the output potential of the integrating circuit 10 becomes equal to or lower than the reference potential, the capacitive element 1
2 is discharged, the direction of the current of the feedback circuit 30 is switched, the output potential of the integration circuit 10 rises, and the state continues until the reference potential of the comparison circuit 20 is exceeded. After that, when the output potential of the integration circuit 10 exceeds the reference potential of the comparison circuit 20, the integration capacitance element 12 returns to the discharge state. As a result of such operations being monotonically repeated, the pulse signal having a constant duty is output from the comparison circuit 20. This pulse signal becomes a carrier signal.

When an analog signal is input to the input terminal 1, the integration capacitance element 12 is changed by the input signal amplitude.
The rate of change in the potential of is affected. That is, the input terminal 1
When the potential of is lower than the reference potential of the comparison circuit 20, the output potential drop rate of the integration circuit 20 is slow and the output potential rise rate is fast. In addition, the potential of the input terminal 1 is the comparison circuit 2
When it is higher than the reference potential of 0, the output potential drop speed of the integrating circuit 20 is fast and the output potential rise speed is slow.

This situation will be described with reference to FIGS. 21 (a) to 21 (d). When an analog signal as shown in FIG. 21 (a) is input to the input terminal 1, the output of the integrating circuit 10 becomes that shown in FIG. 21 (b). On the other hand, the peak of the input signal and the tether input signal are added, and the output of the integrating circuit 10 is limited by the waveform of the amplitude modulation wave shown by the broken line in FIG. Therefore, the output of the multiplication circuit 45 is amplitude-modulated into a waveform as shown by the solid line in FIG.

This amplitude-modulated output is input to the comparator 20, so that the output signal is spread with the spectrum components of the fundamental wave and the harmonics of the carrier signal according to its hysteresis characteristic, and the output signal is shown in FIG. The frequency is modulated as shown. In this way, the output of the integrator circuit 10 is frequency-modulated by applying a signal whose amplitude is modulated by the dither and the input peak to the comparison circuit 20, so that the fundamental wave and harmonic spectrum components of the modulated wave are spread, Unnecessary radiation due to those components can be suppressed. Since the peak levels of the fundamental wave and harmonic spectrum components can be lowered, the adverse effect of the fundamental wave and harmonic spectrum components of the output of the integrating circuit can be suppressed.

In this embodiment, the structure for performing amplitude modulation is provided inside the signal loop, but it may be provided outside the loop. FIG. 22 is a block diagram showing such an example.
A loop composed of the integrating circuit 10, the comparing circuit 20, and the resistor 4 is formed, and the voltage controlled oscillator 1 is provided between the input resistor 2 connected to the input terminal 1 and the input end of the integrating circuit 10.
Twenty outputs are provided. The voltage controlled oscillator 120 is controlled by the control circuit 130.

FIG. 23 specifically shows the structure of FIG. The integrating circuit 10 has the operational amplifier 11 and the comparing circuit 20 has the operational amplifier 21 as in the above-described embodiments. However, the operational amplifier 21
Does not necessarily have hysteresis characteristics.
Further, the voltage controlled oscillator 120 is a VCO 121, and applies a pulse signal having a frequency according to the voltage applied to the control input terminal to the input terminal of the integrating circuit 41 as a carrier signal. The control circuit 130 supplies a voltage signal for controlling the output frequency to the control input terminal of the voltage controlled oscillator 120, and is a dither oscillation circuit 131 here. The carrier signal output from the VCO 121 is frequency-modulated by this dither signal.

By frequency modulation of the carrier signal given to the integrating circuit 10, the peak levels of the spectrum components of the fundamental wave and the harmonics in the output of the integrating circuit 10 can be lowered, so that the fundamental wave and the harmonics of the output of the integrating circuit 10 can be reduced. It is possible to suppress the adverse effect of the wave spectrum component and the adverse effect of the large amplitude input.

In particular, the frequency modulation operation is performed based on the carrier signal generated from the outside of the feedback loop and is independent of the output of the comparison circuit 20, so that the stable operation is not affected by the modulated wave. Is obtained.

FIG. 24 is a circuit diagram showing a modification of the circuit shown in FIG. 23. In the circuit shown in FIG.
As the second control circuit for 1, the peak detection circuit 140 for inputting the signal of the input terminal 1 and detecting the peak thereof is provided. With this configuration, the fundamental wave and the harmonic spectrum of the carrier signal can be variably controlled according to the signal level to the input terminal 1, and a better countermeasure against a large amplitude can be taken.

[0086]

As described above, according to the present invention, the integrating circuit for integrating the input signal with respect to time, the comparing circuit having the hysteresis characteristic, and the feedback means for guiding the output of the comparing circuit to the input of the integrating circuit. Since the amplitude modulation circuit that performs the amplitude modulation is provided in the loop so that the output of the comparison circuit is frequency-modulated, unnecessary radiation is suppressed by the frequency modulation, and the S / N ratio and the dynamic range are maintained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment according to a first aspect of the present invention.

FIG. 2 is a circuit diagram showing in detail the configuration shown in FIG.

FIG. 3 is a waveform chart explaining the operation of the circuit shown in FIG.

FIG. 4 is a waveform diagram explaining the operation of the circuit shown in FIG.

5 is a waveform diagram for explaining the function of the amplitude modulation circuit in the circuit shown in FIG.

FIG. 6 is a waveform diagram illustrating an overall operation of the circuit shown in FIG.

FIG. 7 is a circuit diagram showing the configuration of another embodiment of the present invention.

FIG. 8 is a block diagram showing the configuration of still another embodiment of the present invention.

9 is a waveform chart showing the operation of the circuit diagram shown in FIG.

FIG. 10 is a circuit diagram showing a specific circuit configuration example for the embodiment shown in FIG.

11 is a block diagram showing an embodiment in which the embodiment of FIG. 2 is applied to low load driving.

FIG. 12 is a block diagram showing an embodiment in which the embodiment of FIG. 7 is applied to low load driving.

FIG. 13 is a circuit diagram showing an example of a power driver circuit.

FIG. 14 is a circuit diagram showing another example of a power driver circuit.

FIG. 15 is a graph illustrating a duty ratio of an output signal.

FIG. 16 is an explanatory diagram showing the definition of duty ratio.

FIG. 17 is a circuit diagram showing a configuration of a circuit that can approximately obtain a correction signal.

FIG. 18 is a block diagram showing a schematic configuration of an embodiment according to the second aspect of the present invention.

FIG. 19 is a block diagram showing an example in which FIG. 18 is embodied.

FIG. 20 is a circuit diagram showing an example in which FIG. 19 is further embodied.

FIG. 21 is a waveform chart showing the operation in FIG.

FIG. 22 is a block diagram showing a configuration in which a configuration for performing amplitude modulation is provided outside the loop.

FIG. 23 is a diagram embodying FIG. 22.

FIG. 24 is a block diagram showing an example of performing another method of amplitude modulation.

[Explanation of symbols]

 1 Input Terminal 2 Input Resistance 3 Inverter 3A Buffer 4 Feedback Resistance 5, 5A Output Terminal 6 Dither Input Terminal 9 Second Feedback Resistance 10 Integrator Circuit 20, 20A Comparison Circuit 30 Feedback Circuit 40 Amplitude Modulation Circuit 45 Multiplication Circuit 51, 54 Switch Circuit 55, 56 Multiplier 70 Driver circuit 80 Low-pass filter 81 Speakers 92, 111, 140 Peak detection circuit 93, 94, 95 Comparator 96, 97, 98 Switching amplifier 110 Dither signal generation circuit

Claims (19)

[Claims] 1. An input terminal, an integrating circuit that integrates an input signal supplied to the input terminal with respect to time, and an input circuit provided on the output side of the integrating circuit and
A comparator circuit having a threshold value and a second threshold value, an output terminal connected to the output of the comparator circuit, feedback means for guiding the output of the comparator circuit to the input of the integrator circuit, A pulse width modulation circuit provided in a loop including a circuit and the comparison circuit, the amplitude modulation circuit performing amplitude modulation so that an output of the comparison circuit is frequency-modulated. 2. An input terminal, an integrator circuit for integrating an input signal supplied to the input terminal with respect to time, and an output of the integrator circuit connected to an output of the integrator circuit with a first threshold value and a first threshold value. A comparison circuit for comparing with a threshold value of 2; an output terminal connected to the output of the comparison circuit; a first feedback means for guiding the output of the comparison circuit to the input of the integration circuit; and an output of the comparison circuit. And a second feedback means for guiding the output of the comparison circuit to the amplitude modulation circuit and the output of the amplitude modulation circuit to the input of the integration circuit. 3. The pulse width modulation circuit according to claim 2, wherein the amplitude modulation circuit is supplied with the output of the comparison circuit and a dither signal for modulating the amplitude thereof. 4. The pulse width modulation circuit according to claim 2, wherein the amplitude modulation circuit is composed of a differential amplification circuit including a pair of transistors having a dither signal as a common emitter input. 5. The output terminal comprises a first output terminal for inverting and outputting the output of the comparison circuit, and a second output terminal for extracting the output of the comparison circuit via a buffer. The pulse width modulation circuit according to claim 2. 6. The inverter according to claim 5, further comprising an inverter connected to the output of the comparison circuit and inverting the output of the comparison circuit, and a buffer connected to the output of the comparison circuit and maintaining the output of the comparison circuit. Pulse width modulation circuit. 7. The first output terminal is connected to an inverting input of an operational amplifier forming the integrating circuit via a first feedback circuit including a first feedback resistor, and the second output terminal is 7. The pulse width modulation circuit according to claim 6, wherein the pulse width modulation circuit is connected to the non-inverting input of the operational amplifier via two feedback resistors. 8. An amplitude modulation circuit according to claim 1, wherein the output of the comparison circuit is input to one side and the dither signal is input to the other side.
Switch circuit, and a second switch circuit that receives the inverted signal of the output of the comparison circuit as one side input and the inverted signal of the dither signal by the inverting amplifier as the other side input, and the output and input of the first switch circuit. A first multiplier for multiplying a signal; a second multiplier for multiplying an output of the second switch circuit by an inverting input of the input signal; and outputs of the first and second multipliers for the first and second multipliers. 3. The pulse width modulation circuit according to claim 2, further comprising means for superimposing it on the input of the integration circuit. 9. The amplitude modulation circuit includes first and second differential amplifiers each having an output on one side as an input and a voltage half the reference voltage as an input on the other side, and the differential amplifiers. A current mirror circuit for flowing a current corresponding to a dither signal to each common emitter of the above, an inverting amplifier for inverting the output of the second differential amplifier, and an output of the first differential amplifier and the input signal. The first multiplier, the second multiplier for multiplying the output of the inverting amplifier by the inverting input of the input signal, and the outputs of the first and second comparators are superimposed on the input of the integrating circuit. The pulse width modulation circuit according to claim 2, further comprising: 10. The pulse according to claim 2, wherein a power driver circuit is connected between the comparison circuit and the output terminal, and a low impedance load is connected to the output terminal via a low pass filter. Width modulation circuit. 11. The pulse width modulation circuit according to claim 10, wherein the low impedance load is a speaker. 12. The pulse according to claim 5, wherein a low impedance load is connected between the first and second output terminals via first and second inductances of a low pass filter. Width modulation circuit. 13. The pulse width modulation circuit according to claim 12, wherein the low impedance load is a speaker. 14. The pulse width modulation circuit is provided with a dither signal input terminal, and a correction signal for keeping the frequency of the pulse width modulation signal at a predetermined value is applied to the dither signal input terminal. Item 3. The pulse width modulation circuit according to Item 3. 15. The pulse width modulation circuit according to claim 14, wherein a correction signal generating means for outputting the correction signal is connected to the dither signal input terminal. 16. The correction circuit comprises a peak detection circuit for detecting a peak value of an input signal, and a plurality of comparison circuits in which different comparison reference voltages are input to one side and an output of the peak detection circuit is input to the other side. 16. A switch, a plurality of switch amplifiers whose amplification operations are controlled according to the outputs of these comparators, and an adder circuit that superimposes the outputs of these switch amplifiers. Pulse width modulation circuit. 17. An input terminal, an integrator circuit for integrating the input signal supplied to the input terminal with respect to time, and an amplitude modulation circuit connected to the output of the integrator circuit for performing amplitude modulation of the integrator output, A comparison circuit connected to the output of the amplitude modulation circuit for comparing the output of the amplitude modulation circuit with a first threshold value and a second threshold value; and an output terminal connected to the output of the comparison circuit, A pulse width modulation circuit comprising: feedback means for guiding the output of the comparison circuit to the input of the integration circuit. 18. The pulse width modulation circuit according to claim 17, further comprising a modulated wave generation circuit that controls amplitude modulation for the amplitude modulation circuit. 19. The modulated wave generation circuit includes a peak detection circuit for detecting a peak of an input signal, and an adder for superimposing an output of the peak detection circuit and a dither signal, wherein the amplitude modulation circuit performs the addition. 19. The pulse width modulation circuit according to claim 18, wherein the pulse width modulation circuit is a multiplication circuit that multiplies the output of the converter and the output of the integration circuit.