JPH07151839A - Semiconductor testing apparatus - Google Patents

Abstract

PURPOSE:To prevent a malfunction by detecting that the cycle of a clock signal has exceeded a limit value. CONSTITUTION:The semiconductor testing apparatus is constituted of a clock generator 10, an address generator 11, a control-signal generator 12, a function measuring unit 13 and a clock-cycle monitoring circuit 15. The clock-cycle monitoring circuit 15 generates a delay signal in a prescribed pulse width on the basis of a clock signal 7A from the clock generator 10, and it generates a detection signal 15A when the cycle of the clock signal 7A is shorter than the pulse width of the delay signal. By the detection signal 15A, the address generator 11 and the clock generator 10 stop operating.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus, and in particular, when a cycle of a clock signal is limited, a clock cycle monitoring means for detecting a change in the cycle of an input clock signal is provided. Thus, the present invention relates to a semiconductor test device that prevents malfunctions and the like.

[0002]

2. Description of the Related Art A semiconductor tester is used to perform a logic test on a semiconductor under test. As this type of semiconductor test device, as shown in FIG. 4, a device including a clock generator 10, an address generator 11, a control signal generator 12, a function measuring unit 13, and the like is known. In this semiconductor test apparatus, the control signal generator 12 operates at the frequency of the clock signal output from the clock generator 10, that is, at the test frequency. Also, the function measurement unit 13
Is controlled by the control signal generator 12 to apply a test vector to the DUT 14 which is the semiconductor under test,
In addition, the vector obtained from the DUT 14 is compared with the expected value vector to determine whether they match or not match. The address generator 11 gives an address for generating a pattern for a test vector from the control signal generator 12.

More specifically, in the test of the DUT 14, the above pattern has the function measuring unit 13
Are distributed to the respective pins (not shown) of the DUT 14. Further, in the function measuring unit 13, the result returned from the DUT 14 due to the pattern application is compared with the expected value, and the success or failure (pass / fail) of the test of the DUT 14 is determined by this. The test by applying the pattern as described above is divided into three modes of high speed, medium speed, and low speed depending on the frequency, for example. Also, due to such a difference in mode, for example, there is a difference in the memory capacity of the device required for the test, that is, the required memory capacity is small at high speed and becomes large as the speed becomes low. The operation speed in the semiconductor test apparatus is divided according to these modes, and the function measuring unit must be controlled at high speed as the clock frequency of the clock generator 10 becomes high.

[0004]

By the way, the operation speed of this semiconductor test apparatus is naturally limited, and the operation speed is divided according to the mode as described above. Then, it is necessary to perform the above test within the range of the maximum operating speed limited to this mode. However, for example, in a test program, if the program is written with a cycle of a clock signal that exceeds this limited value due to a description error, the test will not pass or the test device will fail. Malfunctions such as not working properly.

It is an object of the present invention to provide a semiconductor test apparatus which detects that the cycle of a clock signal exceeds the limited value and prevents malfunction when the cycle of the clock signal is limited. .

[0006]

To achieve this object, the present invention outputs a detection signal when the cycle of the clock signal becomes shorter than a predetermined delay time. That is, in the semiconductor test apparatus of the present invention, a clock generating means for generating a clock signal and a clock signal operating at the frequency of the clock signal, a predetermined test vector are added to the semiconductor under test, and a vector obtained from the semiconductor under test. In a semiconductor test apparatus having a determination means for determining match / mismatch with an expected value vector, the delay signal having a predetermined pulse width is generated based on the clock signal, and the cycle of the clock signal is the delay. Clock cycle monitoring means is provided for generating a detection signal when the pulse width is shorter than the pulse width of the signal.

Further, the clock cycle monitoring means includes, for example, a delay signal generating circuit which has a predetermined pulse width and produces a delay signal delayed by the pulse width of the clock signal, and the delay signal and the clock signal. A logical product circuit that takes a logical product and a detection signal generation circuit that generates the detection signal based on the output of the logical product circuit are used.

[0008]

The pulse width of the delayed signal generated by the clock period monitoring means corresponds to the limit value of the period of the clock signal. Therefore, it is detected when the period of the clock signal becomes shorter than the pulse width of the delayed signal as described above. If a signal is generated and the operation of the semiconductor test device is stopped or prohibited by this detection signal, the above-mentioned malfunction can be prevented.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, FIG. 1 shows an embodiment of a semiconductor test apparatus according to the present invention. The semiconductor test apparatus of this embodiment is shown in FIG.
The clock cycle monitoring circuit 15 is added to the conventional configuration shown in FIG. The clock signal 7A from the clock generator 10 is input to the clock cycle monitoring circuit 15. The clock cycle monitoring circuit 15 generates a delay signal having a predetermined pulse width based on the clock signal 7A and also generates a detection signal 15A when the cycle of the clock signal 7A is shorter than the pulse width of the delay signal. .

When the address generator 11 and the clock generator 10 are input to the detection signal 15A, the detection signal 15A is deactivated, whereby the test of the DUT 14 ends (abnormal end). Thus, when the clock signal 7A exceeds the cycle corresponding to the highest frequency (frequency of the judgment standard) in the predetermined test mode, that is, when the clock signal 7A exceeds the frequency of the judgment standard, the detection signal 15A is output. I'm trying to force the test to finish.

FIG. 2 exemplifies a concrete configuration of the clock cycle monitoring circuit 15, and FIG. 3 shows signals in respective parts thereof. As shown in FIG. 2, the clock cycle monitoring circuit 15 includes a flip-flop circuit (DFF) 1 · 6, a delay circuit 2 ·
4, a gate circuit 3, and an AND circuit 5. In the figure, 7 is an input terminal, 8 is a reset terminal,
9 is an output terminal.

At the set terminal S of the flip-flop 1,
The clock signal 7A input from the input terminal 7 is input. Signal 1 output from this flip-flop 1
A is input to the gate circuit 3 via the delay circuit 2.
The delay signal 3A output from the gate circuit 3 is input to the clock terminal of the flip-flop 1 as a signal 4A delayed by the delay circuit 4. Also, delay signal 3A
The other is input to one input terminal of the AND circuit 5. The clock signal 7A from the input terminal 7 is input to the other input terminal of the AND circuit 5. The flip-flop 6 holds the output of the AND circuit 5, and the signal 5A output from the AND circuit 5 is the flip-flop 6.
Is input to the set terminal S of. Also flip-flop 1
6 is a reset signal 8 input from the reset terminal 8
Set to the initial value with A.

In FIG. 3, (a) shows a reset signal 8A.
2B is a waveform diagram of the clock signal 7A. Further, (c) is a waveform diagram of the signal 1A, (d) is a waveform diagram of the delayed signal 3A, (e) is a waveform diagram of the signal 4A, (f).
Is a waveform diagram of the signal 5A, and (g) is a waveform diagram of the detection signal 15A. With reference to FIG. 3, the delay circuit 4 in the clock cycle monitoring circuit 15 having the above-described configuration is for determining a cycle serving as a determination reference for cycle monitoring. And delay circuit 4
Signal 4A forms a pulse trailing end of the signal 1A having a pulse width t1 of 20 ns, which is the determination reference period. The interval t3 between the signal 1A and the clock signal 7A in the first half of FIG. 3 is 12 ns.

This signal 1A is delayed by the delay circuit 2 and the gate circuit 3 and has a pulse width t2 of the clock signal 7A.
By delaying by ns, a delayed signal 3A having a pulse width of 20 ns, which is a periodic signal of the determination standard, is formed. Then, the delay signal 3A and the clock signal 7A are input to the AND circuit 5, and when the clock signal 7A comes in at a cycle shorter than the determination reference cycle of 24 ns, the AND circuit 5
Is output from the output terminal 9 and the detection signal 15A is output from the output terminal 9. In the example of FIG. 3, a change in the cycle of the clock signal 7A from 32 ns in the first half of FIG. 3 to 12 ns in the second half is detected by the signal 5A at time T1, and the detection signal 15A is output.

[0015]

According to the present invention, when the cycle of the clock signal becomes shorter than the pulse width of the delay signal, a detection signal is generated to stop or prohibit the operation of the semiconductor test apparatus. Therefore, the malfunction of the semiconductor test device can be prevented. Therefore, when a clock faster than the maximum set frequency is applied, a detection signal can be output to prevent a malfunction, and the operating rate of the semiconductor testing device is increased. Further, since it is found that the test frequency of the clock signal exceeds the limited value by the detection output, the cycle setting error in the description of the test program can be known, and the frequency setting error of the pattern generation command in the program can also be known. This is useful for developing test programs.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor test apparatus of the present invention.

FIG. 2 is a block diagram showing a clock cycle monitoring circuit that constitutes the semiconductor test apparatus of FIG.

FIG. 3 is a timing chart showing signals of respective parts in the clock cycle monitoring circuit.

FIG. 4 is a block diagram of a conventional semiconductor test apparatus.

[Explanation of symbols]

 1.6 flip-flop 2.4 delay circuit 3 gate circuit 5 AND circuit 10 clock generator 11 address generator 12 control signal generator 13 function measurement unit 14 DUT 15 clock cycle monitoring circuit

Claims (2)

[Claims] 1. A clock generating means (10) for generating a clock signal, operating at a frequency of the clock signal, adding a predetermined test vector to a semiconductor under test (14), and from the semiconductor under test (14). In a semiconductor test apparatus comprising a determination means (11, 12, 13) for comparing the obtained vector with an expected value vector to determine whether they match or not, a delay signal having a predetermined pulse width is generated based on the clock signal. A semiconductor test apparatus comprising: a clock cycle monitoring means (15) for generating a detection signal when the cycle of the clock signal is shorter than the pulse width of the delay signal. 2. A delay signal generating circuit (1, 2, 3, 4), wherein the monitoring means (15) has a predetermined pulse width and produces a delay signal delayed by the pulse width of the clock signal, and the delay signal. AND circuit for ANDing the clock signal with the clock signal
2. The semiconductor test apparatus according to claim 1, further comprising: (5) and a detection signal generation circuit (6) for generating the detection signal based on the output of the AND circuit (5).