JPH07151829A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the overhead of a circuit by making a boundary scan register also play the role of an IC code resister. CONSTITUTION:The input onto one side of a multiplexer(MUX) 14 with which a boundary scan register 100 is provided is fixed to a logic 1 or 0. The input is stored in a flip-flop(FDM) 11 with a built-in MUX, and an ID code is read out via a scan path which uses output scan data SOUT as next-stage input scan data SIN. An MUX 13 changes over a boundary scan and an ID code scan and outputs them. The last output of the boundary scan and the output of a 32nd register 100 as counted from the head are input to the MUX 13, and first to 32nd registers 100 are used when the boundary scan is used as the ID code scan. Consequently, an FF for the ID code is not required thanks to 32 registers 100, and an overhead is reduced because the scan path for the ID code is used in common.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a JTAG (Joint).
The present invention relates to a semiconductor integrated circuit equipped with a JTAG circuit conforming to the Test Action Group).

[0002]

2. Description of the Related Art The JTAG standard has been established as a method for testing the quality of wiring on a board to which a semiconductor integrated circuit is connected. In order to perform a test in accordance with this standard, the following It is necessary to incorporate the boundary scan register and the ID code register as described in 1) in the semiconductor integrated circuit.

FIG. 3 shows an example of the structure of the boundary scan register. This boundary scan register 10 is a flip-flop (hereinafter,
It is composed of a "FDM" 11), a flip-flop (hereinafter abbreviated as "FD") 12, and a multiplexer (hereinafter abbreviated as "MUX") 13, and one semiconductor integrated circuit has such a structure. Many boundary scan registers are mounted and controlled by a control circuit (not shown).

Both the input data DIN and the input scan data SIN are input to the FDM 11, and either one of them becomes valid by the switching signal SW1 output from the control circuit. The FDM 11 also has a clock signal CL
K1 is input, and according to the clock signal CLK1,
The input data DIN or the input scan data SIN is stored in the FDM 11.

The output of the FDM 11 is the output scan data S
It is output as OUT. This output scan data SO
The UT normally becomes the input scan data SIN of another boundary scan register. The output of the FDM 11 is also input to the FD 12 and stored in the FD 12 according to the clock signal CLK2. The multiplexer 13 outputs the output of the FD 12 and the data input DIN according to the switching signal SW2.
And are switched, and the switched signal becomes the output data DOUT.

A large number of boundary scan registers 10 as shown in the figure are mounted in each semiconductor integrated circuit and connected to each other to form a scan path, which is used for testing each semiconductor integrated circuit and at the same time, these semiconductor integrated circuits are also used. Is mounted on a board to form a scan path across the plurality of semiconductor integrated circuits, and is also used for a test conforming to the JTAG standard such as wiring on the board connecting the plurality of semiconductor integrated circuits. .

FIG. 4 is a diagram showing an example of the configuration of the ID code register. This ID code register 20 is
It is composed of X21 and FD22. One input of the MUX 21 is a power supply (logic “1”) or a ground (logic “logic”).
It is fixed to 0 '). The output of MUX21 is FD22
And is stored in the FD 22 according to the clock signal CLK3. The output OUT of the FD22 is usually another ID.
It becomes the input IN of the code register.

In order to perform the JTAG test, it is necessary to identify the semiconductor integrated circuits stored on the board from each other. According to the JTAG standard, each semiconductor integrated circuit has an ID code register as shown in FIG. 32 pieces of 20 are connected in series, and each ID code register 20 has a logic '
By storing 32-bit fixed data (ID number) consisting of a combination of 1'and logic '0', switching the MUX 21 to configure a shift register, and reading the ID number serially, each semiconductor on the board ID of integrated circuit
It is configured to know the number.

FIG. 5 shows an external view of a boundary scan including a plurality of boundary scan registers 10 shown in FIG. 3 and an ID code scan 2 including a plurality of ID code registers 20 shown in FIG. It is a figure showing the data output to. The boundary scan 1 or the ID code scan 2 is output at different timings by the switching signal SWO of the MUX 3.

[0010]

This circuit conforming to the JTAG standard is for testing, and although it does not contribute to the original specifications of the semiconductor integrated circuit, it occupies a large area in the chip and is called overhead. Therefore, there is a problem that a portion that can be used to realize the original operation specifications is pressed or a chip area becomes large.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor integrated circuit capable of performing a test conforming to the JTAG standard and reducing overhead.

[0012]

A semiconductor integrated circuit of the present invention which achieves the above object is a boundary scan circuit having a flip-flop shared as an ID code register in a semiconductor integrated circuit having a JTAG circuit.
It is characterized by having a register.

[0013]

In the semiconductor integrated circuit of the present invention, since the boundary scan register shares the role of the ID code register, the scale of the circuit mounted for the JTAG test is reduced and the overhead is reduced.

[0014]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a configuration block diagram of a boundary scan register according to an embodiment of the present invention. A MUX 14 is added as compared with the conventional boundary scan register 10 shown in FIG. One input of this MUX14 is logic "1"
Alternatively, it is fixed to logic '0'.

As shown in FIG. 5, since boundary scan and ID code scan are not used at the same time,
When reading the ID code, a fixedly set logic "1" or logic "0" (each bit of the ID code)
Stored in the FDM 11 and output scan data SOUT
The ID code is read out via the scan path having the input scan data SIN of the next stage.

FIG. 2 is a diagram showing the data output of the boundary scan constituted by the boundary scan register shown in FIG. Boundary for MUX3
The final output of the scan and the 32nd boundary from the beginning
The output of the scan register 100 is input, and when this boundary scan is used as an ID code scan, the 1st to 32nd boundary scan registers 100 are used.

The above embodiment (FIGS. 1 and 2) is a conventional example (FIGS.
In contrast to 5), the FD22 for the ID code register (see FIG. 4) is used for the 32 boundary scan registers.
The reference code is unnecessary, and the scan path for the ID code can be shared with the boundary scan path. Therefore, the overhead can be reduced accordingly. If the boundary scan register exists in the I / O area,
There is also an advantage that the use of the internal area by the ID code register is eliminated.

The above embodiment is merely an example. For example, the MUX 14 shown in FIG. 1 may be arranged in the path of the input data DIN, and the present invention has various other configurations.

[0019]

As described above, in the semiconductor integrated circuit of the present invention, the boundary scan register also serves as an ID code register, so that the circuit overhead is reduced.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a boundary scan register according to an embodiment of the present invention.

FIG. 2 is a diagram showing boundary scan data output configured by the boundary scan register shown in FIG. 1;

FIG. 3 is a diagram showing a configuration example of a boundary scan register.

FIG. 4 is a diagram showing a configuration example of an ID code register.

5 is a boundary scan in which a plurality of boundary scan registers shown in FIG. 3 are connected and FIG.
FIG. 9 is a diagram showing data output to the outside of an ID code scan in which a plurality of ID code registers shown in FIG.

[Explanation of symbols]

1 Boundary Scan 2 ID Code Scan 3, 13, 14, 21 Multiplexer (MUX) 10, 100 Boundary Scan Register 20 ID Code Register 11 Multiplexer Flip-Flop (FD)
M) 12,22 flip-flop (FD)

Claims (1)

[Claims] 1. A semiconductor integrated circuit equipped with a JTAG circuit, comprising a boundary scan register having a flip-flop shared as an ID code register.