JPH07149223A - Anti-lock control device - Google Patents

Abstract

PURPOSE:To reduce cost while securing certainty of actuation of safety and high reliability by constituting an anti-lock control device with a single micro computer. CONSTITUTION:Signals of wheel speed sensors S1-S4 are divided into two by an input processing circuit 1 and they are input to a single microcomputer 11. In the microcomputer 11, double system input output processing is carried out and existence of abnormality of input and output signals is checked.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an antilock control device for controlling a vehicle brake.

[0002]

2. Description of the Related Art In recent years, it has become widespread to equip a brake device for controlling a wheel of an automobile with an antilock control device for controlling the brake device most effectively in accordance with a road surface running condition of the automobile.

The anti-lock control device reduces the brake fluid pressure of the wheel cylinder when the wheels are locked or is about to be locked during braking of the vehicle, and when the locked state is restored, the brake fluid pressure is increased again to perform braking. The control is performed so as to repeat this in a short time. This makes it possible to decelerate while maintaining vehicle stability.

The antilock control device functions by reducing the brake fluid pressure during braking, and is required to have high safety not only when the system is normal but also when the system fails. Therefore, for various functions such as calculating the wheel speed, acceleration, estimated vehicle speed, slip ratio, etc. based on the input signal from the wheel speed sensor and issuing a pressure reduction command for the hydraulic pressure of the wheel cylinder based on the calculation result. High reliability is also required, and it is necessary to have a configuration that surely prohibits unnecessary depressurization in the event of a failure.

As a control circuit which meets various requirements for such antilock control, for example, US Pat. No. 4,546,437 or Japanese Patent Laid-Open No. 63-233.
There is one disclosed in Japanese Patent Publication No. 401.

The control circuit according to the first publication is composed of two independent microcomputers, and each microcomputer sends its own information to the other party and controls the control valve etc. by the main computer while monitoring each other. Have control.

The control circuit according to the second publication divides an input signal into two parts, inputs each of the divided signals into two independent microcomputers, and performs the same calculation processing in each of the microcomputers. Output the output signals independently and check whether the same output is output.If the output signals are different, the antilock control is performed by the signal determined based on the difference signal to the extent that safety can be secured. The antilock control is stopped when the difference between the output signals becomes large.

[0008]

However, the above-mentioned conventional antilock control circuits, which are disclosed in any of the publications, require at least two microcomputers and are excellent in ensuring the reliability of the control operation. But,
There is a problem that the control device becomes large and expensive.

As one of means for dealing with the above problem, 1
It is possible to employ one in which two microcomputers are used and the same functional units as those processed by two conventional independent microcomputers are provided.

However, in such a microcomputer, two control programs for processing the signals of the two systems can be provided, but since there is only one functional portion for performing logical operation processing by the control program, this processing is performed. If there is an abnormality or a failure in the functional part, the processing results will match regardless of the abnormality or the failure, and there is a problem that the abnormality or the failure cannot be detected completely.

According to the present invention, in consideration of the above-mentioned problems of the conventional antilock control device, each signal obtained by branching the detected wheel speed information into two systems is processed by an arithmetic logic circuit in one microcomputer. Then, it is an object of the present invention to provide an antilock control device capable of reducing the cost while ensuring high safety, reliability, and high reliability as in the case of processing by two conventional independent microcomputers. .

Still another object of the present invention is to check the instruction system of the central arithmetic logic circuit for the functional portion directly related to the microcomputer in the one microcomputer by another simple check program. It is an object of the present invention to provide a control arithmetic logic circuit for an antilock control device in which a check arithmetic circuit to be added is added to ensure high safety, reliability and reliability even with one microcomputer.

[0013]

As a means for solving the above-mentioned problems, the present invention divides a wheel speed signal detected by a wheel speed detecting means into two systems, and divides this branched input signal into a single control arithmetic logic circuit. Input to different input terminals, first, one of the branched input signals is processed by the first arithmetic circuit and the first variable storage circuit as the first processing to determine the first output, and based on this determination An output signal is output from a predetermined output terminal, and the other input signal branched as the second processing is stored in a second arithmetic circuit similar to the first arithmetic circuit and a second variable storage similar to the first variable storage circuit. The second output signal is processed by a circuit to determine a second output, and the second output signal is output from a terminal other than the first output terminal, and the first output and the second output are output determination logic circuits. Is processed by the comparison signal after this processing. And an output abnormality detection circuit for detecting an abnormality of the output signal, the solenoid valve by the determined processed signal is to that the anti-lock control device comprising so as to drive the control target such as a relay.

Regarding the first and second variable storage circuits in the above control device, the input signal used for the first process is stored in the first variable storage circuit immediately after the input signal used for the second process is stored in the second variable. Circuit, and then the first process is performed based on the input signal stored in the first variable storage circuit, and then the second process is performed using the input signal stored in the second variable storage circuit. Can be configured as.

Further, an input comparison processing unit for detecting by a comparison logic operation of signals, a wheel speed, a reference wheel speed, a slip ratio, etc. are obtained according to a predetermined operation program based on the input signal, and pressurization, decompression or It consists of a pressurization / decompression determination unit that outputs a control signal such as holding, and an output distribution processing unit that distributes the output signal to predetermined terminals, and each output signal is processed by an output processing circuit to control solenoid valves, relays, etc. The antilock control device is designed to drive the object.

In this case, with respect to the acceleration signal sent to the pressurization / decrease determination unit when determining the lock or the lock tendency, the detection plate vehicle acceleration signal is input by the vehicle body acceleration detecting means and branched into two systems. Each input signal is input in parallel to another different input terminal of the single control arithmetic logic circuit, and the control arithmetic logic circuit detects another abnormality of the vehicle body acceleration signal by a comparison logic operation of both signals. It is preferable that the input signal is sent to the pressure increase / decrease determination unit as a reference acceleration signal for the pressure increase / decrease determination.

Further, it is preferable that a brake switch signal is added as the input signal, and the added input signal is double processed.

Further, the single control arithmetic circuit connects a predetermined output terminal to a predetermined input terminal which is not connected to anything else, outputs a predetermined signal from the output terminal, and confirms with the input circuit. It is also possible to have an input terminal monitoring circuit.

Further, the output abnormality detection unit determines that the output is normal when the time difference between the two outputs is less than or equal to the maximum output time difference caused by the serial operation processing, and is normal when the output difference is greater than the maximum output time difference. It may be determined that the output is not proper.

As a means for coping with the above-mentioned another problem, a sixth aspect of the present invention is to provide an arithmetic circuit having an input terminal and an output terminal for processing an input signal from the input terminal and a variable for the input signal and the arithmetic processing. It consists of a single control arithmetic logic circuit that has a central arithmetic logic circuit that stores the edit storage circuit to store and the signal processing by these circuits to determine the output, and performs predetermined logic and arithmetic processing in the arithmetic circuit. Anti-lock control with first and second check operation circuits for checking the operation of the central operation logic circuit, and outputting an abnormal signal when the results of the logic and operation processing by both check operation circuits do not match. It is used as a device control arithmetic logic circuit.

In the embodiment of the present invention, the input terminals are different input terminals for branching and inputting the same input signal into two, and the arithmetic circuit and the variable storage circuit process one of the branched input signals. A first arithmetic circuit and a first variable storage circuit, and a second arithmetic circuit that processes the other input signal and a second variable storage circuit, and the central arithmetic logic circuit is the signal processing by the first and second circuits. Is provided so as to determine the first and second outputs, the output terminal is provided as a different terminal that outputs the determined output, and the logic / operation processing by the first and second check operation circuits is performed. Is preferably performed before the logic / processing by the first and second arithmetic circuits.

In this control arithmetic logic circuit,
One of the first and second check arithmetic circuits performs arithmetic processing by multiplication and subtraction on the data of one of the variable storage circuits, and the other arithmetic operation by division and addition on the data of the other variable storage circuit. It is preferable that the arithmetic processings performed by the first and second check arithmetic circuits, such as processing, conflict with each other.

In that case, in order to check the operation of the central arithmetic logic circuit, a logical arithmetic instruction of an input signal,
Both check arithmetic circuits may be provided so as to perform all command commands of the central arithmetic logic circuit including plug setting, resetting, judgment sentence, value substitution, and value retrieval.

[0024]

In the antilock control device of the present invention constructed as described above, the wheel speed signal from the wheel speed detecting means is divided into two input terminals of the single control arithmetic logic circuit through the respective input processing circuits. Is input and an output signal is output from different terminals of the same chip according to the calculation result in the control calculation circuit. This output signal is processed by the output decision logic circuit to prevent the wheels from locking by driving at least the solenoid valve and adjusting the brake fluid pressure.

In the arithmetic logic circuit, two input signals are compared, and if the difference is within a certain range, it is judged to be normal, and normal antilock control is performed. Beyond a certain range,
It is judged to be abnormal and the control is stopped. These controls and monitoring are performed by a single control arithmetic logic circuit unlike the conventional case.

In the anti-lock control, basically, various calculations are performed with the wheel speed signal as a reference to determine whether the pressure is increased or decreased. However, since the vehicle body acceleration is not always accurate when the vehicle body speed is rapidly decelerated by braking by using the differentiated wheel speed signal, the acceleration detecting means is generally provided separately.

Therefore, even when the vehicle body acceleration signal is input to the control arithmetic logic circuit, it is preferable to input the signal in parallel with the wheel speed signal in two systems. This acceleration signal is sent to the arithmetic circuit as a reference acceleration signal. Generally, when there is a certain error or more from the acceleration signal obtained by differentiating from the wheel speed signal, the acceleration signal from the vehicle body acceleration detecting means is correct. Is used as a reference value.

The switch signal from the switch input detecting means is inputted in order to improve the accuracy of the antilock control, and in this case as well, it is used as one of the factors for judging the pressure increase / decrease by the switch signal.

The sixth aspect of the invention is based on the premise that a single control arithmetic logic circuit (microcomputer) is used, and that the arithmetic circuit and the variable storage circuit are also single. Therefore, when performing antilock control by this,
It is not the control such that two microcomputers perform parallel processing or mutual monitoring, but the processing is exactly the same as that performed by a normal single microcomputer. However, only by performing such processing, there is no function of checking for ensuring the safety, reliability, and reliability of the operation.

Therefore, in the sixth aspect of the present invention, in order to check the abnormal operation of the conventional microcomputer, the first and second check arithmetic circuits are provided to detect the occurrence of the abnormal state, thereby ensuring the safety and reliability of the operation. , To ensure reliability.

In this case, the confirmation of the operation by the first and second check arithmetic circuits is generally performed before the processing by the normal control program (antilock control in this invention) by the central arithmetic logic circuit is started. Although it is performed, it is needless to say that it is not always necessary to start such program control but may be performed during or after the control program.

In the control arithmetic logic circuit of the seventh invention, the first and second check arithmetic circuits are provided in the single control arithmetic circuit of the first invention. As a result, before the logic / arithmetic processing is started by the original control program for anti-lock control, the result of logic / arithmetic processing of both check arithmetic circuits is judged to be normal or abnormal depending on whether they match or not. do.

Even when the check operation is performed by the two check arithmetic circuits, the instruction system of the central arithmetic logic circuit for the first arithmetic circuit and the variable storage circuit, and the central arithmetic logic circuit for the second arithmetic circuit and the variable storage circuit. The instruction system is processed in the same order as the original first control program and the second control program by the control arithmetic logic circuit are processed.

If the results of the above two logic / arithmetic processings match, the central arithmetic logic circuit is considered to be normal, and then the original antilock control by the control arithmetic logic circuit is performed. If they do not match, an abnormality signal indicating that the central arithmetic logic circuit is abnormal is output.

In the case of the above-mentioned normality / abnormality check, in the eighth aspect of the invention, the operation command by one of the two check operation circuits performs operation processing by multiplication and subtraction on the data of the variable storage circuit to which the command command corresponds, and the other operation It is assumed that the operation command by the check operation circuit performs operation processing by division and addition on the data of the variable storage circuit corresponding to the command.

As described above, even if the data stored in the arithmetic processing result variable storage circuit by one instruction command system and the data stored in the other system are different in arithmetic processing, as long as the central arithmetic logic circuit is normal, it is always necessary. By setting the arithmetic processing contents included in the command command so that they coincide with each other, even in a single control arithmetic logic circuit, the processing in the two systems can be surely executed with high safety and reliability.

In the ninth invention, the first and second check operation circuits are provided so as to check all instruction commands of the central operation logic circuit by the four arithmetic operations. Therefore, the instruction command of the central processing logic circuit is checked for normality before executing actual program control, so that safety, certainty, and reliability are ensured.

[0038]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an antilock control circuit according to the embodiment. S _{1 to} S ₄ are wheel speed sensors,
A signal having a frequency proportional to the rotation speed of the wheel is generated. G
Is a vehicle body acceleration sensor, and SW is a stop switch signal detecting means.

The signals from the wheel speed sensors S _{1 to} S ₄ are input to the input processing circuit 1, where the waveform is shaped and converted into a binarized signal, which is then branched into two systems respectively to the next one-chip microcomputer. It is read into the microcomputer at a predetermined timing via 11 input ports. At this time, the signal from the wheel speed sensor S ₁ is input to the ports P _{0 1} and P ₁₁ and the signal from the wheel speed sensor S ₂ is input to the ports P _{0 2} and P ₁₂ and S ₃ is P _{0. 3}
To S ₀ , S ₄ to P _{0 4} , P ₁₄ and so on.

Inputs from the acceleration sensor G and the stop switch signal detecting means SW are input processing circuit 2 respectively.
After being processed by (1) and waveform shaping, it is branched into two systems and sent to the microcomputer 11. The signal of the acceleration sensor G is input to the ports P _{0 5} and P ₁₅ and the switch signal is input to the ports P _{0 6} and P ₁₆ .

The input wheel speed signal is arithmetically processed by the control arithmetic circuit in the microcomputer. As shown in FIG. 2, the control arithmetic circuit includes an input storage processing unit, a first arithmetic processing unit, a pressure increase / decrease determination processing unit, an output determination unit, an output storage unit, and a first arithmetic processing unit to an output storage unit. The second processing unit is exactly the same as the above, an output processing unit, an input terminal monitoring processing unit, and an output comparison processing unit, all of which are built in one one-chip microcomputer. Further, an output processing unit, an input terminal monitoring processing unit, and an output comparison processing unit, which will be described later, are also built in the microcomputer.

The input storage processing unit G ₁ stores and stores the signal branched and input into two systems at a predetermined address of the memory, and the first arithmetic processing unit G ₂ calculates the wheel speed based on the input signal. Calculation, calculation of wheel acceleration, calculation of estimated vehicle speed,
Perform necessary arithmetic processing such as calculation of slip amount. Then, the pressurization / depressurization determination processing unit G ₃ pressurizes from the result of the above arithmetic processing,
It is determined which of the pressure reducing signals should be output, and the output determining unit G ₄ outputs the pressure reducing signal, and the output signal is stored in the memory of the output storing unit G ₅ .

Regarding the functional components from the first arithmetic processing unit to the output storage unit, the second arithmetic processing unit to the output storage unit G ₆
Another set of exactly the same as G ₉ is provided. The two sets of processing units correspond to branching the wheel speed signal into two and processing signals input from different terminals.

The output processing section G _{1 0} outputs two output signals obtained based on the functions of the above two sets of arithmetic processing section to output determination section for each system to be controlled such as solenoid valves and relays. and outputs an output signal from the output terminal P _{2 1} -P _{3 1.}
Output terminals _{P 2 2 -P 3 2, P} 2 3 -P 3 3, P 2 4 -P
_{3 4} The same applies to the _{P 2 5 -P 3 5, P} 2 6 -P 3 6.

The input terminal monitoring processor G ₁₁ has the output terminal P
₃ the output from the ₇ input to the input terminal P _{1 7,} monitors the abnormality due to malfunction of the input terminal itself, stops the driving of the solenoid valve or the like is when detecting an abnormality control target by the abnormality signal.

The output signal is the NAND element C ₁ , NO
It is sent to the drive unit 12 via the output comparison processing unit G _{1 2} composed of the R element C ₂ to drive the solenoid valve 13 ₁ . The same applies to the NAND elements C _{1 to} C ₁₁ NOR elements C _{4 to} C ₁₂ and the solenoid valve 13 ₂ .

The NOR elements C ₂ , C ₄ , C ₆ ,
_{C 8, C 1 0, C} 1 to ₂ serves as the output signal of the watchdog circuit 14 is inputted, when there is abnormal operation of the microcomputer NO by the abnormality detection signal
The output of the R element is cut to ensure the safety of operation.

Signals from the acceleration sensor G and the stop switch signal detection SW are not shown in the figure, but a processing unit having the same function as that of the input storage processing unit and below in the control arithmetic circuit corresponds to each signal. It is provided so that the presence or absence of abnormality of each signal can be determined.

Reference numeral 15 is an output signal monitor line.

The operation of the embodiment configured as described above will be described with reference to the flowchart of FIG.

First, the wheel speed sensors S _{1 to} S ₄ , G, SW
After the input signal is processed by the input processing circuits 1 and 2, in the input storage processing section G ₁ , the calculation register RO is processed in step S _1.
Input signals S _{1 to} S ₄ , G, S in the group setting state
W is read from each of the ports P _{0 1} to _{0 6} (step S ₂ ), and its input signal is $ FD _{0 0} to the RAM.
₀ is stored in the Address ₅ address (Step S _3).

Next, in step S ₄ , the operation register is set to R ₁
The other input signal S ₁ to S ₄ which branches into two in the state set to the group, G, and SW from the port P _{1 1} ~ _{1 6} read (step S _5), and the input signal of the RAM $
Store in the address of FE _{0 0} to _{0 5} (step S
₆ ).

Then, in step S ₇ , the operation register is set to the RO group again and the input signal is set to $ FD of the RAM.
Call from address _{0 0-0 5} (step S ₈ ), and control signals WS ₁ to ₄ and WS whose input signal is proportional to frequency.
G, into a WSS, the calculation of calculation slip amount calculating estimated vehicle speed calculation wheel acceleration of the wheel speed based on these (step S _9).

[0054] the process of pressurization determined based on step S _{1 0} In the above calculation results. That is, it is determined whether the pressure should be further reduced or increased depending on the slip amount.

This pressure increase / decrease determination is carried out based on the variable obtained by the calculation in the previous step S ₉ , and for example,
When the wheel speed is lower than the reference wheel speed, it is determined whether to output a control signal for operating the solenoid valve in the direction from pressurization to depressurization or holding according to the speed difference. And, thereby outputting a control signal for opening and closing the solenoid valves V1, V2 of the brake pressure control of the anti-lock braking system in step S _{1 1.}

This means that when the wheel speed falls below the reference wheel speed by a predetermined amount, the slip ratio of the wheel increases, and the tire friction force due to brake braking is not effectively utilized. Therefore, the brake braking force is reduced for an extremely short time even during the brake braking, and when the slip ratio is recovered, the brake braking is again operated in the holding or pressurizing direction. The lock of the wheels can be prevented by performing the above operation.

The output determination unit G ₄ determines the output based on the above determination. The output signal of RAM $ FD _{1 0}
-Stored at the address of address ₁₅ .

Next, the operation register in step S ₁₃ is set to the R ₁ group and the input signal is $ FE _{0 0 of} RAM.
- ₀ calls from address _5, the calculation of calculation slip amount calculating estimated vehicle speed calculation wheel acceleration WSG to control variables WSI, which is proportional to the frequency of the input signal, and converts the WSS wheel speed (Step S _{1 5} ). In this case, the input signal is from the other input terminal.

Then, as in the case of the first group,
Decrease pressure determination (step S _{1 6),} and determines and outputs the output based on the determination (step S _{1 7),} the output signal $ FE _{1 0} of RAM - is stored in _one address ₅ Address .

As described above, the output determined by the pressure increase / decrease based on the input signals from the one and the other terminal groups is determined. The output from the other terminal group is output from the port _{P 3 1 ~ 3 6 (S} 1 9). If the output from one terminal group, the arithmetic register in a state set to RO group (S _{2 0)} output signal of the RAM $ FD _{1 0} - reads from _{1 5} address (S _{2 1)} port P Output from _{2 1} to ₂₆ (S _{2 2} ).

In this case, regarding the outputs P _{2 1} and P _{3 1} , for example, when the drive of the solenoid valve is requested, the signal at the output terminal becomes HI and the signal is input to the NAND element of C ₁ . Therefore, when a solenoid valve drive is requested, both signals of P _{2 1} and P _{3 1} become HI and the output of C ₁ becomes LOW. The output signal of C ₁ is input to the NOR element of C ₂ . The WD signal is input to C ₂ .

The WD signal is a monitoring signal which becomes HI when the one-chip microcomputer runs out of control or abnormally stops. Therefore, the WD signal is normally LOW, and since the LOW signal is input from C ₁ when the solenoid valve drive request is made, the drive signal of the solenoid valve 13 ₁ (V1) is transmitted from C ₂ to the drive circuit 12 ₁ (DV1). The solenoid valve is actually driven. This process other solenoid valves 13 ₂ -
The same process is performed for ₄ (DV ₂ to ₄ ).

When the microcomputer outputs the above-mentioned output, at the same time, the input terminal monitoring section G _{1 1} checks for an abnormality in the input at that input terminal. This monitoring, the arithmetic register in a state set to R ₂ groups, sends to port P _{1 7} and output from the port P _{3 7} the HI output, as shown in FIG. 4, whether the input signal is a HI Judge, H
Then the input signal sends a LOW from the port P _{3 7} to port P _{1 7} as a normal if I can be judged to be normal if LOW.

If HI is not HI or LOW is not LOW in each judgment, an abnormality signal is output, indicating that one of the input terminals is abnormal,
Abnormal processing is performed. Abnormality processing of the input terminals is to prohibit the operation of the antilock control device by an OFF the output to the solenoid valves (V ₁ ~V _4). Although not shown, generally, in this operation prohibited state, a warning light is turned on by a signal indicating the state to call the driver's attention.

After checking the input terminals for abnormalities,
Check the above output for abnormalities. The output comparison processing section G _{1 2,} the output from the output terminal of the two groups described above in Step _{S 2 6 ($ FD 1 0} ~ 1 5, $ FE 1 0
~ _{1 5)} and via the port P _{4 1} - _{4 6} reads the monitor value of the output signal, the next step S ₂ output signals of the first group at _7, and a decision output signal determined by the output determining unit Each of the three is compared.

The comparison of the output signals is performed by the flowchart shown in FIG. 5, for example. First sets an initial value of the variable N to zero, step S _{2 7} FD ₁ the first group and the output signal of the second group at _{1 0 ~ 1 5, FE 1} 0 ~ 1 5
Is determined, and if they match, step S
_{At 2} 72, it is determined whether the monitor signals (ports P _{4 1} to _{4 6} ) match the values of the first group FD ₁₀ to ₁₅ .

[0067] If they coincide, 1 is subtracted from the counter FTIM to calculate the number of occurrences of abnormal state in step S _{2 7 3} (however, MIN of FTIM is 0), the variable N in Step S _{2 7 4} after 1 increments, it determines whether the variable N = 5 in step S _{2 7 5.} Initially N =
Since it is 0, the flow returns to the beginning, and the output signals are compared again.

[0068] Comparison of the output signal is repeated for the variable N = 0 to 5, during the course of the comparison flow, for example, FD _{1 0} ~ _{1 5} Step _{S 2 7 1, FE 1 0} ~
_If any of the signals of _{1 5} do not match with each other, the process proceeds to step S _{2 7 6} and 3 is added to the counter FTIM. The same applies when the disagreement in step S _{2 7 2} occurs.

[0069] The counter FT in step S _{2 7 7}
Whether or not IM is 6 or less is determined. If FTIM is 6 or less, that is, if the abnormal occurrence state is 1 or less, it is determined to be normal, and the flow returns to the normal flow route. If FTIM exceeds 6, the number of occurrences of abnormality is 2 or more, and this is judged to be abnormal, and abnormality processing is performed.

As described above, the abnormality of the output signal is monitored.
Even if the command output and the monitor output do not match with each other by the monitor line, the operation of the antilock control device is prohibited by turning off the output to each solenoid valve (DV _{1 to} V ₄ ). Although not shown, generally, in this operation prohibited state, a warning light is turned on by a signal indicating the state to call the driver's attention.

The above explanation is mainly about the basic control of the antilock based on the wheel speed signal, but in the antilock control, when the lock or lock tendency is judged and the pressurizing / decreasing signal is commanded, the arithmetic processing unit is set to the vehicle body. The acceleration signal from the acceleration sensor G is given as a reference acceleration signal. This acceleration signal is referred to the acceleration signal obtained by differentiating the wheel speed signal in the arithmetic processing section. When the acceleration signal from the differential calculation causes an error more than a predetermined value due to the acceleration signal from the sensor G, the acceleration signal is used as the reference acceleration signal instead of the acceleration signal obtained from the wheel speed.

Further, the stop switch signal detecting means S
The switch signal from W is also sent to the arithmetic processing unit in the same manner as in the case of the acceleration sensor G. For the stop switch signal, for example, the input speed to the brake device performed by the driver is estimated from the relationship between the input timing of the stop switch signal and the subsequent rate of change of the wheel speed, and the pressurization and depressurization is performed using the estimated input speed. Adjust the decompression sensitivity in judgment.

In this embodiment, the input wheel speed is 4 systems, the output valve is 4 and the relay is 2.
Of course, the number of input and output systems is not limited to this embodiment, and may be, for example, three valves with two input systems and one output and one relay.

FIG. 6 is a block diagram showing a modified microcomputer 11 'in which the internal structure of the microcomputer 11 used in the above-described embodiment is partially modified. The input signal corresponds to a signal (for example, ports P ₀₁ and P ₁₁ ) that is branched into two after being processed by the input signal circuit 1 or 2 in FIG. Since this modification mainly relates to the improvement in the microcomputer 11 ', the illustration of the configuration of the entire antilock control device is omitted, but when it is actually used, it is installed in exactly the same manner as in FIG. There is no need to explain what is done.

111 (1) and 111 (2) are I
/ O ports (1) and (2) are shown, and two identical input signals that are branched and input into two are input to different terminals I / O.
Input from O port (1), (2). Although not shown in the figure, it goes without saying that two different terminals are provided as output terminals as I / O ports.

Reference numeral 112 is a data bus, and 113 is a temporary storage unit (random access memory: R) including registers 1 and 2.
AM), 114 is a fixed storage unit (read only memory: R)
OM) and 115 are central processing units (CPU). The registers 1 and 2 are not provided as two completely independent registers but are used by dividing an area used in one memory into two. These registers 1 and 2 are I /
The input signals sent from the O ports (1) and (2) are temporarily stored in the corresponding areas, and the result calculated by the CPU 115 is temporarily stored.

The original program for antilock control is stored in each of the control programs 1 and 2 in the ROM 114. In this case as well, two completely independent ROMs are not provided, but an area of the storage memory is set. Control programs 1 and 2 are provided separately in two. Further, in this embodiment, the ROM 114 includes an instruction command group 1 execution program and an instruction command group 2 execution program (referred to as command execution programs 1 and 2) as illustrated. These two programs are also one ROM 11
It is provided in each of the two divided regions in the table 4.

The CPU 115 is an ordinary one and includes an accumulator, a temporary register, a micro ROM (command group), an ALU (algorithm unit) and the like.

The anti-lock control is performed by using the single microcomputer having the above-mentioned configuration. The operation of the normal anti-lock control is as described in detail in the first embodiment described above. The characteristic part of the embodiment will be described. Note that, to give a supplementary explanation to clarify the relationship with the flowchart of the first embodiment (FIG. 3), the input storage processing unit G ₁ corresponds to the RAM 113 described above and includes registers 1 and 2. The program of step S ₉ of the first arithmetic processing unit G ₂ is included in the control program 1, and the program of step S ₁₅ of the second arithmetic processing unit G ₆ is included in the control program 2.

It is needless to say that the CPU 115 executes various other calculations, determines the pressure increase / decrease, and determines the output.

The characteristic operation of this modified embodiment is as follows. FIG. 7A shows the flow of the main operation program, and FIG. 7B shows confirmation of the four arithmetic operations as an example. In this case, in (a), register 1
Are shown so that the execution of the logical operation by the command execution program 1 using the and the execution of the logical operation by the command execution program 2 using the register 2 are performed in parallel with each other. As shown, the actual execution is of course performed for register 2 after register 1.

Here, regarding the contents of the command execution programs 1 and 2, in the case of using the register 1 as shown in FIG. 7B, for example, for a certain input value (x), It is a program that performs a calculation process of doubling (multiplication) and then subtracting (subtracting) the original value from the value. When register 2 is used, input value (x) is divided by 2 (division), and then two values are added (addition)
Is a program that performs the calculation process.

The input value (x) may be an input signal at the time of disclosure of antilock control, but it is not always limited to the input signal, and such a special signal generator may be provided externally or internally. It may be an input value. For example, a simple example is 100 or 1000 (binarized signal).

The command execution program 1 as described above,
2, the input value (x), for example, is input and stored in the registers 1 and 2 before the antilock control is started, and this value is used to execute the above four arithmetic operations of the execution programs 1 and 2 in the CPU 115. When executed with, the values after calculation are stored in registers 1 and 2, respectively.
Each value of 2 is compared.

As a result, if the processing and the instruction by the CPU 115 are performed correctly, the stored values of the registers 1 and 2 should match, which confirms the normal function of the CPU 115.

If the above-mentioned normal state is confirmed, it is needless to say that the original antilock control is performed by using the registers 1 and 2 as shown in FIG. 7A.

If the comparison results do not match, the CPU 115
If there is an abnormality somewhere in the function of, the abnormality detection signal is output. Therefore, in this case, the fail safe function is activated by the abnormality detection signal and the antilock control is stopped.

As described above, even a single microcomputer has two arithmetic processing functions inside,
By confirming that the function of the CPU is normal before the antilock control is started, safety, certainty,
The reliability can be further improved.

In the above modification, the above-mentioned four arithmetic operation programs are shown as an example of the instruction command group execution program, but the contents of the program include various settings such as flag setting / resetting, judgment statements, value substitution / retrieval. It is necessary to confirm the function of the CPU effectively by confirming that all of these command commands are normal.

Further, in the above embodiment, the check by the instruction command group execution program is performed before the original control program starts, but it may not necessarily be before the program start, but may be in the middle or after the program start.

Further, although a single microcomputer in which the original control program is included in each of the two arithmetic processing functions has been described as an example, it should be applied to a normal microcomputer having one arithmetic processing function. There is no need to explain what you can do. This is because by checking all the command functions of the central operation logic circuit with the two checking command group execution programs, more than the conventional functions by parallel processing or mutual monitoring can be obtained.

[0092]

As described above in detail, the antilock control device of the present invention inputs the two branched input signals to a single arithmetic logic circuit separately and compares the two signals in the logic circuit. By doing so, the antilock control is performed while checking the input signal for abnormalities.Therefore, an antilock control device is configured with a single microcomputer to ensure the safety and reliability of operation while reducing the cost of the entire device. There is an advantage that it can be reduced and high reliability can be obtained.

A microcomputer added with a function for confirming whether or not the function of the central processing logic circuit (CPU) is normal in the internal program of the single microcomputer used for the antilock control device. In the invention of the control arithmetic logic circuit which is, since the function of the CPU is confirmed before starting the antilock control,
Further, there is an advantage that a product with improved safety, reliability and reliability can be obtained.

[Brief description of drawings]

FIG. 1 is an overall schematic block diagram of an antilock control circuit according to an embodiment.

FIG. 2 is a schematic flowchart of a control logic operation circuit.

FIG. 3 is a detailed flowchart of a control logic operation circuit.

FIG. 4 is a flowchart of an input terminal monitoring processing unit.

FIG. 5 is a flowchart of a comparison processing unit.

FIG. 6 is a block diagram of a microcomputer of a modified embodiment.

FIG. 7 is a schematic flow of an instruction command group execution program and an example of the program.

[Explanation of symbols]

1, 2 Input processing circuit 11 One-chip microcomputer 12 Drive unit 13 _{1 to} 13 ₄ Solenoid valve 13 RM, 13RS relay 14 Watchdog circuit 15 Monitor circuit G ₁ Input storage processing unit G ₂ First arithmetic processing unit G ₃ Pressure adjustment judgment Processing unit G ₄ output determination processing unit G ₅ output storage unit G _{1 0} output processing unit G ₁₁ input terminal monitoring processing unit G ₁₂ output comparison processing unit S _{1 to} S ₄ wheel speed sensors C ₁ , C ₃ , C ₅ , C ₇ , C ₉ , C ₁₁ NAND element C ₂ , C ₄ , C ₆ , C ₈ , C ₁₀ , C ₁₂ NOR element 111 I / O port 112 data bus 113 RAM 114 micro ROM 115 CPU

Claims (9)

[Claims] 1. A wheel speed signal detected by a wheel speed detecting means is branched into two systems, and the branched input signals are input to different input terminals of a single control arithmetic logic circuit, and the branched input signal is first One is processed as the first processing by the first arithmetic circuit and the first variable storage circuit to determine the first output,
An output signal based on this determination is output from a predetermined output terminal, and the other input signal branched as the second processing is used as a second operation circuit similar to the first operation circuit and a first variable storage circuit. The second output is processed by the second variable storage circuit, and the second output signal is output from a terminal different from the first output terminal, and the first output and the second output are ,
The output decision logic circuit has an output abnormality detection circuit that performs decision processing and performs a logical comparison operation on the processed signal to detect an abnormality in the output signal. An anti-lock control device configured to be driven. 2. An input signal used for the first process is stored in the second variable storage circuit immediately after storing the input signal used for the first process in the first variable storage circuit. 2. The method according to claim 1, wherein the processing is performed based on the input signal stored in the one-variable storage circuit, and then the second processing is performed using the input signal stored in the second-variable storage circuit. Anti-lock control device as described. 3. The antilock control device according to claim 1, wherein a brake switch signal is added as the input signal, and the added input signal is also double processed. 4. The single control arithmetic circuit connects a predetermined output terminal to a predetermined input terminal that is not connected to anything else, outputs a predetermined signal from the output terminal, and confirms the input circuit. The antilock control device according to claim 1, further comprising an input terminal monitoring circuit. 5. The output abnormality detection unit determines that the output is normal when the time difference between the two outputs is less than or equal to the maximum output time difference caused by the serial operation processing, and is normal when the output difference is greater than the maximum output time difference. The antilock control device according to any one of claims 1 to 4, wherein it is determined that the output is not proper output. 6. An arithmetic circuit having an input terminal and an output terminal for processing an input signal from the input terminal, a variable storage circuit for storing the input signal and a variable by the arithmetic processing, and a signal processing by these circuits for output. A single control arithmetic logic circuit having a central arithmetic logic circuit for determining the central arithmetic logic circuit, which performs predetermined logic / arithmetic processing in the arithmetic circuit to check the operation of the central arithmetic logic circuit. A control arithmetic logic circuit for an anti-lock control device, which is provided with a check arithmetic circuit and is configured to output an abnormal signal when the results of logic / arithmetic processing by both check arithmetic circuits do not match. 7. A first arithmetic circuit in which the input terminal is a different input terminal for branching and inputting the same input signal into two, and the arithmetic circuit and the variable storage circuit process one of the branched input signals. And a first variable storage circuit, and a second operation circuit for processing the other input signal and a second variable storage circuit,
The central arithmetic logic circuit is provided to perform signal processing by each of the first and second circuits to determine the first and second outputs,
The output terminal is provided as a different terminal that outputs the determined output, and the logic / operation processing by the first and second check operation circuits is performed before the logic / processing by the first and second operation circuits. The control arithmetic logic circuit for an anti-lock control device according to claim 6, characterized in that. 8. The first and second check arithmetic circuits perform arithmetic processing by multiplication and subtraction on the data of one of the variable storage circuits, and the other one on the data of the other variable storage circuit. The control arithmetic logic circuit for an antilock control device according to claim 6 or 7, wherein the control arithmetic logic circuit is a circuit that performs arithmetic processing by division and addition. 9. An instruction command of a central arithmetic logic circuit including a logical operation instruction of an input signal, a flag setting, a reset, a judgment sentence, a value assignment, and a value extraction is distributed to both check arithmetic circuits. The control arithmetic logic circuit for an antilock control device according to claim 6 or 7.