JPH07147385A - Semiconductor circuit device for reducing influence of parasitic capacity - Google Patents

Abstract

PURPOSE:To reduce the influence of parasitic capacity by forming a first parasitic capacity formed between a first resistor and a semiconductor substrate so that it is equal to a second parasitic capacity formed between a second resistor and the semiconductor substrate. CONSTITUTION:When a first resistor 31 is connected to an inversion input terminal 33-1 of a differential amplification circuit 33, one edge of a first dummy resistor 61 is connected to a non-inversion input terminal 33-2 and the other edge is opened. Similarly, when a second resistor 32 is also connected to the inversion input terminal 33-1 of the differential amplification circuit 33, one edge of a second dummy resistor 62 is connected to the non-inversion input terminal 33-2 and the other edge is opened. Then, each parasitic capacity formed between the first and second resistors 31 and 32 and the semiconductor substrate is made equal to each parasitic capacity formed between the dummy resistors 61 and 62 and the semiconductor substrate, thus preventing external noise from entering a semiconductor circuit and from being affected by potential fluctuation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit device including a differential amplifier circuit.

[0002]

2. Description of the Related Art As an example of a semiconductor circuit device including a differential amplifier circuit, for example, a reference voltage generating circuit is well known.
When this type of reference voltage generation circuit is realized by an IC, the reference voltage generation circuit is formed on the semiconductor substrate in addition to the first to third resistors formed on the semiconductor substrate, It includes a differential amplifier circuit having first and second input terminals and an output terminal. The first resistor is connected between the signal input terminal and the first input terminal via the first wiring pattern. In this case, the first resistor and the first wiring pattern act as a signal input line. The second resistor is connected between the output terminal and the second input terminal via the second wiring pattern. The second input terminal is also grounded through the third resistor. An input signal is supplied to the first input terminal through the first resistor and has a first input potential (or voltage, which will be described below as voltage). The second input terminal has a second input voltage.

The reference voltage generating circuit amplifies the difference voltage between the first and second input voltages and outputs the amplified signal to the output terminal as an output signal having a predetermined reference voltage. The second resistor acts as a feedback resistor for feeding back the output signal to the second input terminal. Therefore, the second resistor and the second wiring pattern act as a feedback line. The third resistor acts as a voltage dividing resistor.

By the way, it is inevitable that this type of reference voltage generating circuit has a parasitic capacitance. For example, a first parasitic capacitance having a first capacitance value is formed between the signal input line and the semiconductor substrate, particularly between the first resistor and the semiconductor substrate, and between the feedback line and the semiconductor substrate, In particular, a second parasitic capacitance having a second capacitance value is formed between the second resistor and the semiconductor substrate. The first capacitance value and the second capacitance value are different from each other. The first and second input voltages are affected by the first and second parasitic capacitances, respectively. For example, when external noise enters the reference voltage generation circuit, the first capacitance value and the second capacitance value are different from each other, so that the amplitudes of the first and second input voltages individually change with a certain time difference. . In this case, the output signal greatly varies in amplitude.
This means that it is difficult for this type of reference voltage generation circuit to output an output signal having a predetermined reference voltage when external noise enters.

This will be described below with reference to the drawings. FIG. 14 shows a reference voltage generating circuit as an example of a conventional semiconductor circuit device. This reference voltage generating circuit is
The third resistors 21 to 23 and the first and second input terminals 24-
1, 24-2, and a differential amplifier circuit 24 having an output terminal 24-3. The first input terminal 24-1 has a first
Is connected to the signal input terminal 25 through the resistor 21 and is supplied with an input signal having a constant input potential (or voltage). The second input terminal 24-2 is connected to the output terminal 24-3 through the second resistor 22, and the third resistor 2
It is grounded through 3. As will be apparent later, the second resistor 22 acts as a feedback resistor for feeding back the output signal of the differential amplifier circuit 24 to the second input terminal 24-2. The third resistor 23 acts as a voltage dividing resistor. The differential amplifier circuit 24 may be called a comparator.

When this type of reference voltage generating circuit is realized by an IC, the differential amplifier circuit 24 is formed on a semiconductor substrate (not shown). The first resistor 21 is connected between the signal input terminal 25 and the first input terminal 24-1 via the first wiring pattern. The first resistor 21 and the first wiring pattern may be collectively referred to as a signal input line. The first wiring pattern is formed in the upper wiring layer formed on the semiconductor substrate. The second resistor 22 is connected between the output terminal 24-3 and the second input terminal 24-2 via the second wiring pattern. The second resistor 22 and the second wiring pattern may be collectively referred to as a feedback line. The second wiring pattern is formed in the intermediate wiring layer formed on the semiconductor substrate. The output terminal 24-3 and the signal output terminal 26 are connected by a third wiring pattern called a signal output line. The third resistor 23 is grounded through a ground line. The ground line is formed by a ground wiring pattern.

The input signal is transmitted through the signal input terminal 25 to the first
Of the first input terminal 2 when supplied to the input terminal 24-1 of
4-1 has a first input potential P1. The output signal is fed back to the second input terminal 24-2 through the feedback line. In this state, the second input terminal 24-2 has the second input potential P2 determined by the second and third resistors 22 and 23.
have. When the output potential OP of the output signal rises, the second input potential P2 becomes higher than the first input potential P1. In this case, the differential amplifier circuit 24 is connected to the first input potential P1 and the second input potential P1.
It operates so as to reduce the potential difference from the input potential P2. As a result, the output potential OP is reduced so that the first input potential P1 and the second input potential P2 are equal to each other.

When the output potential OP decreases, the second input potential P2 becomes lower than the first input potential P1. Also in this case, the differential amplifier circuit 24 operates so as to reduce the potential difference between the first input potential P1 and the second input potential P2.
As a result, the output potential OP is equal to the first input potential P1 and the second input potential P1.
Input potential P2 is increased to be equal to each other. By the feedback operation through the feedback line, the differential amplifier circuit 24 outputs an output signal having a constant output potential through the signal output terminal 26.

The above-mentioned operation is an ideal operation in an ideal state. In practice, this type of reference voltage generating circuit is
It has first and second parasitic capacitances indicated by C1 and C2 in FIG. The first parasitic capacitance C1 has a first capacitance value,
Is formed between the resistor 21 and the semiconductor substrate, or between the first wiring pattern and another wiring pattern. Similarly, the second
The parasitic capacitance C2 of has a second capacitance value, and the second resistance 2
2 and the semiconductor substrate, or between the second wiring pattern and another wiring pattern.

Usually, the first and second capacitance values are greatly different. This is because the first wiring pattern and the second wiring pattern are formed in the upper wiring layer and the intermediate wiring layer, which are different in position and formation state. This means that the first and second input potentials P1 and P2 are individually affected by the first and second parasitic capacitances C1 and C2. For example,
When external noise enters the reference voltage generation circuit, the amplitudes of the first and second input potentials P1 and P2 individually change with a time lag. As a result, the output potential OP is
As shown in FIG. 15, the amplitude changes greatly.

An inverting amplifier circuit as another example of the conventional semiconductor circuit device will be described with reference to FIG. This inverting amplifier circuit includes a first resistor 3 having a first resistance value R1.
1 and a second resistor 32 having a second resistance value R2, a differential amplifier circuit 33 having an inverting input terminal 33-1 and a non-inverting input terminal 33-2 and an output terminal 33-3. . The inverting input terminal 33-1 is connected to the signal input terminal 34 through the first resistor 31, and the non-inverting input terminal 33-2 is directly connected to the reference voltage input terminal 34. The second resistor 32 acts as a feedback resistor, and the inverting input terminal 33-1
And the output terminal 33-3.

The signal input terminal 34 is supplied with an input signal having the input voltage Vi, and the reference voltage input terminal 35 is supplied with the reference voltage Vr. This inverting amplifier amplifies the difference voltage between the input voltage Vi and the reference voltage Vr, and outputs the amplified signal having the output voltage Vo as an output signal to the signal output terminal 36. The output voltage Vo is represented by the following formula.

Vo = (− R2 / R1) · (Vi−Vr) + Vr With reference to FIG. 17, the differential amplifier circuit 33 includes a differential amplifier unit 3.
3-4, output amplifier 33-5, and bias generator 33
-6 and. The differential amplifier 33-4 includes first and second n-channel MOS transistors Q1 and Q2,
It has third and fourth p-channel type MOS transistors Q3 and Q4 having a current mirror configuration. First,
The second MOS transistors Q1 and Q2 each have a gate electrode connected to the inverting input terminal 33-1 and the non-inverting input terminal 33-2. The third and fourth MOS transistors Q3 and Q4 act as active loads of the first and second MOS transistors Q1 and Q2, respectively. The differential amplifier 33-4 further includes an n-channel type fifth MOS transistor Q5 for supplying a constant current to the first and second MOS transistors Q1 and Q2. That is, the fifth MOS transistor Q5 is connected to the differential amplifier 33
-4 acts as a current source.

The output amplifying section 33-5 includes a p-channel type sixth MOS transistor Q6 and n connected in series.
-Channel type seventh MOS transistor Q7. The seventh MOS transistor Q7 acts as a current source of the output amplification section 33-5. Bias generator 3
3-6 has a resistor 33-7 and an n-channel type eighth MOS transistor Q8 connected in series, and is connected between the high voltage supply line 37 and the low voltage supply line 38. The high voltage supply line 37 has a first voltage Vdd and the low voltage supply line 38 has a second voltage Vss that is lower than the first voltage Vdd. Bias generator 33-6
Is for supplying a gate bias voltage to the gate electrodes of the fifth and seventh MOS transistors Q5 and Q7.

The inverted output signal of the differential amplifier 33-4 is the second
Drain electrode of the MOS transistor Q2 and the fourth MO
It appears at the connection point CP1 with the drain electrode of the S transistor Q4. The inverted output signal is amplified by the output amplifier 33-5 and output from the output terminal 33-3.

This type of inverting amplifier circuit can be realized by a one-chip IC. In this case, the first and second resistors 31, 3
2 is formed by the following first and second methods. In the first method, the first and second resistors 31 and 32 are realized by diffusion layers formed on the semiconductor substrate. For example, in a silicon semiconductor IC, the first and second resistors 31 and 32 are realized by n ⁺ diffusion layers formed on a p-type silicon crystal substrate. In the second method, the first and second resistors 31, 32 are
Is formed of a conductor film having a high sheet resistance value. The conductor film is formed on an insulating layer called a field region.
In such a silicon semiconductor IC, the first and second
The resistors 31 and 32 are realized by a polycrystalline silicon film formed on a field oxide film (SiO2).

The first method will be described with reference to FIG. P ⁻ type silicon substrate 4 as a semiconductor substrate
A field oxide film 41 is formed on the oxide film 0, and openings 41-1 and 41-2 are formed in the field oxide film 41. The silicon substrate 40 corresponding to the openings 41-1 and 41-2 has first and second n ⁺ diffusion layers 40-1 and 40-1, respectively.
40-2 is formed. First and second n ⁺ diffusion layers 4
0-1 and 40-2 are respectively the first and the second shown in FIG.
Of the resistors 31 and 32. First n ⁺ diffusion layer 4
0-1 is aluminum wiring patterns 42-1 and 42-
2 is connected between the signal input terminal 34 and the inverting input terminal 33-1. Aluminum wiring pattern 42
-1, 42-2 may be collectively referred to as a first wiring pattern. The second n ⁺ diffusion layer 40-2 passes through the aluminum wiring patterns 43-1 and 43-2 and the inverting input terminal 33
-1 and the output terminal 33-3 are connected. The aluminum wiring patterns 43-1 and 43-2 may be collectively referred to as a second wiring pattern. Reference voltage input terminal 35
Are connected to the non-inverting input terminal 33-2 through the aluminum wiring pattern 44. In FIG. 18, the differential amplifier circuit 33, the aluminum wiring pattern 42-1,
Although 42-2, 43-1, 43-2, and 44 are shown on the outside of the silicon substrate 40 for convenience, they are actually formed on the silicon substrate 40. This also applies to each terminal such as the signal input terminal 34 and the reference voltage input terminal 35.

A p ⁺ diffusion layer 45 is formed in the silicon substrate 40 through the opening 41-3. The p ⁺ diffusion layer 45 is connected to the power supply 46, and is for supplying the substrate bias voltage Vb to the silicon substrate 40 as is well known. For easy understanding of the explanation, it is assumed that the n-channel type MOS transistor Qn is formed on the silicon substrate 40. The MOS transistor Qn is used for other circuits (not shown) formed on the silicon substrate 40. The drain of the MOS transistor Qn,
For the source, the third and fourth n ⁺ diffusion layers 40-3, 4
0-4 are the fourth and fifth openings 41-4, 41-, respectively.
5 is formed on the silicon substrate 40.

In this type of inverting amplifier circuit using a one-chip IC, S / N tends to decrease due to external noise that changes the potential of the silicon substrate 40. This is based on the following reasons.

This inverting amplifier circuit comprises a silicon substrate 40 and first and second n ⁺ diffusion layers 40-1, 40-2, p ⁺ diffusion layer 45, third and fourth n ⁺ diffusion layers 40-3. , 40-4, respectively, has a parasitic capacitance. here,
For convenience, only the first to third parasitic capacitances Ca, Cb, and Cx are shown. The first parasitic capacitance Ca is the silicon substrate 40.
And the first n ⁺ diffusion layer 40-1 and the second parasitic capacitance Cb are formed between the silicon substrate 40 and the second n ⁺ diffusion layer 40-2. The third parasitic capacitance Cx is
It is formed between the silicon substrate 40 and the third n ⁺ diffusion layer 40-3. The first to third parasitic capacitances Ca, Cb, and Cx have different capacitance values.

In addition to the above parasitic capacitance, the inverting amplifier circuit has a parasitic resistance because the silicon substrate 40 has a resistance component. Here, the first to fourth parasitic resistances R
w1, Rw2, Rw3 and Rw4 are shown. The first n ⁺ diffusion layer 40-1 and the p ⁺ diffusion layer 45 are connected via the first parasitic resistance Rw1 and the first parasitic capacitance Ca, and the second n ⁺ diffusion layer 40-2. And the p ⁺ diffusion layer 45 are connected via a second parasitic resistance Rw2 and a second parasitic capacitance Cb. The first n ⁺ diffusion layer 40-1 and the third n ⁺ diffusion layer 40-3 are connected via the third parasitic resistance Rw3 and the first parasitic capacitance Ca, and the second n ^+. The diffusion layer 40-2 and the third n ⁺ diffusion layer 40-3 are connected via a fourth parasitic resistance Rw4 and a second parasitic capacitance Cb.

If external noise enters through the p ⁺ diffusion layer 45, the potential of the silicon substrate 40 changes. Such a change in the potential is transmitted to the first n ⁺ diffusion layer 40-1 via the first parasitic resistance Rw1 and the first parasitic capacitance Ca, and also to the second parasitic resistance Rw2 and the second parasitic resistance Rw2. Is transmitted to the second n ⁺ diffusion layer 40-2 via the parasitic capacitance Cb. In this case, the first and second n ⁺ diffusion layers 40-1 and 40
-2, that is, the potentials of the first and second resistors 31 and 32 change. This means that the potential of the inverting input terminal 33-1 changes.

On the other hand, when the potential of the third n ⁺ diffusion layer 40-3, that is, the drain electrode changes with the operation of the MOS transistor Qn, this change is transmitted to the silicon substrate 40 through the third parasitic capacitance Cx. Therefore, also in this case, the potential of the silicon substrate 40 changes. This change in potential is transmitted to the first n ⁺ diffusion layer 40-1 via the third parasitic resistance Rw3 and the first parasitic capacitance Ca, and
It is transmitted to the second n ⁺ diffusion layer 40-2 via the fourth parasitic resistance Rw4 and the second parasitic capacitance Cb. Therefore,
Also in this case, the potentials of the first and second resistors 31 and 32 change. As a result, the potential of the inverting input terminal 33-1 changes.

Since the fluctuations in the potentials of the first and second resistors 31 and 32 are amplified by the differential amplifier circuit 33 together with the input signal input from the signal input terminal 34, the S / N of the inverting amplifier circuit is lowered. To do. The first and second resistance values R1 and R2 are 1 (kΩ) and 100 (kΩ), respectively, and the reference voltage V
When r and the input voltage Vi are 0 (V) and 10 (mV), respectively, the output voltage Vo is -1 (mV), assuming that there is no intrusion of external noise. On the other hand, if external noise of 1 (mV) is applied to the inverting input terminal 33-1 due to the first and second parasitic capacitances Ca and Cb, 100 (m)
V) noise is included in the output voltage Vo.

The above second method will be described with reference to FIG. 19, the same parts as those in FIG. 18 are designated by the same reference numerals and the description thereof will be omitted. That is, this inverting amplifier circuit is realized by the first and second polycrystalline silicon patterns 48-1 and 48-2 in which the first and second resistors 31 and 32 are formed on the field oxide film 41, respectively. It is the same as FIG. 18 except that it is described.

For the same reason as described with reference to FIG. 18, the inverting amplifier circuit has first to third parasitic capacitances Ca ', Cb', Cx 'caused by the field oxide film 41. The first parasitic capacitance Ca ′ is formed between the silicon substrate 40 and the first polycrystalline silicon pattern 48-1, and the second parasitic capacitance Cb is formed.
′ Is formed between the silicon substrate 40 and the second polycrystalline silicon pattern 48-2. The third parasitic capacitance Cx ′ is formed between the silicon substrate 40 and the third n ⁺ diffusion layer 40-3.

Generally, the field oxide film 41 has a thickness larger than that of other films, for example, the gate oxide film of a MOS transistor, in order to reduce the value of the parasitic capacitance in the wiring pattern formed thereon. There is. This means that the parasitic capacitance value per unit area is small. However, since the polycrystalline silicon pattern has a small sheet resistance value, a large area is required to use the polycrystalline silicon pattern as a resistor. This is the first to third parasitic capacitances C whose capacitance value cannot be ignored by the inverting amplifier circuit.
It means having a ', Cb', Cx '.

The first to third parasitic capacitances Ca ', Cb', C
In addition to x ′, the inverting amplifier circuit has first to fourth parasitic resistances R
It has w1 ', Rw2', Rw3 ', and Rw4'. The first parasitic resistance Rw1 ′ and the first parasitic capacitance Ca ′ are provided between the first polycrystalline silicon pattern 48-1 and the p ⁺ diffusion layer 45.
And a second polycrystalline silicon pattern 4 which is connected via
The second parasitic resistance Rw is provided between 8-2 and the p ⁺ diffusion layer 45.
2'and the second parasitic capacitance Ca 'are connected. The first polycrystalline silicon pattern 48-1 and the third n ⁺ diffusion layer 40-3 are connected via the third parasitic resistance Rw3 ′ and the first parasitic capacitance Ca ′, and the second Between the third polycrystalline silicon pattern 48-2 and the third n ⁺ diffusion layer 40-3 of the fourth parasitic resistance Rw4 ′ and the second parasitic capacitance Ca ′.
Connected via and.

When the external noise enters the p ⁺ diffusion layer 45, the potential fluctuations of the first and second resistors 31 and 32, that is, the inverting input terminal 33-1 are the same as described with reference to FIG.
Change of electric potential. On the other hand, even when the potential of the third n ⁺ diffusion layer 40-3 changes with the operation of the MOS transistor Qn, the potential of the inverting input terminal 33-1 also changes. As a result, the S / N ratio of the inverting amplifier circuit decreases as described with reference to FIG.

[0030]

As is apparent from the above description, in the semiconductor circuit device including the conventional differential amplifier circuit, when external noise enters the circuit, the differential capacitance is generated due to the parasitic capacitance. The input voltage of the amplifier circuit changes individually with a certain time difference in its amplitude. As a result, the amplitude of the output signal fluctuates greatly, which makes it difficult to output an output signal having a predetermined voltage.

Therefore, an object of the present invention is to provide a semiconductor circuit device which can reduce the influence of parasitic capacitance.

[0032]

According to the present invention, there is provided a differential amplifier circuit formed on a semiconductor substrate, the differential amplifier circuit having first and second input terminals and an output terminal. In addition, an input signal is supplied through the first resistor connected to the first input terminal, and the output terminal and the second terminal are connected.
In a semiconductor circuit device configured to feed back the output signal through a second resistor connected between the input terminal and the input terminal, the first resistor and the second resistor are formed on the semiconductor substrate, respectively. A wiring pattern formed in the wiring layer, and formed between the first resistor and the semiconductor substrate and the first parasitic capacitance formed between the first resistor and the semiconductor substrate. A semiconductor circuit device is obtained in which the second parasitic capacitance is formed to be equal to each other.

The semiconductor substrate may have a diffusion layer formed in a region below the first and second resistors.

Another wiring pattern may be formed on the wiring layer, and a conductor film may be formed in a region between the other wiring pattern and the first and second resistors.

A first contact hole may be connected between the diffusion layer and the conductor film, and a second contact hole may be connected between the conductor film and the other wiring pattern.

According to the present invention, there is also provided a differential amplifier circuit formed on a semiconductor substrate, the differential amplifier circuit comprising:
In a semiconductor circuit device including a second input terminal and a circuit element formed on the semiconductor substrate and connected to one of the first and second input terminals, the circuit element is adjacent to the circuit element on the semiconductor substrate. A dummy circuit element, and a first parasitic capacitance formed between the circuit element and the semiconductor substrate and a second parasitic capacitance formed between the dummy circuit element and the semiconductor substrate. Are equal to each other, and the dummy circuit element is connected to the other of the first and second input terminals to obtain a semiconductor circuit device.

The dummy circuit element is formed so that the cross-sectional shape and the planar shape thereof are the same as the cross-sectional shape and the planar shape of the circuit element, respectively.

The circuit element is one of a resistor, a capacitor and a transistor.

When the circuit element is a resistor, the resistor is formed as a diffusion layer on the semiconductor substrate.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. This embodiment is an example applied to the reference voltage circuit shown in FIG. 14, and the circuit configuration itself is the same as that of FIG. The characteristic of the reference voltage generating circuit according to the present embodiment is in how to form the first and second resistors 21 and 22.

In FIGS. 1 and 2, the reference voltage generating circuit is formed on the semiconductor substrate 50, but the third resistor 23 (FIG. 14) and the differential amplifier circuit 24 (FIG. 14) are omitted for convenience. ing. The first and second resistors 21 and 22 are connected to the wiring layer 5
It is realized by the first and second wiring patterns 51 and 52 formed in 3. The wiring layer 53 is made of an insulating material and is formed on the semiconductor substrate 50. This reference voltage generating circuit has a first
Has a first parasitic capacitance formed between the wiring pattern 51 and the semiconductor substrate 50, and a second parasitic capacitance formed between the second wiring pattern 52 and the semiconductor substrate 50.
What should be noted here is that the first and second wiring patterns 5
1 and 52 are formed such that the capacitance values of the first and second parasitic capacitances are equivalent to each other.

The semiconductor substrate 50 has a diffusion layer 50-1 formed on the upper portion thereof in all regions corresponding to the formation regions of the first and second wiring patterns 51 and 52. The diffusion layer 50-1 is for shielding an electric field caused by the semiconductor substrate 50, and is realized by an n ⁺ diffusion layer or a p ⁺ diffusion layer.

Since the capacitance values of the first and second parasitic capacitances due to the first and second wiring patterns 51 and 52 are equivalent to each other, the first and second parasitic capacitances are the first and second input potentials. P
1, P2 (FIG. 14) have the same effect. In this case, even if external noise enters the reference voltage generation circuit, the first and second input potentials P1 and P2 have the same fluctuations in amplitude and timing. As a result, the reference voltage generating circuit can generate an output signal without fluctuation of the output potential OP, as shown in FIG. The diffusion layer 50-1 is not an essential element and may be deleted.

A modification of the reference voltage generating circuit according to the present invention will be described with reference to FIG. In this example, the wiring layer 5
A third wiring pattern 57 is formed on the wiring layer 53,
It is the same as FIG. 2 except that a conductor film 56 is formed between the third wiring pattern 57 and the first and second wiring patterns 51 and 52 inside. In this example as well, the reference voltage generating circuit is formed on the semiconductor substrate 50, but the third resistor 23 (FIG. 14) and the differential amplifier circuit 24 (FIG. 14) are used.
Are omitted for convenience.

The third wiring pattern 57 is formed on the semiconductor substrate 5
Used for other circuits formed on the 0. The conductor film 56 is made of a metal material such as aluminum.
It is formed so as to cover the second wiring patterns 51 and 52. That is, the conductor film 56 acts as a shield layer for shielding the electric field caused by the third wiring pattern 57. In this way, in the first and second wiring patterns 51 and 52, the electric field caused by the semiconductor substrate 50 is shielded by the diffusion layer 50-1, and the electric field caused by the third wiring pattern 57 is caused by the conductor film 56. Shielded. This is because the reference voltage generating circuit of the present embodiment is similar to that shown in FIG.
It means that it is more stable in operation than the reference voltage generating circuit shown in FIG.

Another modification of the reference voltage generating circuit according to the present invention will be described with reference to FIG. In this example, the diffusion layer 50-1 and the conductor film 56 are connected by at least two contact holes (or through holes) 58, and the third wiring pattern 57 and the conductor film 56 are at least one contact. It is the same as the example of FIG. 4 except that it is connected by holes (or through holes) 59. By doing so, the diffusion layer 50-1, the conductor film 56, and the third wiring pattern 57 are held at the same potential. This potential is preferably the same as the ground potential. In this way, in this reference voltage generating circuit, the shield effect can be further improved as compared with the examples of FIGS. In addition,
Also in this example, the third resistor 23 (FIG. 14) and the differential amplifier circuit 2
4 (FIG. 14) is omitted for convenience.

An example in which the present invention is applied to the inverting amplifier circuit described with reference to FIG. 16 will be described with reference to FIG. This inverting amplifier circuit includes the first and second dummy resistors 6
16 is the same as the inverting amplifier circuit shown in FIG. 16 except that the resistors 1 and 62 are formed on a semiconductor substrate (not shown) adjacent to the first and second resistors 31 and 32. As described with reference to FIGS. 16 to 18, the inverting amplifier circuit includes the first
Formed between the resistor 31 and the silicon substrate 40 of the first
Parasitic capacitance Ca of the second resistor 32 and the silicon substrate 40
And a second parasitic capacitance Cb formed between and. As will be apparent later, the first dummy resistor 61 has the same sectional shape and plane shape as the first resistor 31. Similarly,
The second dummy resistor 62 has the same sectional shape and planar shape as the second resistor 32. As a result, the first dummy parasitic capacitance is formed between the first dummy resistor 61 and the silicon substrate, and the second dummy parasitic capacitance is formed in the second dummy resistor 6.
2 and the silicon substrate.

When the first resistor 31 is connected to the inverting input terminal 33-1 of the differential amplifier circuit 33, one end of the first dummy resistor 61 is connected to the non-inverting input terminal 33-2, The other end is opened. Similarly, the second resistor 32
Is also connected to the inverting input terminal 33-1 of the differential amplifier circuit 33, one end of the second dummy resistor 62 is connected to the non-inverting input terminal 33-2 and the other end is opened.

Referring to FIG. 7, this inverting amplifier circuit is the same as that shown in FIG. 18 except for the following points. That is, the sixth and seventh openings 41 in which the first and second n ⁺ dummy diffusion layers 66 and 67 are provided in the field oxide film 41.
Formed on the silicon substrate 40 through -6 and 41-7,
Moreover, one ends of the first and second n ⁺ dummy diffusion layers 66 and 67 are connected to the non-inverting input terminal 33-2 through the aluminum wiring patterns 68 and 69, respectively. Needless to say, the first and second n ⁺ dummy diffusion layers 66 and 67 act as the first and second dummy resistors 61 and 62, respectively. The above-mentioned first and second dummy parasitic capacitances are shown by Cad and Cbd in FIG. 7, respectively.

As described with reference to FIG. 18, the first n
^{The +} diffusion layer 40-1 and the p ⁺ diffusion layer 45 are connected via the first parasitic resistance Rw1 and the first parasitic capacitance Ca, and the second n ⁺ diffusion layer 40-2 and the p ⁺ diffusion layer are connected. 45 is connected via the second parasitic resistance Rw2 and the second parasitic capacitance Cb. A first ^{n +} diffusion layer 40-1 and the third ^{n +} diffusion layer 40-3 are connected through a third parasitic resistor Rw3 and the first parasitic capacitance Ca, the second ^{n +} diffusion Layer 40-2
And the third n ⁺ diffusion layer 40-3 form a fourth parasitic resistance Rw.
4 and the second parasitic capacitance Cb.

Similarly, the first n ⁺ dummy diffusion layer 66 and p
^{The +} diffusion layer 45 is connected via the first dummy parasitic resistance Rwd1 and the first dummy parasitic capacitance Cad, and the second n ⁺ dummy diffusion layer 67 and the p ⁺ diffusion layer 45 are connected to each other. The dummy parasitic resistance Rwd2 is connected to the second parasitic capacitance Cbd. The first n ⁺ dummy diffusion layer 66 and the third
N ⁺ diffusion layer 40-3 of the third dummy parasitic resistance Rw
The second n ⁺ dummy diffusion layer 67 and the third n ⁺ diffusion layer 4 are connected to each other via d3 and the first dummy parasitic capacitance Cad.
0-3 are connected via a fourth dummy parasitic resistance Rwd4 and a second dummy parasitic capacitance Cbd.

It should be noted here that, as described above, the first resistance 31 and the first dummy resistance 66 are equivalent to each other, so that the first parasitic capacitance Ca and the first dummy parasitic capacitance Cad. Have substantially the same capacitance value, and the first parasitic resistance R
This means that w1 and the first dummy parasitic resistance Rwd1 have almost the same resistance value. Similarly, the second parasitic capacitance Cb
And the second dummy parasitic capacitance Cab have substantially the same capacitance value, and the second parasitic resistance Rw2 and the second dummy parasitic resistance Rw
The resistance value is almost equal to d2. This is the third parasitic resistance R
The same applies to w3 and the third dummy parasitic resistance Rwd3, and the fourth parasitic resistance Rw4 and the fourth dummy parasitic resistance Rwd4.

A first example of a method of forming the first n ⁺ diffusion layer 40-1 and the first n ⁺ dummy diffusion layer 66 in the inverting amplifier circuit of the present invention will be described with reference to FIG. The following method is also applied to the second n ⁺ diffusion layer 40-2 and the second n ⁺ dummy diffusion layer 67. In FIG. 8, a first n ⁺ diffusion layer 40-1 and a first n ⁺ dummy diffusion layer 66 are formed adjacent to each other and in parallel. As described above, the first n ⁺ diffusion layer 40-1 and the first n ⁺ dummy diffusion layer 66 have the same sectional shape and planar shape. One end of the first n ⁺ diffusion layer 40-1 is connected to the signal input terminal 3 via the aluminum wiring pattern 42-1 (only a part is shown).
4 (FIG. 6). First n ⁺ diffusion layer 40-
The other end of 1 is connected to the inverting input terminal 33-1 via an aluminum wiring pattern 42-2 (only a part is shown). One end of the first n ⁺ dummy diffusion layer 66 is connected to the non-inverting input terminal 33-2 via the aluminum wiring pattern 68 (only a part is shown). The other end of the first n ⁺ dummy diffusion layer 66 is open.

In practice, the first n ⁺ diffusion layer 40-1 and the first n ⁺ dummy diffusion layer 66 are the same as the field oxide film 41.
Together with it, it is covered with an insulating layer 70. In this case, both ends of the first n ⁺ diffusion layer 40-1 are respectively passed through the contact holes 71 and 72 formed by penetrating the insulating layer 70.
It is connected to the upper aluminum wiring patterns 42-1 and 42-2. Similarly, the first n ⁺ dummy diffusion layer 66 is connected to the aluminum wiring pattern 68 on the insulating layer 70 through a contact hole 73 formed through the insulating layer 70.

A second example of a method of forming the first n ⁺ diffusion layer 40-1 and the first n ⁺ dummy diffusion layer 66 in the inverting amplifier circuit of the present invention will be described with reference to FIG. First n ⁺ diffusion layer 40-1 and first n ⁺ dummy diffusion layer 66
And are formed parallel to each other. For the sake of convenience, the insulating layer 70 shown in FIG. 8 is not shown. Needless to say, the first n ⁺ diffusion layer 40-1 and the first n ⁺ dummy diffusion layer 66 have the same sectional shape and planar shape. In this example, the aluminum wiring pattern 68 extends to the other end of the first n ⁺ dummy diffusion layer 66, and
The n ⁺ dummy diffusion layer 66 is short-circuited at its both ends by the aluminum wiring pattern 68 by the contact holes 73 and 74. The other structure is the same as that of FIG.

A third example of a method of forming the first n ⁺ diffusion layer 40-1 and the first n ⁺ dummy diffusion layer 66 in the inverting amplifier circuit of the present invention will be described with reference to FIG.
First n ⁺ diffusion layer 40-1 and first n ⁺ dummy diffusion layer 6
6 and 6 are formed adjacent to each other and in parallel. For convenience,
The insulating layer 70 shown in FIG. 8 is not shown. Of course,
First n ⁺ diffusion layer 40-1 and first n ⁺ dummy diffusion layer 6
6 has the same sectional shape and plane shape. In this example, the aluminum wiring pattern 68 extends to the middle portion of the first n ⁺ dummy diffusion layer 66, the first n ⁺ dummy diffusion layer 66 contact holes 75 in the intermediate section
Is connected to the aluminum wiring pattern 68. The other structure is the same as that of FIG.

Returning to FIG. 7, the external noise is p ⁺ diffusion layer 4
The case of invading 5 will be described. In this case, the potential of the silicon substrate 40 changes as described with reference to FIG. Such a change in potential is caused by the first parasitic resistance R
It is transmitted to the first n ⁺ diffusion layer 40-1 via w1 and the first parasitic capacitance Ca, and is also transmitted to the second n ⁺ via the second parasitic resistance Rw2 and the second parasitic capacitance Cb. Diffusion layer 40-
2 is transmitted. In this case, the inverting terminal 33-1 is the first,
Since it is connected to the second n ⁺ diffusion layers 40-1 and 40-2, the potential of the inverting terminal 33-1 changes.

On the other hand, the fluctuation of the potential caused by the p ⁺ diffusion layer 45 is transmitted to the first n ⁺ dummy diffusion layer 66 via the first dummy parasitic resistance Rwd1 and the first dummy parasitic capacitance Cad. At the same time, it is transmitted to the second n ⁺ dummy diffusion layer 67 via the second dummy parasitic resistance Rwd2 and the second dummy parasitic capacitance Cbd. In this case, the non-inverting terminal 33-
2 is connected to the first and second n ⁺ dummy diffusion layers 66 and 67, the potential of the non-inverting terminal 33-2 fluctuates.

As described above, the first and second parasitic resistances R
w1, Rw2 and the first and second dummy parasitic resistances Rwd1,
The resistance values of Rwd2 are substantially equal to each other. The capacitance values of the first and second parasitic capacitances Ca and Cb and the first and second dummy parasitic capacitances Cad and Cbd are substantially equal to each other. In this case, even if external noise enters the p ⁺ diffusion layer 45, the inverting terminal 33-1 and the non-inverting terminal 33-2 have the same amplitude and timing (phase) fluctuations. This means that even if the potential of the silicon substrate 40 fluctuates due to external noise, the fluctuation of the output voltage Vo is reduced to the common-mode rejection ratio.

Next, when the potential of the third n ⁺ diffusion layer 40-3, that is, the drain electrode changes with the operation of the MOS transistor Qn, this change is transmitted to the silicon substrate 40 through the third parasitic capacitance Cx. Therefore, in this case also, the potential of the silicon substrate 40 changes. This change in potential is transmitted to the first n ⁺ diffusion layer 40-1 via the third parasitic resistance Rw3 and the first parasitic capacitance Ca, and
It is transmitted to the second n ⁺ diffusion layer 40-2 via the fourth parasitic resistance Rw4 and the second parasitic capacitance Cb. Therefore,
Also in this case, the potential of the inverting terminal 33-1 changes.

On the other hand, the fluctuation of the potential caused by the third n ⁺ diffusion layer 40-3 is caused by the third dummy parasitic resistance Rwd3 and the first dummy parasitic resistance Rwd3.
Is transmitted to the first n ⁺ dummy diffusion layer 66 via the dummy parasitic capacitance Cad of
It is transmitted to the second n ⁺ dummy diffusion layer 67 via wd4 and the second dummy parasitic capacitance Cbd. In this case, the potential of the non-inverting terminal 33-2 changes.

As described above, the third and fourth parasitic resistances R
w3, Rw4 and third and fourth dummy parasitic resistances Rwd3,
The resistance values of Rwd4 are almost equal to each other. In this case, even if the potential of the silicon substrate 40 changes due to the third n ⁺ diffusion layer 40-3 due to external noise, the inverting terminal 33-1 and the non-inverting terminal 33-2 have the same amplitude and timing ( Phase) fluctuation. As a result, even if the potential of the silicon substrate 40 fluctuates due to external noise, the fluctuation of the output voltage Vo is reduced to the common mode rejection ratio.

Here, the first and second resistance values R1 and R2 are 1 (kΩ) and 100 (kΩ), respectively, and the reference voltage Vr and the input voltage Vi are 0 (V) and 10 (mV), respectively.
And If a potential fluctuation of 1 (mV) occurs at the inverting terminal 33-1 due to the potential fluctuation of the silicon substrate 40, a potential fluctuation of 1 (mV) also occurs at the non-inverting terminal 33-2. Assuming that the differential amplifier circuit 33 has a common mode signal rejection ratio of 80 dB, the fluctuation of the output voltage Vo is 0.01 mV.
Is reduced to. Such variation of the output voltage Vo is much lower than that shown in FIG.

It goes without saying that the present invention can be applied to the inverting amplifier circuit having the structure shown in FIG.

Although the above description is for the inverting amplifier circuit,
The present invention can also be applied to a non-inverting amplifier circuit. In this case, the signal input terminal 34 is used as a voltage input terminal for receiving the offset voltage of the constant voltage Vc, and the reference voltage input terminal 35 is used as a signal input terminal for receiving the input signal having the signal voltage Vs. The output voltage Vo of the output signal is given by the following equation.

Vo = (1+ (R2 / R1)) Vs- (R2 / R1) Vc In any case, the non-inverting amplifier circuit has a stable output without lowering S / N due to potential fluctuation in the semiconductor substrate. Can output signals.

Further, in addition to the first and second resistors 31 and 32, a plurality of resistors similar to the first resistor 31 and acting as signal input resistors may be provided. In this case, a plurality of dummy resistors are formed so as to be adjacent to the plurality of resistors, respectively. Such an inverting amplifier circuit can be applied as an adding circuit.

A case where the present invention is applied to an analog inverting amplifier circuit will be described with reference to FIG. This analog inverting amplifier circuit differs from the inverting amplifier circuit shown in FIG. 6 in the following points, and the rest of the configuration is the same. That is,
The third resistor 78 is connected to the reference voltage input terminal 35 and the non-inverting terminal 3
3-2, and the third dummy resistor 79 is connected to the third
Is formed adjacent to the resistor 78. As we all know,
The third resistor 78 is a resistor for reducing the input offset.

Needless to say, the third dummy resistor 79 has the same sectional shape and the same plane shape as the third resistor 78. One end of the third dummy resistor 79 has a third resistor 78.
Is connected to the non-inverting terminal 33-2, and thus is connected to the inverting terminal 33-1. The other end of the third dummy resistor 79 is open. For the same reason explained in FIG. 7,
This analog inverting amplifier circuit can also prevent a decrease in S / N due to the potential fluctuation of the semiconductor substrate.

A case where the present invention is applied to an integrating circuit will be described with reference to FIG. This integration circuit has the same components as the inverting amplification circuit except for the n-channel MOS transistor Q11, the dummy MOS transistor Qd11, the capacitor C11 having the capacitance value C, the dummy capacitor Cd11, and the reset circuit 80.

As described above, the first dummy resistor 61
Is formed adjacent to the first resistor 31, and the first resistor 3 is formed.
It has the same sectional shape and plane shape as No. 1. Similarly, the dummy MOS transistor Qd11 is formed adjacent to the MOS transistor Q11, and is connected to the MOS transistor Q1.
It has the same sectional shape and plane shape as No. 1. The dummy capacitor Cd11 is formed adjacent to the capacitor C11 and has the same sectional shape and plane shape as the capacitor C11.

The MOS transistor Q11 is for discharging the electric charge accumulated in the capacitor C11 when the integrating circuit is reset. For this purpose, the gate electrode of the MOS transistor Q11 is connected to the reset circuit 80. In other words, the MOS transistor Q1
1 is turned on by the reset circuit 80 when the integrating circuit is reset. In this example, the MOS transistor Q
Since the source electrode of 11 is connected to the inverting terminal 33-1, the source electrode of the dummy MOS transistor Qd11 is connected to the non-inverting terminal 33-2. Dummy MOS
The drain electrode of the transistor Qd11 is open. The gate electrode of the dummy MOS transistor Qd11 is connected to the reset circuit 80. Similarly, since one end of the capacitor C11 is connected to the inverting terminal 33-1, one end of the dummy capacitor Cd11 is connected to the non-inverting terminal 33-2. Dummy capacitor Cd1
The other end of 1 is open.

When the MOS transistor Q11 is turned off, the output voltage Vo is expressed by the following equation.

Vo = −1 (1 / C · R1) · Vidt In this way, the integrating circuit executes the integrating operation.

The structure of the integrating circuit shown in FIG. 12 will be described with reference to FIG. The silicon substrate 40 includes a first n ⁺ diffusion layer 40-1 and a first n ⁺ dummy diffusion layer 66.
And are formed adjacent to each other. Capacitor C11
And the dummy capacitor Cd11 are also formed on the silicon substrate 40 so as to be adjacent to each other. Furthermore, the MOS transistor Q11 and the dummy MOS transistor Qd11 are also
The silicon substrates 40 are formed adjacent to each other. Although not shown, it is assumed here that the p ⁺ diffusion layer 45 and the MOS transistor Qn are formed on the silicon substrate 40 as in FIG. 7.

As described with reference to FIG. 7, the first parasitic capacitance Ca is equal to the first n ⁺ diffusion layer 40-1 and the silicon substrate 4.
0 and a first dummy parasitic capacitance Cad having the same capacitance value as the first parasitic capacitance Ca is formed between the first n ⁺ dummy diffusion layer 66 and the silicon substrate 40. The third parasitic capacitance Cc is the capacitor C11 and the silicon substrate 4
A third dummy parasitic capacitance Ccd having the same capacitance value as that of the third parasitic capacitance Cc is formed between the dummy capacitor Cd11 and the silicon substrate 40. Similarly, a fourth parasitic capacitance Cd is formed between the source region 81 of the MOS transistor Q11 and the silicon substrate 40,
A fourth dummy parasitic capacitance Cdd having the same capacitance value as the fourth parasitic capacitance Cd is formed between the dummy source region 82 of the dummy MOS transistor Qd11 and the silicon substrate 40. The source region 81 and the dummy source region 82 are each realized by an n ⁺ diffusion layer.

The first n ⁺ diffusion layer 40-1 is connected to the p ⁺ diffusion layer 4 via the first parasitic resistance Rw1 and the first parasitic capacitance Ca.
5 (FIG. 7) and the third parasitic resistance Rw
3, the third n ⁺ diffusion layer 40 via the first parasitic capacitance Ca
-3 (FIG. 7). First n ⁺ dummy diffusion layer 6
6 is connected to the p ⁺ diffusion layer 45 via the first dummy parasitic resistance Rwd1 and the first dummy parasitic capacitance Cad, and via the third dummy parasitic resistance Rwd3 and the first dummy parasitic capacitance Cad. It is connected to the third n ⁺ diffusion layer 40-3. This is capacitor C11 and dummy capacitor C
Also applies to d11, the MOS transistor Q1
The same applies to 1 and the dummy MOS transistor Qd11.

For example, the capacitor C11 has a parasitic resistance R
The parasitic resistance Rc2 and the third parasitic capacitance Cc are connected to the p ⁺ diffusion layer 45 via the c1 and the third parasitic capacitance Cc.
Is connected to the third n ⁺ diffusion layer 40-3 via.

For the same reason as described with reference to FIG. 7, when the potential of the silicon substrate 40 changes due to the p ⁺ diffusion layer 45, this potential change causes the first parasitic resistance Rw1 and the first parasitic capacitance. It is transmitted to the first n ⁺ diffusion layer 40-1 via Ca. This potential fluctuation is also transmitted to the capacitor C11 via the parasitic resistance Rc1 and the third parasitic capacitance Cc. This potential fluctuation is further caused by the parasitic resistance Rq1 and the fourth parasitic capacitance C.
It is transmitted to the source region 81 via d. These potential fluctuations cause potential fluctuations at the inverting terminal 33-1.

On the other hand, the potential fluctuation of the silicon substrate 40 caused by the p ⁺ diffusion layer 45 is caused by the first dummy parasitic resistance R.
wd1, the first n through the first dummy parasitic capacitance Cad
⁺ Transmitted to the dummy diffusion layer 66. This potential fluctuation also causes the dummy parasitic resistance Rcd1 and the third dummy parasitic capacitance C
It is transmitted to the dummy capacitor Cd11 via cd.
This potential fluctuation is further transmitted to the dummy source region 82 via the dummy parasitic resistance Rqd1 and the fourth dummy parasitic capacitance Cdd. These potential fluctuations are caused by the non-inverting terminal 33-2.
Cause potential fluctuations. The potential fluctuation of the inverting terminal 33-1 is the same as that explained in FIG.
2 is the same in potential fluctuation, amplitude, and timing (phase). This means that even if the silicon substrate 40 changes in potential due to external noise, the change in the output voltage Vo is reduced to the common-mode rejection ratio.

This also applies to the case where the potential of the third n ⁺ diffusion layer 40-3 (FIG. 7), that is, the drain electrode, changes with the operation of the MOS transistor Qn. In this case, the third dummy parasitic resistance Rwd3 and the parasitic resistance Rc2
And Rq2, dummy parasitic resistances Rcd2 and Rqd2,
First parasitic resistance Rw1, first dummy parasitic resistance Rwd
1, parasitic resistances Rc1 and Rq1, dummy parasitic resistance Rcd
1 and Rqd1 are applied instead.

[0082]

As described above, according to the present invention, it is possible to provide a semiconductor circuit device having an excellent S / N ratio, which is unlikely to be affected by the potential fluctuation of the semiconductor substrate due to external noise or the like.

[Brief description of drawings]

FIG. 1 is a plan view of a main part for explaining a relationship between two resistors included in a case where the present invention is applied to a reference voltage generating circuit.

FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG.

3 is a waveform diagram for explaining the relationship between the potentials of the two input terminals and the potentials of the output terminals of the differential amplifier circuit included in the reference voltage generation circuit in the embodiment of FIG.

FIG. 4 is a cross-sectional view showing a modified example of the example shown in FIG.

5 is a cross-sectional view showing another modified example of the example shown in FIG.

FIG. 6 is a circuit diagram when the present invention is applied to an inverting amplifier circuit.

7 is a diagram showing a cross-sectional structure of a main part of the inverting amplifier circuit shown in FIG.

FIG. 8 is a diagram for explaining a first example of a method of forming the two n ⁺ diffusion layers shown in FIG.

9 is a diagram for explaining a second example of the method for forming the two n ⁺ diffusion layers shown in FIG. 7. FIG.

10 is a diagram for explaining a third example of the method for forming the two n ⁺ diffusion layers shown in FIG. 7. FIG.

FIG. 11 is a circuit diagram when the present invention is applied to an analog inverting amplifier circuit.

FIG. 12 is a circuit diagram when the present invention is applied to an integrating circuit.

13 is a diagram showing a cross-sectional structure of a main part of the integrating circuit shown in FIG.

FIG. 14 is a diagram showing a reference voltage generating circuit to which the present invention is applied.

FIG. 15 is a waveform diagram for explaining the relationship between the potentials of the two input terminals and the potential of the output terminal of the differential amplifier circuit included in the reference voltage generation circuit of FIG.

FIG. 16 is a diagram showing an inverting amplifier circuit to which the present invention is applied.

17 is a circuit diagram of a differential amplifier circuit included in the inverting amplifier circuit shown in FIG.

FIG. 18 is a circuit diagram of 2 included in the inverting amplifier circuit shown in FIG.
It is the figure which showed the cross-section of the principal part in case one resistance is implement | achieved by an n ⁺ diffusion layer.

FIG. 19 is a circuit diagram of 2 included in the inverting amplifier circuit shown in FIG.
It is the figure which showed the cross-section of the principal part when one resistance is implement | achieved by a polycrystalline silicon film.

[Explanation of symbols]

 40 Silicon substrate 50 Semiconductor substrate 50-1 Diffusion layer 51 First wiring pattern 52 Second wiring pattern 53 Wiring layer 56 Conductor film 57 Third wiring pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/06 27/08 331 Z 9170-4M // H03F 3/45 B

Claims (8)

[Claims] 1. A differential amplifier circuit formed on a semiconductor substrate, wherein the differential amplifier circuit has first and second input terminals and an output terminal, and the first input terminal is connected to the first input terminal. An input signal is supplied through a connected first resistor, and the output signal is fed back through a second resistor connected between the output terminal and the second input terminal. In the semiconductor circuit device, the first and second resistors are formed in a wiring pattern in a wiring layer formed on the semiconductor substrate, respectively, and are formed between the first resistor and the semiconductor substrate. The first parasitic capacitance, the second resistance, and the second parasitic capacitance formed between the semiconductor substrate and the semiconductor substrate are formed to be equal to each other. 2. The semiconductor circuit device according to claim 1, wherein the semiconductor substrate has a diffusion layer formed in a region below the first and second resistors. 3. The semiconductor circuit device according to claim 2, wherein another wiring pattern is formed on the wiring layer, and in a region between the other wiring pattern and the first and second resistors. A semiconductor circuit device having a conductor film formed thereon. 4. The semiconductor circuit device according to claim 3, wherein the diffusion layer and the conductor film are connected by a first contact hole, and the conductor film and the other wiring pattern are connected by a second contact hole. A semiconductor circuit device characterized by being connected through contact holes of. 5. A differential amplifier circuit formed on a semiconductor substrate, the differential amplifier circuit being formed on the first and second input terminals and the semiconductor substrate, the first and second input terminals. In a semiconductor circuit device including a circuit element connected to one of input terminals, a dummy circuit element is formed adjacent to the circuit element on the semiconductor substrate, and is formed between the circuit element and the semiconductor substrate. The first parasitic capacitance and the second parasitic capacitance formed between the dummy circuit element and the semiconductor substrate are equal to each other, and the dummy circuit element is connected to the first and second inputs. A semiconductor circuit device characterized by being connected to the other terminal. 6. The semiconductor circuit device according to claim 5, wherein the dummy circuit element is formed such that the cross-sectional shape and the planar shape thereof are the same as the cross-sectional shape and the planar shape of the circuit element, respectively. A semiconductor circuit device characterized by: 7. The semiconductor circuit device according to claim 5, wherein the circuit element is any one of a resistor, a capacitor, and a transistor. 8. The semiconductor circuit device according to claim 7, wherein the circuit element is a resistor, and the resistor is formed of a diffusion layer on the semiconductor substrate.