JPH07146790A - Alteration processing system for firmware program - Google Patents

Abstract

PURPOSE:To alter a firmware program without exchanging a ROM by copying the firmware program stored in the ROM in a RAM and rewriting the firmware program on the RAM. CONSTITUTION:A microprocessor 201 controls a device 3 to be controlled based on a control instruction transmitted from a central processing unit 1 and the firmware program stored in a ROM 202. A RAM 203 having storage capacity sufficient for accumulating the content of the ROM 202 is provided. The content of the ROM 202 is copied in the RAM 203 at the operation time of initialization. A write circuit 200 rewrites the content of the firmware program copied in the RAM 203 by a control instruction indicating the rewriting of the firmware program from the central processing unit 1. The microprocessor 201 is operated by the firmware program copied in RAM 203.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a firmware program change processing method for a device using a microprocessor, and more particularly to a read-only memory (a read-only storage element, which stores a firmware program,
The present invention relates to a firmware program change processing method for changing a firmware program without replacing (hereinafter referred to as ROM).

[0002]

2. Description of the Related Art Conventionally, in a device using a microprocessor, a means for changing a firmware program is an R which stores the firmware program.
Generally, the OM is dealt with by replacing it with a ROM in which a new firmware program is stored, and even a small change is dealt with by replacing the ROM.

Further, two kinds of random access memories (read / write storage elements, hereinafter referred to as RAM) are provided in association with the ROM, and auxiliary data having data indicating validity / invalidity of the contents data of the ROM are provided. RAM,
Japanese Unexamined Patent Publication No. 1-222099 discloses a technique for artificially changing the content data of the ROM by an external RAM that stores different data to be output in place of the content data of the corresponding address of the ROM when the auxiliary RAM is invalidly displayed. It is disclosed.

[0004]

In a device represented by an exchange, load distribution and function distribution are achieved by using a large number of control devices of the same type or different types controlled by a microprocessor, and these distributed control is performed. The firmware program in the device cooperates with the software program of the central controller to perform various functional operations.

Therefore, in a device typified by such an exchange, the conventional firmware program changing means changes the R function each time the firmware program is changed in order to change or add a function of the control device.
Since the OM is replaced, there is a problem that a large number of ROMs are required for the entire apparatus and a large amount of money is required for the ROM replacement.

Further, in a device represented by an exchange, a program of a lower-order device control portion related to a software program of a central control device is also changed at the same time as a firmware program of each decentralized control device is changed. If it is not changed, it is not possible to realize the function operation by the harmony of the firmware program and the software program as a whole in the whole apparatus. There was a problem that different kinds of change work, such as change of, had to be performed synchronously.

Further, in the technique disclosed in Japanese Patent Application Laid-Open No. 1-220299, the validity / invalidity of the data of the corresponding address stored in the ROM is displayed on the auxiliary RAM, and the external RAM is displayed on the basis of the display. Since the data is changed pseudo using the accumulated data,
Although it is effective in dealing with small-scale data changes, it cannot deal with complicated changes such as changing the functions or adding functions of the firmware program of the microprocessor of the control equipment used in the exchange. There are drawbacks.

The present invention has been made to solve the above problems, and it is an object of the present invention to obtain a firmware program change processing method for changing a firmware program without replacing the ROM storing the firmware program. To aim.

[0009]

A firmware program change processing system according to the present invention comprises a microprocessor,
Having a firmware program stored in ROM, the microprocessor is located between the higher-level control device and the controlled device, and the microprocessor is controlled based on the control command and the firmware program transmitted from the higher-level control device. A change processing method in a control device for controlling the device, and as a means for solving the problem, a RAM having a sufficient storage capacity for accumulating the contents of the ROM storing the firmware program, and an initial setting operation , ROM
When the control command transmitted from the host controller is an instruction to rewrite the firmware program, the contents of the firmware program copied to the RAM during the initial setting operation according to the contents of the control command. And a writing means for rewriting the above, and the microprocessor is operated by the firmware program copied to the RAM.

Further, the control command transmitted from the host controller can identify the control command for the microprocessor and the command for instructing the rewriting of the firmware program by the identifier.

[0011]

When the control device is initialized by turning on the power, etc., all firmware programs stored in the ROM are read.
After copying to AM, the microprocessor controls by the firmware program copied to this RAM.

As a result, by transmitting a change command from the host controller and rewriting the firmware program on the RAM, the change of the firmware program is performed by the RO.
M can be carried out without replacement.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the concept of function distribution control of an exchange to which an embodiment of the present invention is applied.

The central control unit 1 has a CPU based on an exchange software program stored in the storage unit 11.
10 executes the exchange control operation of the exchange, and the control equipment 2 represented by the subscriber control equipment 21, the communication path control equipment 22 and the signal control equipment 23 is the subscriber control equipment as each controlled equipment 3. Reference numeral 21 designates a calling subscriber 40, a called subscriber 41, a first subscriber circuit 30 and a second subscriber circuit 31, a speech path control device 22 a speech path device 32 forming a speech path, and a signal control device 23. Controls REC 33 for signal reception and TONE 34 for signal tone transmission such as dial tone and ringing tone.

Based on the control instruction information signal S11, S12 or S13 transmitted from the central control device 1, the control device 2 controls the control target device 3 by a microprocessor and a firmware program for controlling the control signal S21. , S22 or S23, and supervisory signals S31, S3
2 or S33 is used for control and monitoring, and the control result and monitoring information are sent to the central control unit 1 by the report information signal S10.
As a result, a harmonious exchange control operation is performed as a whole.

An outline of the exchange operation executed in the exchange by the cooperation of the exchange software program and the firmware program included in the control equipment under the above-mentioned equipment configuration will be described below.

When the calling subscriber 40 makes a call, the calling state is detected by the scan operation of the first subscriber circuit 30 performed by the firmware program in the subscriber control unit 21 (monitoring signal S31). The call detection information is transmitted to the central controller 1 by a report information signal S10 having a predetermined information format.

In the central controller 1, a software program for calling connection is executed on the basis of the call detection information received from the subscriber controller 21, and the call path P1 of the call path device 32 is transmitted to the call path controller 22. And the control instruction information signal S12 to form the communication path P2, and the control instruction information signal S13 to the signal control device 23 so as to report the reception of the selected digit from the calling subscriber 40.
Instruct.

The microprocessor and the firmware program of each control device analyze these control instruction information,
The call path control device 22 sends the control signal S22 to the call path device 3
Then, the signal control device 23 prepares to receive the REC 33.

Subsequently, the selection signal from the calling subscriber 40 received by the REC 33 is sequentially detected by the supervisory signal S33 by the microprocessor and the firmware program of the signal control device 23, and the calling subscriber information is added to the central signal. The report information signal S10 is transmitted to the control device 1.

Upon receiving the selection signal information, the central control device 1 executes the selection signal information translation software program, selects the called subscriber 41 as a connection partner, and then instructs each control device by the call connection program. To prepare for connection between the calling subscriber 40 and the called subscriber 41.

A call path (not shown) for supplying a ringing tone to the calling subscriber 40 is connected to the call path control device 22, and a call path P3 for connecting the calling subscriber 40 and the called subscriber 41 is reserved. (Note that the communication path P2 and the communication path P1 are released upon receipt of the release instruction at the time of receiving the first numeral and at the completion of receiving the numeral).
And the call control signal 3 is sent to the subscriber control device 21.
6 is connected to the second subscriber circuit 31 and is instructed by the control instruction information signal S11 to report the response of the terminating subscriber 41.

In each control device, the control instruction information from the central control unit 1 is analyzed by the microprocessor and the firmware program, and the communication path control unit 22 is controlled by the control signal S22 and the subscriber control unit 21 is controlled by the control signal S21. Corresponding control is performed for each controlled device.

After this, when the called subscriber 41 responds, the subscriber control device 2 which has monitored it (monitoring signal S31)
1 reports it to the central control unit 1 by means of a report information signal S10, and the central control unit 1 executes a call control software program corresponding to the incoming subscriber response, and the calling subscriber 4
0 and the connection operation of the called subscriber 41 is performed.

The central controller 1 releases the call path (not shown) for supplying the ringing tone to the calling subscriber 40 to the call path controller 22 and connects the reserved call path P3. Instructed by the control instruction information signal S12, the calling signal 36 connected to the second subscriber circuit 31 is disconnected to the subscriber control device 21, and the polarity of the call line of the calling subscriber 40 is reversed. Is instructed by the control instruction information signal S11 to perform the necessary operation of the first subscriber circuit 30 before the start of the call.

Based on the instruction, the speech path controller 22
The subscriber control device 21 controls the speech path device 32, the second subscriber circuit 31, and the first subscriber circuit 30 by controlling the respective microprocessors and firmware programs.

In this way, in the exchange, the main exchange control is executed by the central control unit, but the operation control of various peripheral devices necessary for the exchange operation is closely linked with the software program of the central control unit. Originally, they are distributed and executed by various control devices using a microprocessor.

A firmware program executed by the control device by the microprocessor is usually stored in the ROM, and the present invention stores the ROM program even when these firmware programs need to be changed due to a function change or a function addition. It allows the firmware program to be changed without replacement.

FIG. 2 is a block diagram showing a firmware program change processing system of a control device according to an embodiment of the present invention.

The control device 20 is an example of the control device 2 which collectively refers to the subscriber control device 21, the communication path control device 22 or the signal control device 23 in FIG. 1, and stores a microprocessor 201 and a firmware program. One or more ROMs 202, a RAM 203 having a storage capacity sufficient to copy and store the contents of these ROMs, and the contents of the ROM 202 to the RAM 203 when the controller 20 is turned on or other reset operation is performed. -Then
Further, it comprises a writing circuit 200 which changes the firmware program on the RAM 203 based on the firmware program change control instruction information transmitted from the central control unit 1.

The writing circuit 200 is interworking with the central control unit 1, receives various control instruction information signals transmitted from the central control unit 1 described with reference to FIG. 1, and is controlled by the microprocessor 201. It also relays a report information signal that informs the central controller 1 of the result of monitoring or controlling the target device 3.

Further, the microprocessor 201 uses the firmware program copied on the RAM 203 as a firmware program for performing its control operation.

In the firmware program change processing system according to the present invention, the control instruction information signal transmitted from the central control unit 1 to the control unit 20 is added to the control instruction information relating to the normal exchange operation control. Firmware program change control instruction information is provided, which can be identified by an identifier indicating a control instruction type that constitutes a control instruction information signal.

The control instruction information signal transmitted to the control device 20 is received by the writing circuit 200 and is relayed to the microprocessor 201 if it is the control instruction information relating to the normal exchange operation control. When the writing circuit 200 identifies the change control instruction information, the write circuit 200 performs R based on the address and the change information included in the change instruction information.
The AM 203 is accessed to rewrite the information of the corresponding address with the change information.

The operation of the firmware program change processing system according to the present invention will be described in more detail with reference to FIG.

FIG. 3 is a block diagram showing the function of the writing circuit of the firmware program change processing system of the control device according to the embodiment of the present invention.

The write circuit 200 includes a reset control circuit 20.
01, a counter update timing circuit 2002, an address counter circuit 2003, and a refresh control circuit 2
004, selection circuit 2005 and instruction analysis circuit 2006
It consists of and.

The reset control circuit 2001 includes the control device 2
The contents of the ROM 202 are received by the RAM 203 upon receiving these reset signals at the time of power-on of 0 or other reset operation.
Control for starting the copy operation or for stopping the copy operation upon receipt of a count end report of all addresses from the address counter circuit 2003.

The counter update timing circuit 2002 is
The memory is activated by the reset control circuit 2001 and corresponds to a memory address (corresponding to a read address in the ROM 202, RA
M03 is a circuit for generating a timing clock that controls updating (corresponding to a write address).

The address counter circuit 2003 sequentially instructs memory control address information to the refresh control circuit based on the timing clock generated from the counter update timing circuit 2002, and resets it when the counting of all addresses is completed. 2001
Report to.

The refresh control circuit 2004 sends read address information and control information such as read control timing to the ROM 202 based on the address information designated by the address counter circuit 2003, and refreshes the memory to the RAM 203. Control information such as write control timing, and RA for the selection circuit 2005.
The write address information to M203 and the selection signal instructing that it is the write information based on the reset operation are sent.

The selection circuit 2005 is a RAM sent from the refresh control circuit 2004 based on the reset operation.
Write address information to the RAM 203, data information read from the ROM 202, and change write information to the RAM 203 sent by the instruction analysis circuit 2006 based on the firmware program change control information from the central controller 1. The RAM 203 is provided with the write information based on the reset operation when the selection signal sent from the refresh control circuit 2004 is received, and the modified write information when the selection signal is not received. Is selectively written to.

The instruction analysis circuit 2006 is provided in the central controller 1
When the control instruction information signal transmitted from the central control unit 1 is received and the control instruction information is a change writing control instruction of the firmware program, the change writing is performed. Information is sent to the selection circuit 2005, and if it is a normal exchange operation control instruction, the control instruction information signal is relayed to the microprocessor 201 as it is.

Further, the instruction analysis circuit 2006 relays the report information signal transmitted to the central control unit 1 by the microprocessor 201 controlling the device 3 to be controlled.

Under the above structure, the contents of the ROM 202 by the reset operation are copied to the RAM 203.
The operation to be performed and the operation of changing the contents of the RAM 203 based on the change writing control instruction from the central controller 1 will be described below.

The operation of copying the contents of the ROM 202 to the RAM 203 by the reset operation is to send a reset signal to the reset control circuit 2001 when the power of the control device 20 is turned on or when the other control devices 20 are reset. Be started by.

When the reset control circuit 2001 is activated, the reset control circuit 2001 sends a microprocessor reset signal to the microprocessor 201 to stop its operation and activates the counter update timing circuit 2002 to activate the address of the memory. Generates the timing clock used to control updates.

When the timing clock is generated from the counter update timing circuit 2002, the address counter circuit 2003 sequentially sends the address information to the refresh control circuit 2004 based on the timing clock.

The refresh control circuit 2004 sends the read address information and the read control information such as the read control timing to the ROM 202 according to the address information instructed by the address counter circuit 2003 to output the contents of the corresponding address to the RAM 203. On the other hand, the memory is refreshed and write control information such as the write control timing is sent to prepare for writing to the memory, and the selection circuit 200
5, the write address information to the RAM 203 and the selection signal instructing that the write information is based on the reset operation are sent.

Upon receiving the selection signal from the refresh control circuit 2004, the selection circuit 2005 receives the gate address B1 of the write address information from the refresh control circuit 2004 to the RAM 203 and the output data (ROM data of the ROM content from the ROM 202). Gate Bn for writing data to RAM 203)
Is selected and these write address information and write data information are sent to the RAM 203.

By the above operation, the content of one address in the ROM 202 is written in the RAM 203, and thereafter, the address counter circuit 2003 sequentially counts the final address of the ROM 202 and the similar operation of the ROM 202 is performed until the final address is updated. The contents are written in the RAM 203.

The address counter circuit 2003 is a ROM
When the final address of 202 is updated, a stop request is issued to the reset control circuit 2001 to report the end of the copy operation.

In response to the stop request, the reset control circuit 20
01 stops the operation of the counter update timing circuit 2002, and further releases the stopped state of the microprocessor 201.

The microprocessor 201, which has been released from the stopped state, sequentially executes the instruction operation using the firmware program written in the RAM 203.

Next, the content changing operation of the RAM 203 based on the change writing control instruction from the central control unit 1 will be described.

When it becomes necessary to change the firmware program of the control device 20 by changing the function of the control device 20 or adding the function, an input device (not shown) such as a magnetic tape device or a teletypewriter. The change information input by a command or the like from is edited into a control instruction information signal for the control device 20 by the software program of the central control device 1, and is the same as the control instruction information signal related to the normal exchange operation control. Be transmitted to.

As the control instruction information signal transmitted to the control device 20, the control instruction information signal related to the normal exchange operation control and the control instruction information signal related to the firmware program change control are sent to the instruction analysis circuit 2006. Are identified by an identifier indicating the control instruction type.

When it is identified that the identifier relates to the firmware program change control and the information instructing the start of the change operation is received, the instruction analysis circuit 200
Reference numeral 6 instructs the microprocessor 201 to stop operating.

Then, when the control instruction information signal including the change address information and the change data information is received, the change address information and the change data information included in the control instruction information signal are extracted. The respective information is sent to the gates A1 and An of the selection circuit 2005, and the RAM 20
3 to send the write control information.

Since the selection circuit 2005 has not received the selection signal, the selection circuit 2005 instructs the RAM 203 to write according to the changed address information and the changed data information received from the gates A1 and An.

In this way, the contents of the RAM 203 are rewritten based on the firmware program change control information signal sequentially transmitted from the central controller 1.

When all the change data information has been transmitted, the central control unit 1 sends a control instruction information signal including information for instructing the end of the change operation, so that the instruction analysis circuit 200
When 6 identifies it, it releases the stopped state of the microprocessor 201.

The microprocessor 201, which has been released from the halted state, sequentially executes the instruction operation using the changed firmware program.

[0065]

According to the firmware program change processing system of the present invention, the firmware program is written from the ROM to the RAM by the writing circuit when the power is turned on or the control device is reset. In rare cases, the microprocessor operates with the firmware program on the RAM, and the writing circuit is stored on the RAM according to the firmware program change control instruction information transmitted from the central control unit. The firmware program can be changed.

As a result, a large number of control devices controlled by the microprocessor are used to achieve load distribution and function distribution, and the firmware programs in these distributed control devices cooperate with the software program of the central control unit. In a device such as an exchange, which performs various functional operations, even when the function is changed or the firmware program is changed in accordance with the addition of functions, the maintenance personnel can install a teletypewriter etc. installed remotely. The change procedure can be performed only by inputting a command related to the firmware program change from the output terminal.

Therefore, the physical ROM to be replaced and the work of replacing the ROM, which are required in the conventional change processing system, can be eliminated, and the work of changing the firmware program can be performed very easily and There is an effect that it can be done in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing the concept of distributed control of exchanges.

FIG. 2 is a block configuration diagram showing a control device as an embodiment of the present invention.

FIG. 3 is a block configuration diagram focusing on the function of a writing circuit of a control device according to an embodiment of the present invention.

[Explanation of symbols]

 1 Central Control Unit 2 Control Device 3 Controlled Device 20 Control Device 200 Writing Circuit 201 Microprocessor 202 Read Only Memory (ROM) 203 Random Access Memory (RAM) 2001 Reset Control Circuit 2002 Counter Update Timing Circuit 2003 Address Counter circuit 2004 Refresh control circuit 2005 Selection circuit 2006 Instruction analysis circuit

Claims (4)

[Claims] 1. A control command, which has a microprocessor and a firmware program stored in a read-only memory, is located between a host control device and a control target device, and is transmitted from the host control device. A control device in which the microprocessor controls the controlled device based on the firmware program and a random access memory having a storage capacity sufficient to store the contents of the read-only memory; During the setting operation, the contents of the read-only memory are copied to the random access memory, and when the control command transmitted from the upper-level control device is a command for rewriting the firmware program, the control command is written. Writer that rewrites the contents of the random access memory according to the contents of Has the door, the microprocessor random access
A firmware program change processing method characterized by being operated by a firmware program copied to a memory. 2. The writing means is activated at the time of initial setting operation to stop the operation of the microprocessor, and at the same time, the read-only write operation is performed.
Copy operation control means for instructing to start an operation of copying the contents of the memory to the random access memory, instructing to stop the copy operation at the end of the copy operation, and releasing the operation stop of the microprocessor; At the start of the copying operation, the addresses of the memory to be copied are sequentially generated, the contents of the addresses are read out by the read-only memory, and the write address and the write address to the random access memory are written. A read / write control unit that outputs control information and outputs end information of the copying operation when all addresses of the memory to be copied are generated, and a control command transmitted from the host controller, and receives the control command. Is an instruction to rewrite the firmware program, the rewrite address and the rewrite address are written according to the contents of the control instruction. An instruction analysis unit for outputting data to control writing, a data read from the read-only memory, and a write address and a write address to the random access memory output from the read / write control unit. When the write control information, the rewrite address and the rewrite data output from the instruction analysis means are received, and the write control information is received from the read and write control means, the read only memory is read from the read only memory. When the data to be read and the write address to the random access memory output from the read / write control means, and the write control information from the read / write control means are not received, , Address information and data are transferred to the random access memory by selectively using the rewriting address and the rewriting data output from the instruction analyzing means. Firmware program change processing method according to claim 1, characterized in that it comprises a selection control unit for outputting information. 3. The control command transmitted from the host controller includes an identifier for identifying a control command for the microprocessor and a command for instructing rewriting of the firmware program. Change processing method of the firmware program described. 4. The rewriting address and the rewriting data included in the command for instructing the rewriting of the firmware program transmitted from the higher-level control device are input by remote input means. Firmware program change processing method.