JPH07141900A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To decrease a load on a tester and enable reducing testing time by making a device become a self-diagnostic mode by receiving specific signal from an outside and testing the device itself while generating a test pattern in the inside of the device. CONSTITUTION:A self-diagnostic/non-self-diagnostic mode control circuit 3 becomes the self-diagnostic mode at the specific condition of a control signal inputted at an input terminal 10. At the time of the self-diagnostic mode, cells a memory cell block 8 are accessed successively according to an address signal incremented successively by a counter 1. Besides, input data at the time of a writing and expectancy values at the time of a readout are generated in a data generating circuit 2 based on the output signal of the counter 1. Input data and expectancy generated in the circuit 2 are inputted respectively to a data input circuit 6 and a comparator circuit 4. The comparator 4 comparating readout data with expectancy outputs pass and fail as a result of the comparison to the outside of this semiconductor storage device 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a self-diagnosis function.

[0002]

2. Description of the Related Art Conventionally, in order to test a semiconductor memory device such as DRAM or SRAM, an address signal, input data corresponding to the address signal, and a test pattern such as expected data are generated by using a tester. Testing is performed using the test pattern.

[0003]

However, as the degree of integration of semiconductor memory devices has increased and the storage capacity has increased, the load on the tester for generating a test pattern also increases and the test time also increases. There is a problem.

The present invention has been devised in order to eliminate such disadvantages of the prior art, and its main purpose is to:
An object of the present invention is to provide an improved semiconductor memory device that can reduce the load on the tester and the test time.

[0005]

According to the present invention, a counter for starting counting with a specific condition signal and an address decoding means for generating an address signal based on the count value of the counter are provided according to the present invention. A data generating means for generating a pattern of write data and expected data for the memory cell block based on the count value of the counter; and a data input for inputting the data generated by the data generating means to the memory cell block. Means for comparing the data output from the memory cell block with expected data generated by the data generating means and outputting the comparison result to the outside of the semiconductor memory device; Receiving a specific condition signal from the outside of the memory device, the specific condition signal for self-diagnosis for the inside of the semiconductor memory device It is achieved by providing a semiconductor memory device characterized by a control means for forming.

[0006]

With this structure, when a specific condition signal is received from the outside of the semiconductor memory device, the semiconductor memory device enters the self-diagnosis mode. In this self-diagnosis mode, a test pattern is generated inside the semiconductor memory device, and the semiconductor memory device itself is tested. The result of the test is output to the outside of the semiconductor memory device.

[0007]

The present invention will be described in detail below with reference to specific embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, a counter 1, a data generation circuit 2, a self-diagnosis / non-self-diagnosis mode control circuit 3, and a comparison circuit 4
Is a self-diagnosis circuit inserted for easy evaluation.
The address decoder 5, the data input circuit 6, the data output circuit 7, and the memory cell block 8 are circuits that constitute a conventional semiconductor memory device. These circuits are included in the integrated circuit 9.

Self-diagnosis / non-self-diagnosis mode control circuit 3
Becomes a self-diagnosis mode under a specific condition of a control signal externally input to the control signal input terminal 10. Self-diagnosis / non-self-diagnosis mode control circuit 3 in self-diagnosis mode
Generates a control signal in the self-diagnosis mode for the counter 1, the data generation circuit 2, the comparison circuit 4, the address decoder 5, the data input circuit 6, and the data output circuit 7.

In the self-diagnosis mode, counter 1,
The data generation circuit 2 and the comparison circuit 4 are activated, and the data output circuit 7 is deactivated. The counter 1 counts a clock signal supplied from the outside. Counter 1
The output signal of the address decoder 5 is used as an address signal.
Entered in. The cells in the memory cell block 8 are sequentially accessed according to the address signal sequentially incremented by the counter 1.

On the other hand, with respect to the input data at the time of writing and the expected value at the time of reading, a signal such as a checker pattern or a march pattern is generated by the data generating circuit 2 based on the output signal of the counter 1. It The input data such as the checker pattern, the march pattern, etc., and the expected value generated in the data generating circuit 2 are input to the data input circuit 6 and the comparison circuit 4, respectively. That is, at the time of writing, data is written in the memory cell block 8,
At the time of reading, the comparison circuit 4 compares the data read from the memory cell block 8 with the expected value. The comparison circuit 4 that compares the read data with the expected value outputs the pass and fail as the comparison result to the outside of the semiconductor memory device 9.

By inserting the self-diagnosis circuit as described above, the load on the tester can be reduced and the evaluation time can be shortened.
In this embodiment, the counter 1 counts the clock signal normally supplied to the memory, but it may be a self-oscillation type counter.

Reference numerals 11 and 12 are input terminals, reference numeral 1
Reference numerals 3 and 14 are output terminals.

[0014]

As described above, according to the present invention, it becomes almost unnecessary to supply the test pattern from the tester when the semiconductor memory device is evaluated. This makes it possible to reduce the load on the tester and reduce the test time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device incorporating a self-diagnosis circuit of the present invention.

[Explanation of symbols]

 1 counter 2 data generation circuit 3 self-diagnosis / non-self-diagnosis mode control circuit 4 comparison circuit 5 address decoder 6 data input circuit 7 data output circuit 8 memory cell block 9 integrated circuit

Claims (1)

[Claims] 1. A counter that starts counting with a specific condition signal, an address decoding unit that generates an address signal based on the count value of the counter, and a memory cell block based on the count value of the counter. Data generation means for generating a pattern of write data and expected data; data input means for inputting the data generated by the data generation means to the memory cell block; and data output from the memory cell block and the data generation Comparing the expected data generated by the means, and outputting the comparison result to the outside of the semiconductor memory device; and comparing the expected data to the semiconductor memory device by receiving a specific condition signal from the outside of the semiconductor memory device. And a control means for generating the specific condition signal for self-diagnosis of the inside of the device. Storage device.