JPH07141859A - Dual port ram - Google Patents

Abstract

PURPOSE:To obtain a dual port RAM having constitution suitable for a LSI (ASIC) for a specific use which detects generation of access for the same row by detecting directly a state of two word lines through a logic gate and a transistor(TR). CONSTITUTION:When a signal is made '1' by selecting by Word line drivers ADRVx, BDRVx corresponding to two word lines AWLx, BWLx of each row, the output of an AND gate is made '1', and discharge TR Dx is turned on. And a sense line FLN is charged, it is directly detected by a sense amplifier without providing a comparator and the like that access to word line AWLx, BWLx in the same rows is simultaneously generated. By using this constitution, a dual port RAM provided with constitution suitable for ASIC which detects that access to the same row is simultaneously generated can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual port RAM having two ports for accessing each memory area independently of each other.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing one memory cell of a dual port RAM. This memory cell 10
Is provided with two inverters 12 and 13 whose inputs and outputs are connected to each other. Further, the memory cell 10 has a bit line b _A and a bit bar line b on the A port side.
Bit line b _B and bit bar line b _B on the _A and B ports side
The inverter 1 with the input of the inverter 12
3, the pass transistors 14 and 16 are arranged between the connection point with the output of FIG. 3 and the bit lines b _A and b _B , and the connection point between the input of the inverter 13 and the input of the inverter 12 and the bit bars. The pass transistors 18 and 20 are arranged between the lines b _A and b _B. In addition, this memory cell 10
Has a word line AWL on the A port side and a word line BWL on the B port side extending, the gates of pass transistors 14 and 18 are connected to the word line AWL, and the gates of pass transistors 16 and 20 are connected to the word line BWL. Has been done.

When writing from the A port side to the memory cell 10 configured as described above, the word line AWL on the A port side is raised to logic "1" and the bit line b _A and the bit bar line b _A are set. By setting the logic to "1", "0" or the logic "0", "1", respectively, the logic "1" or the logic "0" is written in this memory cell. Further, when reading the stored contents of the memory cell 10 from the A port side, the word line AWL on the A port side is raised to logic "1" and the memory cells 10 appearing on the bit line b _A and the bit bar line b _A are read. The content is detected by a sense amplifier (not shown). The same applies to the B port side.

Although only one memory cell 10 is shown here, a plurality of such memory cells 10 are arranged to form one memory area to which one address is assigned, and this memory area is usually arranged in the row direction. A common word line AW is arranged in a plurality of memory areas arranged in the column direction and arranged in the same row direction.
L and BWL are extended. Here, a problem arises when a certain row is simultaneously accessed from both the A port side and the B port side. For example, an attempt is made to write to the memory cell 10 shown in FIG. 3 from the B port side, and at the same timing, reading from a memory area existing in the same row other than the memory area including the memory cell 10 shown in FIG. 3 is performed. Suppose you try. At this time, the two word lines AW
Since L and BWL are in the logic "1" state at the same time,
Four pass transistors 14 of the memory cell 10 shown in FIG.
All 16, 18, and 20 are turned on. Therefore,
Bit lines b _B and bit bar lines b _B are connected to the memory cell 10.
Attempting to write predetermined bit information via the path transistors 14, 18 and the bit lines b _A , bit bar lines b _A also become loads, and the pass transistors 14, 1
Since 6, 18 and 20 are formed of small transistors, it takes a very long time to drive the load.

In order to avoid this, it is detected that both word lines AWL and BWL in the same row become logic "1" at the same time, and both bit lines b _A and b _B and both bit bar lines are detected. Shorting b _A and b _B together,
Small size pass transistors 14, 16, 18, 2
Countermeasures have been proposed, such as eliminating the difficulty of current flow due to 0 and enabling high-speed access (for example, Japanese Patent Laid-Open No. Hei 4
(See Japanese Patent Application Laid-Open No. 184788/1994 and Japanese Patent Application Laid-Open No. 4-60972)

[0006]

As a countermeasure when both word lines AWL and BWL of the same row rise to logic '1' at the same time, it is left to the above proposal that both word lines AWL and BWL of the same row are The problem is how to detect whether the BWLs have risen to logic "1" at the same time.

4 and 5 are a block diagram and a circuit diagram showing a conventional detection method. Here, A port side, B
Each address on the port side is represented by 4 bits for simplicity. Conventionally, a general-purpose dual-port RAM memory has an address AA on the A port side as shown in FIG.
D0 to AAD3 and B port side addresses BAD0 to BA
An address comparison circuit for directly comparing D3 is provided, and this address comparison circuit is configured as shown in FIG. 5, for example.

In the case of a general-purpose dual-port RAM, writing may occur at the same address (same memory area) at the same time in the same row, and in order to avoid this, the general-purpose dual-port RAM has the above-mentioned structure. An address comparison circuit is provided to detect simultaneous writing at the same address and prohibit simultaneous writing. Since the conventional general-purpose dual-port RAM is provided with the address comparison circuit as described above, it is possible to detect that the same row is simultaneously accessed by using the address comparison circuit, and the same row is simultaneously accessed. When the access occurs, the measures proposed above can be taken.

In the case of a general-purpose dual-port RAM, it is necessary to avoid simultaneous writing to the same address, so the address comparison circuit as described above is required.
When a system including a dual port RAM is incorporated in one chip (special purpose LSI), simultaneous writing to the same address can be avoided depending on its usage method, and therefore the address comparison circuit as described above is unnecessary. is there. Nevertheless, the provision of the address comparison circuit only for detecting the simultaneous access to the same row has a large area demerit.

Further, this address comparison circuit is based on the ASIC.
When designing a memory having an arbitrary capacity and configuration using a module generator like a memory card, it is necessary to change the design each time according to the number of addresses, which is not suitable for ASIC. In view of the above circumstances, the present invention provides a dual port R having a configuration suitable for ASIC that detects simultaneous access to the same row.
The purpose is to provide AM.

[0011]

A dual-port RAM of the present invention which achieves the above object has a plurality of memory cells each having one or a plurality of memory cells arranged two-dimensionally in a row direction and a column direction. Dual having a memory area, a plurality of word lines provided for each row of the plurality of memory areas, and first and second ports for accessing each of the plurality of memory areas independently of each other In the port RAM, (1) A sense line for detecting that the memory areas arranged in the same row are simultaneously accessed from the first and second ports (2) Of the first and second ports A charging circuit for charging the sense line by detecting that access from at least one port is suspended (3) Both two word lines extending in the same row are simultaneously It is characterized in that it comprises a detection circuit for detecting that the discharge circuit (4) the sense lines to discharge the sense line senses that it has been selected has been discharged.

[0012]

The present invention does not compare the addresses as in the prior art, but directly detects the state of word lines extending by two in each row, and thereby detects that the same row is being accessed. Therefore, a circuit for detecting this can be uniformly formed in each row, and the design of the ASIC memory using the module generator becomes easy.

[0013]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a circuit diagram of a portion of a dual-port RAM according to an embodiment of the present invention that detects whether or not simultaneous access to the same row has occurred. In the memory unit MEM in which a large number of memory areas are arranged, a large number of word lines AWL0, ...
WLx, ..., And many word lines BWL on the B port side
0, ..., BWLx, ... Extend and their respective word lines AW
L0, ..., AWLx, ...; BWL0, ..., BWLx ,.
, One of the word line drivers ADRV0, ..., ADR
VDR, ...; BDRV0, ..., BDRVx ,. Each of these word line drivers ADRV0, ...,
ADRVx, ...; BDRV0, ..., BDRVx ,.
Depending on the input address and the port to which the address is input, the corresponding word lines AWL0, ..., AW
Lx, ...; BWL0, ..., BWLx, ... Are driven to drive the word lines AWL0, ..., AWLx ,.
BWLx, ... Set to logic '1'.

The dual port RAM is also provided with an A port side dummy cell and a B port side dummy cell (not shown), and the A port dummy word line ADWL and the B port dummy word line BDWL extend to these dummy cells, respectively. Those A port dummy word line ADW
An A port dummy word line driver ADMY and a B port dummy word line driver BDMY are connected to one ends of the L and B port dummy word lines BDWL, respectively.

Here, the A-port side dummy cell and the B-port side dummy cell are simultaneously accessed when any memory area from the A-port side or the B-port side is accessed, and the stored contents of the memory area are read out. At this time, it plays a role in determining the timing for activating the sense amplifier. A sense line FLN extends in the vertical direction of the figure, and the precharge P-channel transistors APR and BP are connected to the sense line FLN with the power supply V _DD.
R is connected, and the gates of these transistors APR and BPR are connected to the A port dummy word lines ADWL and ADWL, respectively.
It is connected to the B-port dummy word line BDWL.

A large number of discharge N-channel transistors D0, ..., Dx, ... Are connected to the sense line FLN and the ground. The gates of these N-channel transistors D0, ..., Dx, ... Are connected to the outputs S0, ..., Sx, ... Of the respective AND circuits AND, and the inputs of these respective AND circuits are two each extending in the same row. Word lines AWL0, BWL0; ...; AWLx,
It is connected to BWLx; The logic of the sense line FLN is detected by the sense amplifier SENSE.

FIG. 2 shows the dual port RAM shown in FIG.
2 is a timing chart of. 2 are the same as those in FIG.
It corresponds to each code shown in. Here, as shown in FIG. 2, there are two word lines AWL extending in the same row.
It is assumed that x and BWLx are raised to the logic '1' at some timings thereof.

Simultaneous access does not occur when at least one of A port and B port is not accessed. Therefore, the dummy word lines ADWL, B
When DWL is at logic "0", the precharge transistors APR and BPR are turned on to precharge the sense line FLN. At this time, the sense amplifier S
The output FL of ENSE becomes logic "0".

Two word lines AWLx, which extend in the same row,
When BWLx rises to logic '1' at the same time, the discharge transistor Dx is turned on, and at that time, since the precharge transistors APR and BPR are both off, the sense line FLN is discharged, and this is detected by the sense amplifier SENSE. The output FL of the sense amplifier SENSE becomes logic "1".
As a result, it is detected that simultaneous access to the same row has occurred.

Although the discharge transistors D0, ..., Dx, ... Are provided for each row in the above embodiment, the output Sx of the AND circuit AND provided for each row is
The number of discharge transistors may be reduced by inputting to each OR circuit (not shown) for every plurality of rows and connecting the output of the OR circuit to the gate of the discharge transistor.

Also on the precharge side, in addition to using the dummy word lines ADWL and BDWL, for example, in the case of a dual port RAM that accesses in synchronization with an external clock, each of these clocks is set to one. The sense line FLN may be precharged at a timing when it is input to the precharge circuit and is not accessed by the A port or the B port based on the clock.

As described above, the present invention can be variously constructed.

[0023]

As described above, since the dual port RAM of the present invention directly detects the state of the word line extending by two in each row, it is suitable for the design of the ASIC memory using the module generator. Dual port R with the function to detect simultaneous access to the same row
It becomes AM.

[Brief description of drawings]

FIG. 1 shows a dual-port RAM according to an embodiment of the present invention,
FIG. 6 is a circuit diagram of a portion that detects whether or not simultaneous access to the same row has occurred.

FIG. 2 is a timing chart of the dual port RAM shown in FIG.

FIG. 3 is a circuit diagram showing one memory cell of a dual port RAM.

FIG. 4 is a block diagram showing a conventional detection method.

FIG. 5 is a circuit diagram showing a conventional detection method.

[Explanation of symbols]

10 memory cells AWL0, ..., AWLx, ... A port side word line BWL0, ..., BWLx, ... B port side word line FLN sense line SENSE sense amplifier APR, BPR precharge P channel transistor D0, ..., Dx, ... Discharge N-channel transistor MEM memory part

Claims (1)

[Claims] 1. A plurality of memory areas each having one or a plurality of memory cells arranged two-dimensionally in a row direction and a column direction, and two memory areas each including two or more memory areas. Port RA having a plurality of word lines and first and second ports for accessing each of the plurality of memory areas independently of each other.
M, a sense line for detecting that the memory areas arranged in the same row are simultaneously accessed from the first and second ports, and at least one of the first and second ports. Access to the sense line is stopped, and the charge circuit for charging the sense line and two word lines extending in the same row are selected at the same time, and the sense line is discharged. A dual port RAM comprising a discharge circuit and a detection circuit for detecting that the sense line has been discharged.