JPH0713954A - Test circuit of microcomputer - Google Patents

Abstract

PURPOSE:To shorten teat time simultaneously executing the test of a whole microcomputer except an EEPROM function, and EEPROM screening. CONSTITUTION:The test circuit 16 executes screening to EEPROM 12 by an instruction from CPU 11, the screening time is counted by a regiater 17. Since CPU 11 released from control concerning acreening after instructing the test circuit 16, of the start of screening, the test concerning the function of the microcomputer 10 except EEPROM 12 is simultaneously executed in parallel based on a test device. When screening is interrupted by the circumstances of the test concerning the function of the microcomputer 10, the count value of the register 17 is temporarily saved to a storage area 12a and the contents of the storage area 12a is restored to the register 17 after the test concerning the function is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is provided in a microcomputer having a built-in read-only memory (hereinafter referred to as EEPROM) which is electrically erasable and rewritable.
The present invention relates to a test circuit of a microcomputer capable of shortening the test time of the EEPROM test and the other tests.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference 1: JP-A-3-77148 Reference 2: JP-A-3-205700 Reference: FIG. 2 shows a conventional EEPROM described in the reference 2 and the like.
It is a figure which shows the memory cell structure of. The memory cell of this EEPROM has a source (array ground) 2 and a drain 3 formed on the surface of a semiconductor 1, and the source 2
A floating gate 4 having a tunnel window 4a and a control gate 5 are formed in a stacked state between the drain 3 and the drain 3 with an insulating film interposed therebetween.

In this type of EEPROM memory cell,
For example, the write operation is executed as follows. When an EEPROM write voltage of about 20 V is applied to the control gate 5, electrons are injected into the floating gate 4 through the tunnel window 4a and the threshold V _{t of the} memory cell is reached.
Becomes higher. Approximately 2V to control gate 5 during reading
Even if is applied, the memory cell maintains the high impedance state. This state is called the erased state of the EEPROM, and the read data is "1". Conversely, control gate 5
Is fixed to the ground potential (GND) level, and E is set to the drain 3.
When the EPROM write voltage is applied, holes are injected into the floating gate 4 and the threshold value V _t becomes low. When about 2 V is applied to the control gate 5 during reading, the memory cell becomes conductive. This state is EEP
This is called the ROM write state, and the read data is "0".

The majority of the failure modes of the EEPROM, which occur after the defects during manufacturing are removed by a test, are due to the disappearance of the electrons or holes accumulated in the floating gate 4, and the disappearance of the electrons and the like. Is due to deterioration of the tunnel window 4a as the number of rewrites increases. Since the data retention capability is an extremely important characteristic from the viewpoint of reliability, writing and erasing are performed several thousand to 10,000 times for all memory cells of the EEPROM to remove the initial failure of the tunnel window 4a. Screening methods are common. Usually, the time required for writing and erasing in the EEPROM is about 5 mS each. For example, even if it has a test mode in which all the memory cells of the EEPROM can be erased and programmed at one time,
It takes 100 seconds of test time to perform erasing and writing ten times. In order to efficiently carry out such a screening method, conventionally, in the technique of Document 1, a read-only memory (hereinafter referred to as a ROM) for a test dedicated to screening is provided and a plurality of chips are tested at the same time. There is. Further, in the technique of the above-mentioned document 2, a test mode dedicated to screening is provided, and by performing screening during a heating test (burn-in) or the like, a test method that does not require exclusive use of expensive test equipment for a long time is implemented. It

[0005]

However, in the test circuit using either of the conventional methods of Document 1 and Document 2, a test of the entire microcomputer and an E test are performed.
In order to perform the EPROM screening, it is necessary to perform probing a plurality of times in a wafer state, or to perform the screening after assembling a microcomputer. Therefore, there is a problem that the test process becomes complicated, the test time becomes long, and the test cost is not sufficiently improved, and it is difficult to solve them. SUMMARY OF THE INVENTION The present invention provides a test circuit for a microcomputer, which solves the problem that the conventional technique has, that the test time is long and the test cost is not sufficiently improved.

[0006]

In order to solve the above-mentioned problems, the present invention incorporates an EEPROM, and the EEPROM is
In a microcomputer that program-controls the entire microcomputer including
The following means are provided. That is, a screening-dedicated test circuit for carrying out screening by writing and erasing data in a part or all of the storage area of the EEPROM independently of a test other than the EEPROM carried out under the control of the CPU. A counting means for counting the number of times of screening based on at least one of writing and erasing the data;
A non-volatile storage unit configured by a ROM or another EEPROM for storing the count value of the counting unit is provided in the microcomputer.

[0007]

According to the present invention, since the test circuit of the microcomputer is constructed as described above, when the microcomputer tests other than the EEPROM function by the CPU, the EEPROM is tested in parallel with the test circuit by the screening dedicated test circuit. Is performed, and the number of times of screening is counted by the counting means. For the convenience of testing the entire microcomputer, when the EEPROM screening is interrupted, the contents of the count means are written into the nonvolatile storage means (saving processing), and when the entire microcomputer test is completed, the nonvolatile The number of times of screening at the time of interruption of screening saved in the storage means is set in the counting means (recovery process). This enables the micro
The test time can be shortened due to the simultaneous execution of the test of the entire computer and the screening of the EEPROM.
Therefore, the above problem can be solved.

[0008]

1 is a functional block diagram of a microcomputer incorporating a test circuit showing an embodiment of the present invention. The microcomputer 10 includes a CPU 11 that controls a program of the entire microcomputer, an EEPROM 12 that is a non-volatile memory that retains data even when power is cut off, and a readable / writable memory (hereinafter, RAM) that stores data and programs. Say) / RO
M13, the input / output circuit 15 capable of connecting the test apparatus 20 and the like, and the screening of the EEPROM 12 (“0”)
And repeatedly writing "1") to the EEPROM1
2 includes a test circuit 16 dedicated to screening that generates a control signal S16f and a count-up signal S16e required by 2 at a predetermined timing, and a screening number register 17 that counts the number of screenings based on the count-up signal S16e.

The CPU 11 is an address / data bus BU
A function of being connected to the EEPROM 12, RAM / ROM 13, peripheral circuit 14, input / output circuit 15, screening test circuit 16 and screening frequency register 17 via S and controlling them according to a program stored in the RAM / ROM 13. Have Also, CP
The U11 has a function of controlling the reading of data from the EEPROM 12 and the like by the control signal S11.
The EEPROM 12 has a large number of memory cells shown in FIG. 2, for example, and they are arranged in a matrix. EEPR
A screening frequency storage area 12a is provided in a part of the OM 12. The screening for the EEPROM 12 is performed by the screening dedicated test circuit 1
CPU 11 by the control signal S16f given from
The screening is designed to be performed independently of the control. The CPU 11 is connected to the screening-dedicated test circuit 16 via the flag FG. Flag F
As G, a start flag SFG and a busy flag BF
G and an end flag EFG are provided.

FIG. 3 is a block diagram showing a configuration example of the screening dedicated test circuit 16 and the screening number register 17 in FIG. The test circuit 16 for exclusive use of screening is reset by the count-up signal S16e and is controlled by the CPU 11 with a start flag SF.
A set / reset flip-flop (hereinafter referred to as FF) 16a set by G, a two-input OR gate 16b for obtaining the logical sum of the output of the FF 16a and the end flag EFG, and an oscillation circuit 16c are provided. OR
The output terminal of the gate 16b is connected to the input terminal of the inverter 16d that controls the busy flag BFG, and
It is connected to the clear terminal CLR of the ripple carry counter 16e. The output terminal of the oscillator circuit 16c is connected to the clock terminal CLK of the counter 16e. The output terminal of the counter 16e is connected to the input terminal of the logic circuit 16f, and the EEPRO is connected to the output terminal of the logic circuit 16f.
Control signal S required for screening M12
16f is generated at a predetermined timing. In the following description, the signal of the busy flag BFG will also be included in the control signal S16f. The count-up signal S16 is output from the carry-out terminal CO of the counter 16e.
e is output, is sent to the FF 16a, and is also input to the clock terminal CLK of the screening number register 17. From the carry-out terminal CO of the screening frequency register 17, OR gates 16b and C are connected.
The signal of the end flag EFG given to the PU 11 is output.

FIG. 4 is a flowchart of the screening process of the microcomputer 10 shown in FIG.
The operation of FIGS. 1 and 3 will be described with reference to this figure. First, the test apparatus 20 is connected to the input / output circuit 15 in the microcomputer 10, and the test apparatus 20 allows the basic function of the microcomputer 10 and the EEPROM.
Test 12 basic functions. The basic functions of the microcomputer 10 include contact check of all pins (inspection of contact state and whether PAD section and protection diode inside IC are connected), input of whether or not input signal is leaked. There are leak tests and functional tests with high failure rates (function tests).
Test item. The basic function test of the EEPROM 12 is a simple test performed before performing a time-consuming screening. For example, 00 / FF is written in the entire storage area of the EEPROM 12 and read. If even one of these test items is found defective by the test apparatus 20, the microcomputer 1
The 0 test is aborted immediately and no further tests are performed. After such a basic function test is performed, the following test is performed on the non-defective microcomputer 10.

The CPU 11 starts the screening process in step 30, initializes the screening number register 17, and then sets the start flag SFG to "1" in step 31. When the start flag SFG becomes "1" in step 31, the screening dedicated test circuit 16 is activated, the busy flag BFG connected to the inverter 16d in the screening dedicated test circuit 16 becomes "1" in step 33, and step 34 is executed. Via the control signal S16f output from the logic circuit 16f in the screening-dedicated test circuit 16 via the steps 35, 3
At 6, a write / erase cycle for the EEPROM 12 is performed. When at least one of writing and erasing is performed once, the count-up signal S16 output from the counter 16e in the screening-dedicated test circuit 16 is output.
By e, the screening frequency register 17 is incremented by +1 in step 37. And
The screening is continued through step 38 until a predetermined number of times is reached. When the predetermined number of times of screening has been performed, in step 39, the busy flag BFG is set to "0" by the output of the inverter 16d in the screening-only test circuit 16, and the screening number register 17 overflows to set the end flag EFG to "1". ”
Then, the operation of the screening dedicated test circuit 16 is stopped. When the screening is completed in step 39, the test which is being executed in parallel with the screening is awaited.

On the other hand, the CPU 11 sets the start flag SFG to "1" for the screening dedicated test circuit 16.
After instructing the screening-dedicated test circuit 16 to start screening, the control relating to screening is released. Therefore, the CPU 11
A test on the functions of the microcomputer 10 other than the EEPROM 12 is carried out at the same time as the start of step 30, in parallel with the screening process, based on a control signal from the test device 20. Here, as the test regarding the function of the microcomputer 10, CPU 11, R
The AM / ROM 13, the function test in the peripheral circuit 14 such as the timer and the input / output port (excluding the items performed before the screening), the AC (AC) test such as the memory access time, and the peripheral circuit 14 There are direct current (DC) tests such as the drive capability of the output port. Such a microcomputer 1
When performing a test for zero functionality, for example, RAM
EE power supply voltage to measure the lowest voltage
In some cases, the voltage may be lower than the voltage required for screening the PROM 12. Also, to carry out different test items,
The power of the entire microcomputer 10 may be temporarily turned off. In particular, when the power is turned off during the screening, the number of screenings already performed stored in the screening frequency register 17 is erased. Therefore, before the contents of the screening frequency register 17 are erased by turning off the power, the screening frequency storage area 12a for copying the information of the screening frequency is the EEPROM to be tested.
It is provided using the storage area of 1 byte or 2 bytes or more of M12 itself.

As a procedure for turning off the power supply to the microcomputer 10 by the test apparatus 20, first, the CPU 11 sets the start flag SFG to "0" and waits for the end of the write / erase cycle by the screening dedicated test circuit 16. That is, the screening-dedicated test circuit 16 continues the screening until the current write / erase cycle is completed. When the write / erase 1 cycle is completed, the start flag SFG is "0" in step 34 of FIG.
In step 2, the dedicated screening test circuit 16 sets the busy flag BFG to "0". As a result, the screening dedicated test circuit 16 stops the screening operation. The CPU 11 monitors the busy flag BFG, and when detecting the end of the cycle, reads the contents of the screening number register 17 and writes the contents in the EEPROM.
Data is written into the screening frequency storage area 12a in 12 (save processing), and after the writing is completed, the test device 2
0 is given permission to turn off the entire microcomputer 10. As a result, the test apparatus 20 turns off the entire power supply of the microcomputer 10.

When the test apparatus 20 again turns on the power supply of the entire microcomputer 10 to carry out the next test, the CPU 11 reads out the screening frequency information from the screening frequency storage area 12a, After the read value is set (loaded) in the screening frequency register 17 and the start flag SFG is set to "1" (return processing), another test is performed.
When the start flag SFG becomes "1", the test circuit 16 for exclusive use in screening is simultaneously conducted in parallel with the other tests.
The screening is restarted and carried out by. In the test by the test device 20, when the power supply of the microcomputer 10 is insufficient for performing the screening, but the potential becomes higher than the memory holding voltage of the screening frequency register 17, the CPU 11 only operates the start flag SFG. This can be dealt with, and the save processing to the screening frequency storage area 12a as described above is unnecessary.

As described above, in this embodiment, EEPRO
Each test of the entire microcomputer 10 excluding M12 and the screening process of the EEPROM 12 can be simultaneously executed in parallel. If the power supply of the microcomputer 10 to be tested is insufficient for carrying out the screening due to another test using the test apparatus 20, the CPU 11 controls the screen count register 17 to store the screening frequency. The number of times the screening has been performed is stored in advance in the screening frequency storage area 12
After the other tests are completed and the power is applied as usual, the screening process is restored. Therefore, the screening process of the EEPROM 12 is not affected by other tests. Therefore, the test time is shortened and the test cost can be reduced accordingly.

FIG. 5 is a block diagram showing a configuration example of another embodiment of the present invention in which a count memory 43 and the like are provided instead of providing the screening count storage area 12a of FIG. In this configuration example, instead of providing the screening frequency storage area 12a of FIG. 1, a count-up signal S16e output from the counter 16e of FIG. 3 and an output of the inverter 41 that inverts the signal of the end flag EFG are provided.
It is input to the 2-input AND gate 42, and its output is input to the clock terminal CLK of the screening number register 17. The contents of the screening number register 17 are copied at the same time as at least one of the writing and erasing in the programming / erasing cycle of screening.
A count memory 43 composed of a PROM is attached to the screening count register 17. The output of the frequency memory 43 is
The detection circuit 44 detects all "1" s and outputs the signal of the end flag EFG. With such a configuration, at least one of the writing / erasing of the screening write / erase cycle by the screening dedicated test circuit 16 and at the same time the screening number register 17
Is copied to the frequency memory 43. Therefore, during the screening, the test device 20 may be used for other tests.
Even when the power of the microcomputer 10 is turned off, the number of times memory 43 holds the number of times of screening at the time of screening interruption. Then, when another test by the test apparatus 20 is completed based on the held contents, the interrupted screening process can be recovered at the same time. Therefore, it is possible to omit the procedure for saving / returning the screening frequency information from the CPU 11 to the screening frequency storage area 12a as the power is turned on / off during the screening, and control can be facilitated.

The present invention is not limited to the above embodiment,
Various modifications are possible. The following are examples of such modifications. (A) The test circuit 16 dedicated to screening shown in FIG.
You may change to another circuit structure. For example, counter 16
Alternatively, e may be configured by a down counter, and the screening count register 17 may decrement (decrement) by 1 based on the countdown signal output from the down counter. Also, the screening frequency register 17
May be composed of other counting means. (B) The microcomputer 10 to be tested shown in FIG. 1 may be changed to another circuit configuration.

[0019]

As described above in detail, since the test-dedicated test circuit, the counting means, and the non-volatile memory means are provided in the microcomputer to be tested, each test of the microcomputer except the EEPROM is performed. Can be performed by the CPU, and at the same time, the EEP can be performed in parallel with the screening test circuit.
ROM screening can be performed. Moreover, CPU
If the power supply of the microcomputer to be tested is insufficient for performing the screening due to another test based on the control of 1., the number of performed screenings at the time of the interruption of the screening is the nonvolatile storage means. Once, the number of times the screening has been carried out is returned to the counting means. Therefore, the EEPROM screening process can be performed without being affected by other tests. Therefore, the test time can be shortened, and thus the test cost can be reduced.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a microcomputer showing an embodiment of the present invention.

FIG. 2 is a diagram showing a memory cell structure of a conventional EEPROM.

FIG. 3 is a block diagram showing a configuration example of a screening dedicated test circuit and a screening frequency register in FIG.

FIG. 4 is a flowchart showing a screening process of FIG.

FIG. 5 is a block diagram showing a configuration example of another embodiment of the present invention.

[Explanation of symbols]

 10 Micro Computer 11 CPU 12 EEPROM 12a Screening Count Storage Area 16 Screening Test Circuit 17 Screening Count Register 20 Test Device 43 Counting Memory

Claims (1)

[Claims] 1. A microcomputer having an electrically erasable and rewritable read-only memory built-in, wherein the entire microcomputer including the read-only memory is program-controlled by a central processing unit. A screening-dedicated test circuit that performs screening by writing and erasing data in a part or all of the storage area of the read-only memory independently of a test other than the read-only memory performed by Counting means for counting the number of times of screening based on at least one of writing or erasing data, and a non-volatile storage means for storing the count value of the counting means, which is composed of the read-only memory or another read-only memory, Provided in the microcomputer Test circuit of micro-computer, wherein the door.