JPH0713805A - Parallel computer and program execution reproducing method - Google Patents

Abstract

PURPOSE:To decrease the amount of records of information required for program reproduction and to easily perform the program reproduction from an optional check point. CONSTITUTION:In the parallel computer which allows plural processing elements to access a common memory, the common memory 2 is provided with a data holding part 20, a version management part 21 which records the update frequency and read frequency of data, and an access discrimination part 22 which discriminates whether or not access operation is performed. At the time of program execution, snap shot operation is performed to record data accessed between check points, the history of access to the common memory 2, and process state information at check point time and when the program reproduction is performed, the program is re-executed on a common memory 2, reproduced on the basis of recorded information, with the processor state information after the program reproduction is synchronized on the basis of the access history.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer having a shared memory and a program execution reproducing method in the parallel computer.

[0002]

2. Description of the Related Art Generally, in a device having a single processing element, a program behaves the same even if it is repeatedly executed. Many debugging tools have been developed using this property.

Meanwhile, in order to realize a computer having a higher processing capacity, a parallel computer has been developed in which a plurality of processing elements are provided and processing is performed in parallel by these elements.

In a parallel computer, the program execution does not always have the same behavior due to the timing shift of each processing element. In order to reproduce the program execution from an arbitrary elapsed time, it is necessary to retain many snapshots and memory access history. Therefore, the debugging tool used in a single processing element device cannot simply be applied to a parallel computer.

As a method for reproducing a program on a parallel computer, a method having a shared memory is known as "Real-Time, Coc
urrent Checkpoint for Parallel Programs "(Kai L
i, Jeffrey F. Naughton and James S. Plank, ACM SIGP
LAN Notices, Vol.25, No.3, pp. 79-88, 1990), there is a method of recording all the memory contents at each checkpoint. This method is easy to improve so that only the changed portion is recorded, but in terms of reproducing the program execution, since it does not have mutual interference information between processes, even if it starts from a specific state, it is not always necessary. The result may not be the same as the previous program execution.

As a method in a distributed environment, "IG
OR: A System for Program Debugging via Reversible E
xecution "(S. Feldman and C. Brown, ACM SIGPLAN
Notices, Vol.24, No.1, pp.112-123, 1989), there is a method to incrementally record only the changing part. In this method, the mutual interference information between processes records the sending and receiving of messages, and due to the characteristic that message communication is slower than shared memory access, the log amount recorded per unit time is relative in a distributed environment. Very few. However, when a message is overtaken, it is necessary to record information such as a unique message number or content added by the message sender, not only from where it arrived.

Further, conventionally, in order to record a history for reproducing the order of shared memory access, a time stamp is taken by a global clock common to each processing element, or a processing element number and an access are made to a common storage area. It was necessary to record the operation type, data, etc. while maintaining the order relation.

[0008]

As described above, in the conventional parallel computer, it was necessary to record a lot of information in order to reproduce the program so as to have the same behavior. Also, when trying to reproduce a program from an arbitrary checkpoint, a storage area is provided to store the above-mentioned various information such as the global clock and the unique message number and contents added by the message sender. I needed to.

The present invention has been made in consideration of the above circumstances, and it is possible to reduce the recording amount of information required for program reproduction and easily reproduce the program from an arbitrary checkpoint. An object is to provide a parallel computer and a program execution reproduction method.

[0010]

According to the present invention, in a parallel computer which accesses a shared memory from a plurality of processing elements, data holding means for storing data and data held in the data holding means are provided. Correspondingly, a version management unit that records information indicating the number of times of updating and the number of times of reading of the same data, and whether or not an access operation is performed are identified for each memory block including the data held in the data holding unit. And a shared memory provided with access identification means for recording information for instructing the processing element to instruct execution of a snapshot at the time of program execution, and a check is performed according to the information recorded by the access identification means. In the shared memory where the access operation was performed between points A snapshot management means for storing the data held by the storage means and the information recorded by the version management means, and an instruction to reproduce and execute the program from an arbitrary checkpoint to the processing element when reproducing the program. A checkpoint management unit provided with a reproduction execution management unit that restores the shared memory based on the contents stored by the snapshot management unit; and, in accordance with a snapshot execution instruction from the snapshot management unit, An access history storage unit for storing an access history to the shared memory, a processor state storage unit for storing processor state information at the time of checkpoint, and the processor according to an instruction of program reproduction execution by the reproduction execution management unit. Processor state restoration means for restoring the processor state information stored by the state storage means, and the reproduction execution management means after the program reproduction is synchronized based on the access history stored by the access history storage means. And a processing element provided with a processor that re-executes a program according to the reproduced shared memory and the processor state information restored by the processor state restoring means.

[0011]

According to such a configuration, during program execution, each processing element records the version number (update count) and the read count at the time of writing, and only the version number at the time of reading. Also, as a snapshot of the shared memory, only the changed portion from the previous time is recorded.

When the execution of the program is reproduced from an arbitrary checkpoint, the shared memory retrieves the latest information of the shared memory from the checkpoint and the previous points, and restores the contents of the shared memory. Each processing element restores the processor state from the processor state information of the checkpoint.

At the time of program execution reproduction, each processing element waits for a write operation until the version number and the number of times of reading match at the time of writing, according to the shared memory access history, and at the time of matching, the write operation is performed. At the time of reading, the operation is put on standby until the version numbers match, and when they match, the reading operation is performed. As a result, the execution of the program is reproduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the main configuration of a parallel computer according to this embodiment. As shown in FIG. 1, the parallel computer has a plurality of processing elements 1-1, 1-
2, ..., 1-n, shared memory 2, checkpoint management unit 3, secondary storage device 4, and bus 5. Processing elements 1-1, 1-2, ...
1-n, shared memory 2, and checkpoint management unit 3
Are connected via a bus 5, and write / read operations from the respective processing elements 1-1, 1-2, ..., 1-n to the shared memory 2 are performed via the bus 5.

Each processing element 1-1, 1-
2, ..., 1-n are provided with a processor 10, a local memory 11, a processor state management unit 12, and an access history management unit 13. The processor state management unit 12
The processor 10 manages processor state information.
PSW (program status word), a register, a processor state storage unit 12a for storing processor state information including the contents of local memory, and a processor state restoring unit 12b for restoring the processor state information at any time. . The access history management unit 13 includes an access history storage unit 13a for storing an access history of the shared memory 2 of each processor, and an access history restoration unit 13b for restoring the order of access to the shared memory 2.
Is provided. The local memory 11 is not always necessary and is used as a component for the following description.

The shared memory 2 is provided with a data holding unit 20, a version management unit 21, and an access identification unit 22. The data holding unit 20 is for storing data operated by each processing element 1-1, 1-2, ..., 1-n. Version management unit 21
Manages the version number indicating the number of updates to the data and the number of times of reading corresponding to the value of the version number corresponding to each data stored in the data holding unit 20. The number of readings counter 21a and the number of updates counters 21b is provided. The access identification unit 22 is for recording a flag (access information) for identifying whether or not the area is accessed in units of memory blocks. Further, not only is it discriminated whether or not it is accessed, but read / write access may be discriminated and recorded. A description will be given later of the operation for each situation where the read / write access is not recorded separately by the access identification unit 22.

The checkpoint management unit 3 is provided with a snapshot management unit 30 and a reproduction execution management unit 31. The snapshot management unit 30 periodically executes each processing element 1-1, when the program is executed.
It is for instructing 1-2, ..., 1-n to execute a snapshot. The snapshot management unit 30
Each processing element 1-1, 1-2, ..., 1-
The processor state management unit 12 of n stores the processor state and the contents of the local memory 11, and the access history management unit 13 stores the information of the shared memory 2. The reproduction execution management unit 31 instructs each predetermined unit to reproduce and execute the program from an arbitrary checkpoint state at the time of reproducing the program. Since the program is reproduced and executed from the state at the arbitrary checkpoint, the processor state The management unit 12 restores the processor state of the checkpoint and the local memory 11, and the access history management unit 13 restores the information in the shared memory 2.

Under the control of the checkpoint management unit 3, the secondary storage device 4 has various data for reproducing the program execution, for example, the data in the data holding unit 20 and the read number counter of the version management unit 21. 21a
And the value of the update counter 21b.

Next, the operation of this embodiment will be described for each situation. Here, processing element 1-
An operation of an arbitrary processing element P in 1, 1-2, ..., 1-n will be described as an example.

(1) A method in which the access identification unit 22 does not distinguish between reading and writing. (1-A) During program execution. Here, the processing element P is the shared memory 2
Data from the address ADDR1 of the register X
The read operation to the shared memory 2 will be described by using an example of issuing a read command to be stored in the memory. The state of the shared memory 2 before the processing of this instruction is executed is shown in FIG.
It is assumed to be as shown in (a). That is,
Data 5 is stored in the address ADDR1 of the data holding unit 20, and the version management unit 21 corresponds to this data.
Of the memory block corresponding to the address ADDR1 of the access identification unit 22 has a value of “o”.
ff ”.

First, in response to a read command, the access flag of the memory block corresponding to the address of the access identification unit 22 is turned "on". In addition, the data holding unit 20
The data 5 of the address is fetched from and is passed to the processor of the processing element P.

The version management unit 21 increments the read count counter 21a of the address (value is 4), extracts the value 2 of the update count of the address from the update count counter 21b, and processes the processing element P.
To the access history management unit 13. The access history management unit 13 of the processing element P records the value in the access history storage unit 13a as a log.

After the above-mentioned read operation, the state of the shared memory 2 is shown in FIG. 2B, and the contents of the log stored in the access history storage unit 13a of the access history management unit 13 are shown in FIG.
(C), Processor 10 of Processing Element P
The contents of the register X are changed as shown in FIG.

Next, a write operation to the shared memory 2 will be described using an example in which the processing element P issues an instruction to write the contents of the register X to the address ADDR2 of the shared memory 2. It should be noted that the state of the shared memory 2 before the processing of this instruction is executed is shown in FIG. 3A, the register X of the processor 10 of the processing element P.
It is assumed that the contents of the above are as shown in FIG. That is, the address ADDR2 of the data holding unit 20
Stores data 5 and the value of the read number counter 21a of the version management unit 21 is 4 in correspondence with this data.
The value of the update counter 21b is 2, and the flag of the memory block corresponding to the address ADDR2 of the access identification unit 22 is "on". The content of the register X is data 10.

First, in response to a write command, the access flag of the memory block corresponding to the address of the access identification unit 22 is turned "on". In addition, the data holding unit 2
0 sets the data 10 of the register X from the processor 10 of the processing element P to the address.

The version management unit 21 uses the value 4 of the read number counter 21a of the address and the update number counter 2 of the address.
The value 2 of 1b is passed to the access history management unit 13 of the processing element P, and the read number counter 21a
Is cleared and the update number counter 21b is incremented. The access history management unit 13 of the processing element P records the value of the read count counter 21a and the value of the update count counter 21b (version number) as a log.

After the above write operation, the shared memory 2
3C, the contents of the log stored in the access history storage unit 13a of the access history management unit 13 are shown in FIG.
It changes as shown in (d).

The snapshot management unit 30 instructs each of the processing elements 1-1, 1-2, ..., 1-n to take a snapshot in order to periodically make a checkpoint. At this time, the snapshot management unit 30 causes the processing elements 1-1, 1-
2, ..., 1-n may be interrupted, or the snapshot management unit 30 writes a snapshot instruction to a specific area of the shared memory 2, and each processor periodically polls the specific area. You can do it.

To generate a checkpoint, the processor 10 of each processing element 1-1, 1-2, ..., 1-n interrupts normal processing. The processor state management unit 12 saves the state of the processor 10 and the contents of the local memory 11 in the processor state storage unit 12a. Since the contents of the local memory are only accessed by the processor 10, it is sufficient to store only the portion where the value is changed. The processor state is the contents of various registers and PSW necessary for restoring the program from that point.

The snapshot management unit 30 refers to the access information of the access identification unit 22 to search for a portion accessed since the previous snapshot. For example, a part of the shared memory 2 immediately before taking the snapshot is shown in FIG.
It is assumed to be as shown in (a).

In this case, since the flags of the memory blocks i and k are "on" in the access identification unit 22,
The snapshot management unit 30 stores the data of the memory blocks i and k of the data holding unit 20 stored in the shared memory 2 and the read number counter 21 a of the version management unit 21.
And the value of the update counter 21b is stored in the secondary storage device 4. FIG. 4B shows information recorded by the snapshot.

Upon completion of these processes, the snapshot management unit 30 causes the access identification unit 22 to clear the access information and informs each processor that the snapshot is completed. Each processor resumes normal processing. FIG. 4C shows the contents of the shared memory 2 after the snapshot, which corresponds to FIG.

(1-B) At the time of reproducing the program. In order to reproduce the processing from an arbitrary checkpoint, the reproduction execution management unit 31 uses each processing element 1-
1, 1-2, ..., 1-n are notified of checkpoint positions to be reproduced.

The processor state restoring unit 12b of the processor state managing unit 12 searches the processor state storing unit 12a for the processor state at the checkpoint position notified by the reproduction execution managing unit 31 and the contents of the local memory. 10 and local memory 11
Set to.

The access history restoration unit 13b of the access history management unit 13 prepares to read the log from the beginning at the checkpoint so that the history from the notified checkpoint can be accessed.

The reproduction execution management unit 31 restores the state of the shared memory 2 from the secondary storage device 4 by using the information recorded by the snapshots of the checkpoints to be reproduced and the checkpoints before that from the secondary storage device 4, respectively. The latest information of the memory block is searched and set in the data holding unit 20 and the version management unit 21 (reading counter 21a, updating counter 21b) of the shared memory 2.

When these processes are completed, the reproduction execution management section 31 determines the processing elements 1-1, 1-
2, ..., 1-n is notified that the preparation for execution reproduction is completed.

Here, the read operation for the shared memory 2 will be described using an example in which the processing element P issues a read command for reading data from the address ADDR1 of the shared memory 2 and storing it in the register X. The state of the shared memory 2 before the processing of this instruction is executed is shown in FIG. 5A, and the log stored in the access history storage unit 13a of the processing element P is shown in FIG. 5B. It is assumed that

When a read operation is performed on the shared memory 2, the processor 10 waits until the log information from the access history management unit 13 and the update count counter 21b of the version management unit 21 become equal. When the two values become equal, the version management unit 21 increments the value of the read number counter 21a, passes the data of the data holding unit 20 to the processor 10, and continues the processing. The access history management unit 13 advances the pointer of the log. In this example, the processor 10 is waited until the value of the update counter 21b corresponding to ADDR1 becomes 2, and when the value of the update counter 21b becomes 2, the read counter 21a is incremented.
The state of the shared memory 2 after the processing of this instruction is as shown in FIG.

Next, the write operation to the shared memory 2 will be described using an example in which the processing element P issues an instruction to write the contents of the register X to the address ADDR2 of the shared memory 2. The state of the shared memory 2 before the processing of this instruction is shown in FIG. 6A, the register X of the processor 10 of the processing element P is shown.
6B, and the log stored in the access history storage unit 13a of the access history management unit 13 is as shown in FIG. 6C.

When the processor 10 performs a write operation on the shared memory 2, the version number (update count) from the access history management unit 13 and the version management unit 21.
The update count counter 21b has the same value, and the read count from the access history management unit 13 is equal to the read count counter 21a. When the values become equal, the shared memory 2 stores the data from the processor 10 in the data holding unit 20, increments the update count counter 21b of the version management unit 21, and clears the read count counter 21a. Then, the processing of the processor 10 is continued, and the pointer of the log of the access history management unit 13 is advanced.

In this example, the processor is waited until the value of the update counter 21b corresponding to ADDR2 becomes 2 and the value of the read counter 21a becomes 4, and the value of the update counter 21b becomes 2. When the value of the read number counter 21a becomes 4, the update number counter 21b is incremented and the read number counter 21a is cleared. The state of the shared memory 2 after the processing of this instruction is as shown in FIG. 6 (d).

(2) A method of distinguishing read / write access in the access identification unit 22. As described above, the access identification unit 22 reads / reads.
In the method of not distinguishing the write access, the access history management unit 13 only determines whether or not the access is made by the “on / o”.
Although it was recorded as “ff”, the distinction method is “R (Read)” when only writing, “W (Write)” when only writing, and “R / W” when both are performed.
(Read / Write) "and" off "when not accessed.

(2-A) During program execution. Here, the processing element P is the shared memory 2
The read operation to the shared memory 2 will be described using an example of issuing an instruction to store the contents of the address ADDR1 in the register X.

First, in response to the read command, if the access flag of the memory block corresponding to the address ADDR1 of the access identification unit 22 is W, it is set to "R / W", otherwise it is set to "R". Further, the data of the address is taken out from the data holding unit 20 and passed to the processor of the processing element P.

The version management unit 21 increments the read count counter 21a of the address, extracts the update count of the address from the update count counter 21b, and passes it to the access history management unit 13 of the processing element P. The access history management unit 13 of the processing element P records the value as a log.

Next, a read operation to the shared memory 2 will be described using an example in which the processing element P issues an instruction to write the contents of the register X to the address ADDR2 of the shared memory 2.

First, in response to a write command, if the access flag of the memory block corresponding to the address of the access identification unit 22 is "R", it is set to "R / W", and otherwise it is set to "W". . Further, the data holding unit 20 sets the data of the register X from the processor 10 of the processing element P to the address.

The version management unit 21 reads the value of the read counter 21a of the address and the update counter 21b.
Is passed to the access history management unit 13 of the processing element P, the read number counter 21a is cleared, and the update number counter 21b is incremented.
Access history management unit 13 of processing element P
Reads the value of the read number counter 21a and the value of the update number counter 21b (update version 9 is recorded as a log.

The snapshot management section 30 instructs each of the processing elements 1-1, 1-2, ..., 1-n to take a snapshot in order to periodically make a checkpoint.

In order to generate a checkpoint, the processor 10 of each processing element 1-1, 1-2, ..., 1-n interrupts normal processing. The processor state management unit 12 saves the state of the processor 10 and the contents of the local memory 11 in the processor state storage unit 12a.

The snapshot management unit 30 refers to the access information of the access identification unit 22 and searches for a portion accessed since the previous snapshot. For example, a part of the shared memory 2 immediately before taking the snapshot is shown in FIG.
It is assumed to be as shown in (a).

In this case, since the flag of the memory block k is "W" in the access identification unit 22, the snapshot management unit 30 is stored in the shared memory 2.
The data in the data holding unit 20 in the portion of the memory block k where the write operation is performed, the read number counter 21a and the update number counter 21b of the version management unit 21
The value of is stored in the secondary storage device 4. Further, the snapshot management unit 30 reads the number-of-reads counter 21a for the portion of the memory block i in which the flag of the access identification unit 22 is “R” and only the read operation is performed.
And the value of the update counter 21b is stored in the secondary storage device 4. FIG. 7B shows information recorded by the snapshot.

Upon completion of these processes, the snapshot management unit 30 causes the access identification unit 22 to clear the access information and informs each processor that the snapshot has been completed. Each processor resumes normal processing. FIG. 7C shows the contents of the shared memory 2 after the snapshot corresponding to FIG. 7A.

(2-B) At the time of reproducing the program In order to reproduce the process from an arbitrary checkpoint, the reproduction execution management section 31 makes each processing element 1-
1, 1-2, ..., 1-n are notified of checkpoint positions to be reproduced.

The processor state management unit 12 retrieves the processor state at the checkpoint position notified by the reproduction execution management unit 31 and the local memory contents from the processor state storage unit 12a, and retrieves each of them.
And in the local memory 11.

The access history management unit 13 prepares to read the log from the beginning at the checkpoint so that the history from the notified checkpoint can be accessed.

In order to restore the state of the shared memory 2, the reproduction execution management unit 31 obtains the latest information of each memory block from the information recorded by the snapshots of the checkpoints to be reproduced and the checkpoints before that. The data is retrieved and set in the data holding unit 20 and the version management unit 21 (read count counter 21a, update count counter 21b) of the shared memory 2. At this time, it is assumed that the data in the data holding unit 20 of the shared memory 2 and the information in the version management unit 21 are searched separately.

When these processes are completed, the reproduction execution management section 31 determines the processing elements 1-1, 1-
2, ..., 1-n is notified that the preparation for execution reproduction is completed.

When the read operation is performed on the shared memory 2, the processor 10 waits until the log information from the access history management unit 13 and the value of the update count counter 21b of the version management unit 21 become equal. When the two values become equal, the version management unit 21 increments the value of the read number counter 21a, passes the data of the data holding unit 20 to the processor 10, and continues the processing. The access history management unit 13 advances the pointer of the log.

When the processor 10 performs a write operation on the shared memory 2, the access history management unit 1
The version number (update count) from 3 is equal to the value of the update count counter 21b of the version management unit 21, and
Waiting is performed until the number of times of reading from the access history management unit 13 and the value of the number of times of reading counter 21a become equal.
When the values become equal, the shared memory 2 stores the data from the processor 10 in the data holding unit 20, increments the update count counter 21b of the version management unit 21, and clears the read count counter 21a. Then, the processing of the processor 10 is continued, and the pointer of the log of the access history management unit 13 is advanced.

[0062]

As described above, according to the present invention, since the program can be reproduced only from the number of data updates and accesses and the data change portion of the shared memory, the recording amount of information necessary for the program reproduction can be reduced. Can be reduced. Further, since the program reproduction from an arbitrary checkpoint is synchronized by the version number, there is an effect that it can be realized without requiring a global clock or a common storage area.

[Brief description of drawings]

FIG. 1 is a block diagram showing the main configuration of a parallel computer according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a read operation at the time of executing a program in a method in which the access identification unit 22 does not distinguish read / write.

FIG. 3 is a diagram for explaining a write operation at the time of program execution in a method in which the access identification unit 22 does not distinguish read / write.

FIG. 4 is a diagram for explaining a snapshot in a method in which the access identification unit 22 does not distinguish between reading and writing.

FIG. 5 is a diagram for explaining a read operation at the time of reproducing a program in the method of distinguishing read / write by the access identification unit 22.

FIG. 6 is a diagram for explaining a write operation at the time of reproducing a program in the method of distinguishing read / write by the access identification unit 22.

FIG. 7 is a diagram for explaining a snapshot in a method of distinguishing read / write by the access identification unit 22.

[Explanation of symbols]

1-1, 1-2, ..., 1-n ... Processing element, 2 ... Shared memory, 3 ... Checkpoint management unit, 4
... secondary storage device, 5 ... bus, 10 ... processor, 11 ...
Local memory, 12 ... Processor state management unit, 13 ...
Access history management unit, 20 ... Data holding unit, 21 ... Version management unit, 21a ... Read number counter, 21b ...
Update counter, 22 ... Access identification unit, 30 ... Snapshot management unit, 31 ... Reproduction execution management unit.

Claims (2)

[Claims] 1. In a parallel computer for accessing a shared memory from a plurality of processing elements, data holding means for storing data, and updating of the data corresponding to the data held in the data holding means Version management means for recording information indicating the number of times and the number of times of reading, and an access identification for recording information for identifying whether or not an access operation is performed in a memory block unit including the data held in the data holding means And a shared memory provided with means for instructing the processing element to execute a snapshot during program execution, and performing an access operation between checkpoints according to the information recorded by the access identification means. Data held by the holding means, And snapshot management means for storing the information recorded by the version management means, and for instructing the processing element to reproduce and execute the program from an arbitrary checkpoint when reproducing the program, and storing the information by the snapshot management means. A reproduction execution management unit for restoring the shared memory based on the contents, a checkpoint management unit provided with, and an access history for the shared memory stored in response to a snapshot execution instruction from the snapshot management unit. Access history storage means, processor state storage means for storing processor state information at the time of checkpoint, and storage by the processor state storage means in response to a program reproduction execution instruction from the reproduction execution management means. Processor state restoration means for restoring processor state information, the shared memory reproduced by the reproduction execution management means after synchronization of program reproduction based on the access history stored by the access history storage means, and A parallel computer comprising: a processor that re-executes a program based on the processor state information restored by the processor state restoring means; and a processing element provided with: 2. A program execution reproducing method in a parallel computer for accessing a shared memory from a plurality of processing elements, wherein the shared memory holds a data holding unit for storing data, and the data holding unit holds the data holding unit. The version management means for recording the information indicating the number of times of updating and the number of times of reading the corresponding data, and whether or not the access operation is performed in a memory block unit including the data held in the data holding means. Access identification means for recording information for identifying whether or not is provided, when executing the program, to execute a snapshot to the processing element, according to the information recorded by the access identification means, The holding means in which an access operation is performed between checkpoints The data held by the device, the information recorded by the version management unit, the access history to the shared memory and the processor state information at the checkpoint are recorded, and when the program is reproduced and executed, based on the access history, A method for reproducing a program execution, characterized in that after the program reproduction is synchronized, the program is re-executed according to the shared memory and the processor state reproduced based on the information recorded by the snapshot.