JPH07131348A - Characteristic display method and automatic corrector for serial/parallel a/d converter - Google Patents

Abstract

PURPOSE:To facilitate fine adjustment and to make dispersion in the adjusted result hardly generated by inputting an inclined wave signal to a serial/parallel analog/digital(A/D) converter to be measured, converting the signal to a digital value, storing that value in a memory connected to the output terminal of the serial/parallel A/D converter and displaying the digital value stored in the memory as a histogram. CONSTITUTION:The inclined wave such as a triangular wave or sawtooth wave is inputted to an input terminal 12 of a serial/parallel A/D converter 10. This inclined wave is converted to the digital value in the serial/parallel A/D converter 10 and outputted from an output terminal 28. As for a digital value from this terminal 28, its output frequency is counted for each digital value by a CPU 64. Then, the CPU 64 prepares image data for performing the histogram display of the digital value and outputs them to a display memory 66. The display 68 displays the histogram based on the image data in the display memory 66. At such a time, an adjusting person observes the displayed histogram and when the histogram is flat, the adjustment is finished as it is but when not flat, a voltage source 26 is adjusted again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a characteristic measuring method for a serial / parallel type analog / digital converter, and more particularly to an analog / digital converter for outputting a digital value as a lower bit in the serial / parallel type analog / digital converter. The present invention relates to a method for measuring characteristics of a serial-parallel type analog-digital converter and an automatic calibration device suitable for adjusting the reference voltage value.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram of a serial / parallel type analog-digital converter 10. The input terminal 12 is connected to the input of a track hold circuit (or sample hold circuit) 14. The output of the track and hold circuit 14 is connected to the input of the first analog-digital converter 16 and the input of the delay line 24.
The output of the first analog / digital converter 16 is connected to the input of the digital / analog converter 20 and the digital error correction circuit 18. Digital-analog converter 2
The output of 0 and the output of the delay line 24 are connected to the inverting input terminal and the non-inverting input terminal of the differential amplifier 22, respectively.
The output terminal of the differential amplifier circuit 22 is connected to the input of the second analog-digital converter 24. A reference voltage source 26 (or a digital / analog converter) is connected to the second analog / digital converter 24. The output of the second analog-to-digital converter 24 is the digital error correction circuit 1
8 is connected. The digital error correction circuit 18 is connected to the output terminal 28.

The conversion operation of the serial-parallel type analog-to-digital converter 10 will be described below. The analog signal input to the input terminal 12 is input to the track hold circuit or sample hold circuit 14 and held for a certain period. The signal held in the track and hold circuit 14 is converted into a digital value as the upper bit by the first analog / digital converter 16 and input to the digital error correction circuit 18 and the digital / analog converter 20. The analog value from the digital / analog converter 20 is input to the inverting input terminal of the differential amplifier 22. The signal from the track hold circuit 14 is input to the non-inverting input terminal of the differential amplifier 22 through the delay line 24. As for the delay time of the delay line 24, the signal from the track hold circuit 14 is
It is equal to the time after being digitally converted by the digital converter 16 and further converted to an analog signal by the digital / analog converter 20 and output. The analog signal amplified by the differential amplifier 22 is supplied to the second analog-digital converter 24.
Is input to the digital error correction circuit 18 after being converted into a digital value as a lower bit. The digital error correction circuit 18 compensates for the non-linearity of the first analog-to-digital converter 16 which is well known to those skilled in the art. The digital error correction circuit 18 outputs the digital value of the serial-parallel type analog-digital converter 10 as a whole, which is equal to the number of digits obtained by adding the digits of the upper bits and the lower bits.

However, in such a serial-parallel type analog-digital converter, if the voltage value of the reference voltage source 26 of the second analog-digital converter 24 is not an appropriate value, as shown in FIGS. 3 and 4. It causes an error.

FIG. 3 is a diagram showing the input voltage-output digital value characteristic of the analog-digital converter 10 as a whole when the voltage value of the reference voltage source 26 is smaller than an appropriate value.
The input voltage values 34 and 36 are input voltage values for which the output digital value of the first analog-to-digital converter 16 that outputs the digital value as the upper bit increases by one. The characteristic 30 of the serial-parallel type analog-digital converter 10 shifts to a value larger than the ideal value 32 as the output digital value as the lower bit of the second analog-digital converter 24 increases. This is because the voltage value of the reference voltage source 26 is smaller than the proper value, so that the output digital value of the second analog-digital converter becomes larger than the proper output digital value. Further, immediately before the voltage values 34 and 36 at which the output digital value of the first analog-digital converter increases by 1, the output digital value of the second analog-digital converter has already reached the maximum value and is saturated. Therefore, the input voltage range for outputting the digital values a and b is wide.

FIG. 4 is a diagram showing the input voltage-output digital value characteristic of the entire analog-digital converter 10 when the voltage value of the reference voltage source 26 is larger than the proper value. The input voltage values 42 and 44 are input voltage values at which the output digital value of the higher-order analog-digital converter 16 is incremented by 1. Characteristic 40 of the serial-parallel type analog-digital converter 10
Becomes larger than the ideal value 32 as the output digital value of the second analog-digital converter 24 becomes larger. This is because the output digital value of the second analog-digital converter 24 becomes smaller than the proper output digital value because the voltage value of the reference voltage source 26 is too large than the proper value. At the voltage values 42 and 44 in which the output digital value of the first analog-digital converter increases by 1, the digital values are output by jumping over the digital values c to d and e to g.

In order to prevent the above error from occurring, the voltage value of the reference voltage source 26 may be adjusted to an appropriate value. Conventionally, in order to adjust the voltage value of the reference voltage source 26, a digital-analog converter (not shown) is connected to the output terminal 28 of the serial-parallel type analog-digital converter 10, and a triangular wave or Enter the sawtooth wave,
The adjuster made the adjustment while displaying the waveforms shown in FIGS. 3 and 4 on the oscilloscope and observing the waveform. When displaying a waveform, the abscissa of the oscilloscope is input, that is, the input voltage, and the ordinate is the output of the digital-analog converter. The adjuster adjusted the displayed waveform to be a straight line like the waveform 50 in FIG.

However, in the above adjusting method, noise and
1 LSB due to the effect of quantization error of the digital-analog converter connected to the measured analog-digital converter
Fine adjustments such as evaluating (least significant bit) are not possible.

[0008] The individual who makes the adjustment causes individual differences, and the adjustment results vary.

Further, when the input voltage versus the output digital value is displayed, a high-speed digital-analog converter having more bits than the number of bits of the analog-digital converter to be measured is required, which is expensive. .

Further, there has been a problem that the characteristics of the digital-analog converter connected to the output of the serial-parallel type analog-digital converter are also affected.

Therefore, an object of the present invention is to solve the above-mentioned problems by providing a characteristic measuring method for a serial-parallel type analog-digital converter suitable for adjusting a reference voltage value in the serial-parallel type analog-digital converter. Is to provide.

[0013]

A serial-parallel type analog / digital converter having a first analog / digital converter for outputting a digital value of upper bits and a second analog / digital converter for outputting a digital value of lower bits. The ramp wave signal is input to the digital converter and converted into a digital value. The digital value from the serial-parallel type analog-digital conversion value is stored in the memory. Create and display a histogram from the digital values stored in memory.

[0014]

FIG. 2 shows an embodiment of a characteristic display device using the characteristic measuring method of the present invention. The output terminal 28 of the serial-parallel type analog-digital converter 10 of FIG. 9 is connected to the input terminal 60. A signal generator (not shown) that generates a ramp wave such as a triangular wave and a sawtooth wave is connected to the input terminal 12 of the serial-parallel analog-digital converter 10.
The input of the memory 62 is connected to the input terminal 60. CP
The U 64, the memory 62 and the display memory 66 are connected by a bus. The display memory 66 is connected to the display 68.

FIG. 1 is a flow chart for adjusting the voltage value of the reference voltage source 26 of the serial-parallel type analog-digital converter 10 using the characteristic measuring method of the present invention. The operation of the characteristic display device using the characteristic measuring method of the present invention will be described below with reference to FIGS. Adjustment is started in step 70. In step 72, a ramp wave such as a triangular wave or a sawtooth wave is input to the input terminal 12 of the serial-parallel type analog-digital converter 10. The frequency fs of the ramp wave may be sufficiently lower than the clock frequency fc of the serial-parallel type analog-digital converter. The ramp wave is a series-parallel analog
The digital value is converted by the digital converter 10 and output from the output terminal 28. In step 74, the output terminal 28
The digital value from is input to the input terminal 60 of FIG. The digital value stored in the memory 62 can be counted by the CPU 64 for each individual digital value. In step 76, the CPU 64 creates image data for displaying a histogram of digital values,
Output to the display memory 66. The display 68 displays a histogram based on the image data in the display memory 66. In step 78, the coordinator displays the display 68.
Observe the histogram of the digital values displayed on the screen. If the histogram is flat, proceed to step 82 to end the adjustment. If the histogram is not flat, proceed to step 8
0, depending on the shape of the histogram, the reference voltage source 26
Readjusts the voltage value of and returns to step 72.

When the automatic adjustment is performed, step 78
Then, the CPU 64 determines whether the histogram is flat,
When it is determined that the surface is not flat, the process proceeds to step 80. In step 80, the CPU 64 changes the voltage value of the reference voltage source 26. In order to change the voltage value, the reference voltage source 26
Alternatively, a digital / analog converter may be used, or the CPU 64 may control a motor or the like to rotate an adjusting knob such as a variable resistor.

FIG. 6 is an example of a histogram display by the characteristic measuring method of the present invention when the reference voltage value of the reference voltage source 26 is smaller than the proper value. The digital values a and b in the histogram 90 are the digital values a and b in FIG.
It corresponds to each. If the distribution of the occurrence frequency of the input voltage value is uniform, the histogram should be flat, but the frequency of occurrence of the digital values a and b is large. Since the voltage value of the reference voltage source 26 is smaller than the proper value, the second analog-digital converter 24 which outputs the lower bit immediately before the output digital value of the first analog-digital converter 16 increases by 1. This is because the output digital value of is saturated and the frequency of occurrence of the same digital value increases. There is some variation in the substantially flat portion other than the digital values a and b, but this is due to the error and noise of the second analog-digital converter. If the noise is white Gaussian noise, the frequency of the histogram is increased and the influence of noise is reduced by increasing the number of conversions of the serial-parallel type analog-digital converter 10, that is, increasing the digital value stored in the memory 62. You can

FIG. 7 is an example of a histogram display by the characteristic measuring method of the present invention when the voltage value of the reference voltage source 26 is larger than the proper value. Digital values c to d and e to g in the histogram 92 correspond to digital values c to d and e to g in FIG. C, respectively. If the distribution of the occurrence frequency of the input voltage value is uniform, the histogram should be flat, but the occurrence frequency of the digital values c to d and e to g is small. This is because the voltage value of the reference voltage source 26 is larger than the proper value, and therefore the first analog signal which outputs the upper bit before the digital value of the lower bit by the second analog-digital converter 24 becomes the predetermined digital value.・
This is because the digital value of the digital converter is increased by 1, and a digital value whose frequency of occurrence is low is generated.

FIG. 8 shows a histogram display example according to the present invention when the voltage value of the reference voltage source 26 of the serial-parallel type analog-digital converter 10 is adjusted to an appropriate value. The adjuster ends the adjustment when a flat histogram like the histogram 94 is displayed. At this time, the voltage value of the reference voltage source 26 is adjusted to the optimum value.

In step 78, the CPU 64 automatically determines whether or not the histogram is flat. To determine whether the histogram is flat, the upper limit threshold and the lower limit threshold are determined according to the number of digital values taken in, and the upper limit threshold is determined. If there is a digital value with a frequency exceeding the value, the reference voltage value is increased in step 80, and if a digital value with a frequency less than or equal to the lower limit threshold value is present, the reference voltage value is decreased in step 80. In this case, if a digital / analog converter is used for the reference voltage source 26, the CPU 64 can directly send a digital signal to the digital / analog converter to adjust the reference voltage.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the embodiments described herein, and various modifications and changes can be made as necessary without departing from the gist of the present invention. It will be apparent to those skilled in the art that changes can be made.

For example, it is desirable that the ramp wave input to the serial-parallel type analog-digital converter 10 preferably generate a voltage value within the conversion range of the analog-digital converter at a uniform frequency. A gate circuit may be provided in front of the input terminal 12 to eliminate a waveform portion that does not have a uniform occurrence frequency and to pass only a portion that occurs at a uniform frequency.

Further, in the embodiment shown in FIGS. 6 and 7, the histogram display range is set such that the upper bit digital value is 2
Although the range is increased, it may be wider than the range in which the digital value of the higher-order bit is increased by 1.

Although the serial / parallel type analog / digital converter of the embodiment is a two-step type, it can be used for a serial / parallel type analog / digital converter of two steps or more.

In the embodiment, the adjuster determines whether the histogram is flat and adjusts the reference voltage source 26. However, the CPU 64 determines whether the histogram data is flat and the reference voltage is adjusted. Automatic calibration may be performed using a digital-to-analog converter for source 26. CPU64
When determining whether or not the histogram data is flat, it may be determined whether or not the frequency of the histogram data is within the predetermined upper and lower limits, and the variance of the histogram frequency is calculated. Alternatively, it may be determined whether the variance is equal to or less than a predetermined variance value.

In the above automatic calibration, the memory 62, C
PU64 and reference voltage source (digital / analog converter)
26 may be provided as a calibration device in the serial-parallel type analog-digital converter 10.

[0027]

According to the method of measuring the characteristics of the serial-parallel type analog-digital converter of the present invention, the following effects can be obtained.
Since the memory directly takes in the digital value from the series-parallel type analog-digital converter, it is less susceptible to noise,
1LSB of digital value from analog-digital converter
Fine adjustments such as evaluating (least significant bit) can be made. Individual differences between adjusters are unlikely to occur, and variations in adjustment results are unlikely to occur. Further, when the histogram is displayed, the memory directly takes in the output digital value of the serial-parallel type analog-digital converter, so that an expensive digital-analog converter is not required and the display can be performed at low cost.

[Brief description of drawings]

FIG. 1 is a flow chart for adjusting a reference voltage source of a serial / parallel type analog / digital value by using a method of measuring characteristics of a serial / parallel type analog / digital converter of the present invention.

FIG. 2 is an example of a characteristic display device for performing the characteristic measuring method of the present invention.

FIG. 3 is a diagram showing an input voltage-output digital value characteristic of the analog-digital converter 10 as a whole when the voltage value of a reference voltage source 26 is smaller than an appropriate value.

FIG. 4 is a diagram showing input voltage-output digital value characteristics of the entire analog-digital converter 10 when the voltage value of the reference voltage source 26 is larger than an appropriate value.

FIG. 5 is a diagram showing input voltage-output digital value characteristics of the entire analog-digital converter 10 when the voltage value of the reference voltage source 26 is an appropriate value.

FIG. 6 is an example of a histogram display by the characteristic measuring method of the present invention when the reference voltage value of the reference voltage source 26 is smaller than an appropriate value.

FIG. 7 is a histogram display example according to the characteristic measuring method of the present invention when the voltage value of the reference voltage source 26 is larger than an appropriate value.

FIG. 8 is an example of a histogram display according to the present invention when the voltage value of the reference voltage source 26 is adjusted to an appropriate value.

FIG. 9 is a block diagram of a serial-parallel type analog-digital converter.

[Explanation of symbols]

 10 Serial-parallel type analog-digital converter 16 First analog-digital converter 24 Second analog-digital converter 62 Memory 90 Histogram 92 Histogram 94 Histogram

Claims (2)

[Claims] 1. An input signal is input to first and second analog-digital converters, said first analog-digital converter is a digital value as upper bits, and said second analog-digital converter is lower bits. In the method for measuring the characteristics of a serial-parallel type analog-to-digital converter that outputs a digital value of, a ramp wave signal is input as the input signal and converted into a digital value, the digital value is recorded in a memory, and A method of displaying characteristics of a serial-parallel type analog-digital converter, which is characterized by displaying a histogram of digital values. 2. A first analog-digital converter which receives an input signal and outputs a digital value as upper bits, and a second analog-digital converter which receives the input signal and outputs a digital value as lower bits. A serial-parallel type analog-to-digital converter automatic calibration device having: a memory for recording a converted digital value by inputting a ramp wave signal as the input signal; and histogram data of the digital value in the memory. A serial-parallel type analog-to-digital converter automatic calibrating device, comprising: a calibration means for generating and calibrating the reference voltage of the second analog-to-digital converter based on the histogram data.