JPH07131298A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a means which can easily set a control signal for correcting the timing of a data signal and a clock signal supplied to flip-flop circuits as to the semiconductor integrated circuit device which uses many flip-flops. CONSTITUTION:This device is equipped with the flip-flop circuits F1-F8 and an electrically erasable programmable read-only memory (EEPROM) 10 wherein a specific control signal supplied to a selector 1 that the flip-flop circuits F1-F8 have is previously programmed; and address signals A1, A2, A3, and A4 which specify the selector are connected to the address input terminal of the EEPROM 10, and output signals DO1-DO8 of the EEPROM 10 are connected to control terminals 81-88, and 91-98 of the corresponding flip-flop circuits F1-F8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a circuit for correcting the timing of a data signal and a clock signal supplied to a flip-flop circuit.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit device of this type is
As shown in the block diagram of FIG. 2, the flip-flop circuit F includes selectors 1 and 2, delay circuits 3 and 4, a data input terminal D, a clock input terminal C, an output terminal Q, and an output terminal QB (inversion of Q). And a known flip-flop circuit 5 including a master side (not shown) at the front stage and a slave side (not shown) at the rear stage.

The selector 1 receives either a data signal D supplied from a terminal 6 or a signal obtained by delaying the data signal D by a delay circuit 3 for a predetermined time.
Selected in response to the high (H) level of the control signal Cj supplied via the control signal Cj and supplied as the data signal of the flip-flop circuit 5. On the other hand, the selector 2 supplies either the clock signal C supplied from the terminal 7 or the signal obtained by delaying the clock signal C by the delay circuit 4 for a predetermined time, through the terminal 8. It is selected in response to the high (H) level of Ci and supplied as the clock signal of the flip-flop circuit 5.

[0004]

[Table 1]

Here, α indicates the internal state of the master side of the flip-flop circuit.

Referring to Table 1 showing the truth table of the flip-flop circuit 5, the flip-flop circuit 5 is
The data signal D is read into the flip-flop circuit 5 in response to the timing when the clock signal C changes from the low (L) level to the H level, and is read in response to the timing when the clock signal C changes from the H level to the L level. It operates so as to output the data signal D from the flip-flop circuit 5.

Referring also to FIG. 3A showing a timing chart for explaining the operation of the flip-flop circuit 5, the clock signal C when the data signal D is at H level.
Is changed from the L level to the H level after the time t1, the H level signal is output to the output terminal Q and the L level signal is output to the output terminal QB.

However, if the change timings of these data signal and clock signal are deviated, the flip-flop circuit 5 may malfunction.

Further referring to FIG. 3B showing a timing chart for explaining malfunction of the flip-flop circuit 5, for example, the wiring of the clock signal C is also common to many other flip-flop circuits. Suppose The clock signal C is delayed with respect to the data signal D by a time t2 longer than the time t1 due to the gate capacitance of these flip-flop circuits, the wiring resistance and the wiring capacitance thereof that increase in proportion to the wiring length. As a result, since the data signal D has already changed to the L level at the timing when the clock signal changes from the L level to the H level, the L level and the H level signals are output to the output terminals Q and QB. It becomes the same as the state before the data change.

In order to correct the timing shift between the data signal and the clock signal as described above, the data signal D and the clock signal C are supplied via the delay circuits 3 and 4.

That is, in order to delay the data signal D, the selector 1 selects the delay circuit 3 and the selector 2 selects the clock signal C as it is.
And Cj may be set. Further, when the wiring delay of the data signal D is large, the delay circuit may be selected to be inserted on the clock signal side.

Further, as another example of this type of circuit, there is a flip-flop circuit described in Japanese Patent Laid-Open No. 3-34617.

Referring to FIG. 4 shown in a block diagram, this flip-flop circuit includes latch circuits 41 and 42.
And a delay circuit 43 and a selector 44. The data signal DI is supplied to the input terminal D of the latch circuit 41, the latched output signal Q is supplied to the input terminal D of the latch circuit 42, and the latch output DO is output from the output terminal Q.

The clock signal CK is supplied to the input terminal G of the latch circuit 41 and one input terminal of the selector 44 and to the other input terminal of the selector 44 through the delay circuit 43, and the selection signal S is supplied.
In response to C, the output of the selector 44 is supplied to the input terminal G of the latch circuit 42.

According to this structure, when correcting the delay of the clock signal, the latch circuit 4 is caused by the output signal CKs of the selector 44 delayed by the delay circuit 43 for a predetermined time.
By securely latching the data output signal of 1, the malfunction of reading the data signal due to the wiring delay of the clock signal is prevented when a plurality of flip-flop circuits are connected in cascade.

[0016]

In the above-mentioned conventional semiconductor integrated circuit, it is necessary to select whether to insert a delay circuit for correcting the timing of the data signal and the clock signal supplied to the flip-flop circuit. The control signal is generally set externally at the time of inspection in the manufacturing process or at the start of operation during actual use.

However, there is a drawback that setting the control signal of the selector each time the power is turned on is very troublesome in the process at the time of inspection or at the time of actual use.

The object of the present invention was made in view of the above-mentioned drawbacks, and in a semiconductor integrated circuit device using a large number of flip-flop circuits, it is for correcting the timing of the data signal and the clock signal supplied thereto. It is to provide means for easily setting a control signal from the outside.

[0019]

A semiconductor integrated circuit device of the present invention comprises a control means for delaying an input signal by a delay circuit for a predetermined time, and selectively outputting at least one of the delayed signal and the input signal. In a semiconductor integrated circuit device provided with the selector, the selector selectively outputs the delayed signal and the input signal in response to a predetermined control signal, and the control supplied to these selectors. The signal is configured in combination with an electrically erasable rewritable read-only memory in which signals are preprogrammed.

It is also possible to provide a plurality of flip-flops to which the data signal and the clock signal are respectively supplied via the selecting means.

[0021]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, this semiconductor integrated circuit outputs predetermined control signals DO1, DO2, ..., DO7, DO8 supplied to the flip-flop circuits F1, ..., F8 and the selector 1 included in these flip-flop circuits. A pre-programmed electrical erase rewritable read only memory (EEPROM) 10
At the input end of the ROM 10, a flip-flop circuit F1, ...
..., address signal A for designating selector 1 of F8
1, A2, A3, A4 are connected, and the output signals DO1, DO2, ..., DO7, DO8 of the EEPROM 10 are supplied as control signals to the selector 1, and the corresponding flip-flop circuits F1, F2 ,. It is connected to the control terminals 81 to 88 and 91 to 98 of F8, respectively. The configuration of each of the flip-flop circuits F1, F2, ..., F8 includes the same constituent elements as the flip-flop circuit F of the conventional example, and the same reference numerals are given to the respective constituent elements. In this embodiment, a case where there are eight flip-flop circuits will be described for ease of explanation. Of course, if the number of flip-flop circuits is increased, it is possible to increase the number of bits of the EEPROM corresponding thereto.

The selectors 1 and 2 are, for example, AND
A combination circuit including an OR circuit is used. In the selector 1, the data signal D is connected to one input end of the AND gate 11, and the control signal DO2 from the terminal 91 is inverted in polarity by the inverter 14 and connected to the other input end. The data signal D is connected to one input terminal of the AND gate 12 through the delay circuit 3, and the terminal 9 is connected to the other input terminal.
1, the control signal DO2 is directly connected, the outputs of the AND gates 11 and 12 are connected to the OR gate 13, and the output of the OR gate 13 becomes the output signal of the selector 1.

In the selector 2, the clock signal C is connected to one input terminal of the AND gate 15 through the delay circuit 4, and the control signal DO1 from the terminal 81 is inverted in polarity by the inverter 18 and connected to the other input terminal. Has been done. AND
The data signal D is connected to one input terminal of the gate 15,
The control signal DO1 is directly connected to the other input terminal from the terminal 81, the outputs of the AND gates 15 and 16 are connected to the OR gate 17, and the output of the OR gate 17 becomes the output signal of the selector 2.

For example, when the control signal DO1 is at H level, DO
If 2 is at L level, AND gate 15 is in the selected state,
Since the AND gate 16 is in the non-selected state, the clock signal supplied from the terminal 7 is selected as it is and supplied to the terminal C as the clock signal of the flip-flop circuit 5. On the other hand, the data signal D supplied from the terminal 6 is
Since the D gate 11 is in the non-selected state and the AND gate 12 is in the selected state, the signal via the delay circuit 3 is selected by the selection circuit 2 and supplied to the terminal D as the data signal of the flip-flop circuit 5.

The EEPROM 10 has a known circuit configuration, and only the main part thereof is shown. The present invention is characterized in that the control signal of the selector is set in the EEPROM 10 in advance. That is, when the semiconductor integrated circuit device of the present invention is inspected at the time of manufacture, or the user can decide whether to insert the delay circuit for each flip-flop circuit according to the state of the system to be used.

First, the erase operation of the EEPROM 10 will be described. A1 and A2 are selection signals of the row decoder, and A3 and
A4 becomes a selection signal for the column decoder. As an example, the cell 111 is erased. The inputs A1 and A2 of the row decoder 104 are set to L level and RA1 is set to a high voltage of 20.
Set to V. Further, inputs A3 and A of the column decoder 103
4 is set to L level and CA1 is set to 20V. In this state, the column transistors 107 and 108 are turned on, and the erasing voltage signal 20V at the point a is supplied to the control gate (not shown) of the cell 111.

The bit line B01 becomes the potential at the point b via the data string selecting transistor 108 which is turned on. When the potential at the point b is set to 0V, the cell 111 enters the erased (electron injected) state. Similarly, B02, ..., B
The cell is erased by setting any bit line of 08 to 0V.

Next, in the write operation, the address input A1
When A2 and A2 are set to L level, A3 and A4 are set to L level, and the potential at point a = 0V and the potential at point b = 20V,
0V is applied to the control gate of the cell via the transistor 107, and bit B01 is applied via the transistor 108.
Is supplied with 20V. RA1 = 20 is applied to the select gate (not shown) of the cell 111 by the level shifter 106.
Since V is supplied, the cell is in the write mode, and cell 1
Electrons are emitted from the floating gate of 11.

At the time of reading, the output of the selected level shifters 105 and 106 becomes 5V. In order to select the cell 111, the addresses A1 and A2 are set to L level and A3 and A4 are set to L level as in the case of erasing and writing, and RA1 = 5V and CA1 = 5V. In this mode, the potential at point a is fixed at 0V. Since the transistor 107 and the select gate of the cell 111 are turned on, the potential at the point a = 0V is applied to the control gate of the cell 111 through the transistor 107. Here, if the cell 111 is an erased cell, the memory transistor is an enhancement type and is turned off. Therefore, the memory cell is bit line B0.
No signal is sent to 1.

In this mode, B01 at the point b is held at the potential of 1V, so this 1V level is sensed by the output circuit section 102 and is regarded as the H level. On the other hand, when the cell B01 is a write cell (electron emission), the memory transistor of the cell 111 is a depletion transistor, and therefore the cell is on even if the gate is 0V. Therefore, the bit line B01 is pulled down to the ground potential via the select transistor. Since a pull-up element (not shown) is normally attached to the tip of the bit line B01, the potential of B01 drops to 0.2V. This potential is sensed by the output circuit and set to the L level.

Similarly, in the case of the cell 112, the transistor 1
Row decoder A1 so that 09 and 110 are selected.
And A2 to L level, the column decoder A3 to H level,
A4 can be set to L level to erase, write and read.

Whether the delay circuit is inserted by predicting the delay of the data signal and the clock signal supplied to each of the flip-flop circuits F1 to F8 arranged in advance inside the semiconductor integrated circuit device by the method as described above is determined. Then, the data is programmed so that the delay circuit to be selected can be designated in the EEPROM 10. Further, when the semiconductor integrated circuit device is operated by using the data, or when it is necessary to readjust the insertion of the delay circuits 3 and 4 as a result of operating the entire system mounting the semiconductor integrated circuit device. Also, it can be dealt with by resetting the data of the EEPROM 10, and since the value is stored once set, it is not necessary to reset it every time the system is started.

[0034]

As described above, according to the semiconductor integrated circuit device of the present invention, a plurality of flip-flop circuits arranged inside are subjected to several electrical characteristic tests performed during the manufacturing process of the semiconductor integrated circuit device. Control signal for correcting the timing of the data signal or clock signal of
The optimum timing condition is found and written in the EEPROM. Therefore, since the contents of the EEPROM are retained even when the power is turned off, it is not necessary to reset the control signal each time in the subsequent inspection.

Further, even in the actual use state, it is not necessary to reset the control signal each time the power is turned on, and it is possible to reset the control signal depending on the state of the system.

Therefore, if it takes 0.5 seconds to set the control signal and the time required for the inspection is about 5 seconds, 1
This is a 0% reduction, which is effective in reducing costs.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional semiconductor integrated circuit device.

3A is an explanatory timing chart of the block diagram shown in FIG. FIG. 4B is a timing chart for explaining a malfunction of the block diagram shown in FIG.

FIG. 4 is a block diagram showing another example of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 1, 2 Selector 3, 4 Delay circuit 5, F1, F8 Flip-flop circuit 6 Data signal input terminal 7 Clock signal input terminal 8, 9, 81-88, 91-98 Control signal input terminal 10 EEPROM 11, 12, 15, 16 AND gate 13, 17 OR gate 14, 18 Inverter 101 Input circuit unit 102 Output circuit unit 103 Column decoder 104 Row decoder 105, 106 Level shifter 107-110 Transistor 111, 112 cell A1-A4 Address input DI1-DI8 Setting data input terminal DO1 to DO8 Control signal (EEPROM output signal) CA1, CA2 Column decoder output RA1 Row decoder output

Claims (2)

[Claims] 1. A semiconductor integrated circuit device comprising a control means for delaying an input signal by a delay circuit for a predetermined time, and selectively outputting at least one of the delayed signal and the input signal, wherein the selecting means has a predetermined value. A plurality of selectors for selectively outputting the delayed signal and the input signal in response to the control signal of the control signal, and an electrically erasable rewritable read-only read control program in which the control signal supplied to the selectors is preprogrammed. A semiconductor integrated circuit device characterized by being configured by combining with a memory. 2. The semiconductor integrated circuit device according to claim 1, further comprising a plurality of flip-flops to which a data signal and a clock signal are respectively supplied via said selecting means.