JPH07122975A - High speed scanning radio receiver - Google Patents

Abstract

PURPOSE:To unnecessitate the complicated operation of a user by preliminarily storing frequencies which are unnecesary to be received by a search mode and automatically make them skip. CONSTITUTION:When the existence of the input of a signal is detected by the output voltage of a frequency discriminator 14 in a squelch circuit 16, a squelch signal (SC signal) is transmitted to a CPU 14. When the CPU 24 receives the squelch signal, the CPU checks whether the reception frequency at this time is registered in a skip memory 26 or not. If the frequency is not registered, the mute (MUTE) circuit of a low frequency amplifier is turned OFF, a sound signal is outputted to a speaker 20 and the generation frequency of a frequency synthesizer 22 is fixed. As a result, a scanning is stopped and a station selection is terminated. If the reception frequency is not registered in the skip memory 26, the scanning is continued without stopping it. Namely, frequencies which are not necessary to be received are skipped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a high speed scanning radio receiver,
In particular, the present invention relates to a high-speed scanning wireless receiver in which frequencies unnecessary for reception are stored in advance in search mode and automatically skipped (SKIP).

[0002]

2. Description of the Related Art In a radio receiver provided with a channel memory, a frequency to be heard is stored in advance in the channel memory, and the selected frequency is automatically selected. In such a channel memory type radio receiver, if there is a frequency that is not desired to be heard among the stored frequencies, it has lockout information and skips the frequency.

In contrast to such a channel memory type wireless receiver, there is a frequency synthesizer type high speed scanning wireless receiver which automatically searches by scanning a certain frequency range. Such a high-speed scanning wireless receiver includes a squelch circuit, and when the squelch circuit detects the presence of a signal,
Reception is performed with the frequency generated by the frequency synthesizer fixed.

[0004]

In such a high-speed scanning radio receiver, the squelch circuit selects all the frequencies judged to have a signal input. Therefore, when a station which one does not want to hear is selected, There is a problem that it is annoying because it is necessary to operate so as to move to the scan of.

In addition, the frequency at which the squelch circuit determines that there is a signal input does not include a voice signal and may be noise. Even in such a case, it is troublesome to operate to move to the next scan.

Further, spurious reception cannot be avoided with the squelch circuit.

It is an object of the present invention to provide a high speed scanning radio receiver in which a frequency unnecessary to be received is stored in advance in a search mode and automatically skipped.

[0008]

SUMMARY OF THE INVENTION The present invention relates to a frequency synthesizer type high speed scanning radio receiver, a squelch circuit for detecting the presence or absence of a signal from the output voltage of a frequency discriminator, a skip memory for registering a skip frequency that does not need to be received, When the squelch circuit generates a squelch signal, it is checked whether the reception frequency at that time is registered in the skip memory, and if it is registered, the scan is continued without stopping and the reception frequency is skipped. And a processing device.

When the memory becomes full, the skip frequency registration is performed by deleting the old registration skip frequency.
Make sure to register a new skip frequency.

Further, according to the present invention, in a high speed scanning radio receiver of a frequency synthesizer system, a squelch circuit for detecting the presence or absence of a signal from an output voltage of a frequency discriminator, and a skip memory for registering skip frequencies not required to be received in frequency block units. Then, within the response waiting time of the squelch signal generated by the squelch circuit, first determine which block the reception frequency is included in, then check the skip frequency registered in the corresponding block, and the squelch circuit When a squelch signal is generated, based on the result of the check, if the reception frequency at that time is registered in the skip memory, the scanning is continued without stopping, and the processing device that skips the reception frequency, It is characterized by being provided.

[0011]

1 is a block diagram of a high speed scanning radio receiver according to an embodiment of the present invention. 10 is an antenna, 12 is a radio receiver, 14 is a frequency discriminator, 16 is a squelch circuit, 18 is a low frequency amplifier, 20 is a speaker, 22 is a frequency synthesizer, and 24 is a microcomputer (CP).
U) and 26 are skip memories, and 28 is a keyboard.

In the skip memory 26, frequencies that one does not want to hear and frequencies for spurious reception are registered in advance.
The registration of skip frequency is done by the user
There are two possible cases in which the manufacturer pre-registers the product before shipping.

The CPU 24 stores the frequency range to be searched in a memory (not shown), and sends the PLL data to the frequency synthesizer 22 according to the frequency range in the search mode. The frequency synthesizer 22 supplies the generated frequency to the wireless reception unit 12.

The radio receiver 12 converts the frequency received by the antenna 10 into an intermediate frequency based on the frequency from the frequency synthesizer 22 and supplies it to the frequency discriminator 14. The frequency discriminator 14 discriminates the frequency, converts it into a voltage, and sends it to the squelch circuit 16.

The squelch circuit sends a squelch signal (SC signal) to the CPU 24 when a signal input is detected by the output voltage of the frequency discriminator 14. Upon receiving the squelch signal, the CPU 24 checks whether the reception frequency at this time is registered in the skip memory 26.
If not registered, mute low frequency amplifier (MU
The TE) circuit is turned off to output an audio signal to the speaker 20, while the frequency generated by the frequency synthesizer 22 is fixed. As a result, the scanning stops and the tuning ends.
If the reception frequency is registered in the skip memory 26,
Continue without stopping the scan. That is, frequencies that are unnecessary for reception are skipped.

Although the above is an outline, two specific examples (Examples 1 and 2) will be described in detail below.

Embodiment 1 In this embodiment, the skip memory 26 is a RAM,
The frequency to be skipped is registered by the user and can be deleted if necessary, and the registered frequency is skipped at the time of searching. In this case, the memory has a finite capacity, so when the user registers the skip frequency in the memory, when the memory is full (FULL), the oldest data is erased in order and a new skip frequency is registered. To do.

The operation of the CPU 24 of this embodiment will be described with reference to the flowcharts of FIGS.

The CPU 24 turns on the mute circuit of the low frequency amplifier 18 and disconnects the audio output (step S).
1). The frequency synthesizer 22 has a PLL (Phase)
Locked Loop data is output (step S
2) The squelch signal (SC signal) from the squelch circuit 16 is detected for a predetermined time (SC waiting time). When the SC waiting time ends (step S3), it is determined whether or not the SC signal is detected (step S4). If the SC signal is not detected, the next PLL data is created (step S9), is output to the frequency synthesizer 22, and the scan of the next frequency is started. If the SC signal is detected, the skip memory 26 is checked (step S5).

FIG. 3 is a flow chart showing the checking of the skip memory. In this flowchart,
SKIP_F is the skip flag, MEM_CNT is the count value of the memory check counter, and SKIP_
M (MEM_CNT) is MEM_CN of the skip memory
The T-th data (MEM_CNT: 0 to N), and N indicates the number of skip memories minus one.

In checking the skip memory, first, the memory check counter is cleared (step S
10) It is determined whether or not the skip frequency registered in the address of the skip memory indicated by the count value of the counter (“0” in this case) is equal to the currently received frequency (step S11). If they are equal, the skip flag is set to "1" (step S15). If they are not equal, the count value of the memory check counter is incremented by 1 (step S12).

It is judged whether or not the count value of the memory check counter is larger than N which is the MAX value (step S13). If not larger, the process returns to step S11. When the count value of the memory check counter is larger than N, the skip flag is set to "0" (step S14).

Returning to the flowchart of FIG. 2, step S
In step 6, it is determined whether or not the currently received frequency is registered in the skip memory, that is, whether or not the skip flag is set to "1". If not registered in the skip memory, turn off the mute circuit
Then, the sound is output from the low frequency amplifier 18 to the speaker 20 (step S7). To move to the next search operation, S
It is determined whether or not the C signal is detected (step S
8) If the SC signal is not detected, step S
Go to 9 to scan for the next frequency.

As described above, in the first embodiment, the skip memory is checked by sequentially comparing the data at the head address of the memory with the currently received frequency and returning the result to the skip flag.

As described above, the user registers and deletes the skip frequency in the memory 24. However, since the memory capacity of the memory is limited, when the memory becomes full, the oldest data is deleted. Delete them in order and register new data. This is FAST IN / LA
It can be performed by the ST OUT method.

Hereinafter, (1) memory registration, (2) memory deletion, (3) memory registration when the memory is full (F
AST IN / LAST OUT) will be described in this order.

(1) Registration of Memory When registering a skip frequency in the memory, as shown in FIG. 4, the skip frequencies to be registered are sequentially written from the first address 0 of the skip memory to an empty address. The figure shows a state in which the skip frequency 56.570 MHz is written in the address 6.

FIG. 5 is a flow chart showing the registration operation of the CPU 24. The memory check counter is cleared, and it is checked in order from the first address 0 of the skip memory whether or not it has been registered (steps S20 to S2).
2). If the skip frequency is not registered in the address indicated by the memory check counter, the skip frequency is registered in that address (step S23).

(2) Deletion of Memory When deleting a skip frequency registered in the memory, the address (A) of the memory to be deleted is searched. All the data from the found address of the memory to the address (N-1) immediately before the last address N of the memory are shifted one by one to the previous address. After that, the data in the last address of the memory is cleared. That is, the following operation is performed. FOR i = A TO N−1 SKIP_M (i) = SKIP_M (i + 1) NEXT i SKIP_M (N) = 0 FIG. 6 is a diagram showing how skip frequencies are deleted.
Skip frequency 823.2 registered at address A = 4
An example is shown in which 50 MHz is deleted and the address N is cleared.

FIG. 7 is a flow chart showing the deleting operation of the CPU 24. The frequency to be deleted is found in the skip memory 26 (steps S30 to S33). Assuming that the count value of the memory check counter when it is found is A = 4 as shown in FIG. 6, address A + address A +
The process of copying the data of No. 1 to the address N from address 4
-1 is sequentially performed (steps S34 to S37) to clear the data at the address N, that is, the unregistered state is set (step S38).

(3) Registration with full memory (FAS
(T IN / LAST OUT) When registering the skip frequency in the memory, I searched for a vacant address, but if there is no vacant address anywhere,
All the data from the first address 0 of the memory to the address (N-1) immediately before the last address N of the memory are shifted one by one to the previous address. After that, the skip frequency to be registered is written in the last address N that has become an empty address. That is, the following operation is performed. FOR i = 0 TO N-1 SKIP_M (i) = SKIP M (i + 1) NEXT i SKIP_M (N) = registered frequency Steps S24 to S29 in FIG. 5 show this operation of the CPU 24. In step S24, if the count value of the memory check counter becomes larger than the MAX value (N), the memory check counter is cleared,
The data of the address (A + 1) is copied to the address A of the skip memory. This process is performed from A = 0 to A = N-1 (steps S25 to S28). Then, the skip frequency is registered in the address N (step S29).

FIG. 8 is a diagram showing the state of the memory. The example shows that the oldest data 25.500 MHz is deleted and new data 150.860 MHz is added.

According to the first embodiment described above, when the memory is full, the oldest data is deleted in order, so that the memory can be effectively used. In addition, skip frequency check (frequency comparison)
Is performed after the "SC signal present" is detected, not when the PLL data is output.
Even when the operation of U24 is slow, it is possible to prevent the search speed from being delayed.

Embodiment 2 In this embodiment, the skip memory 26 is a ROM,
The frequencies to be skipped are registered in advance by the maker side, and the registered frequencies are skipped during the search. In this case, since the memory is a ROM, the user cannot register the skip frequency.

In this method, the frequency which is not desired to be received,
You can register many harmonics of the local oscillation frequency and frequencies that are known to be noise in advance, but the more skip frequencies you have, the longer it takes to check (comparison of frequencies),
Search speed becomes slow. Therefore, in this embodiment,
"Frequency check time", "effective use of idle time" and "efficient ROM" are designed so that the search speed does not slow down.

Regarding the effective use of the idle time, after the PLL data is output, it is checked in advance whether the received frequency is the skip frequency or not by using the PLL lock time and SC response waiting time. The reception frequency is PLL
The skip frequency actually checks the PLL output frequency corresponding to the reception frequency to be skipped because it is determined if the output frequency is known.

In order to shorten the check time, the frequency check range is first roughly limited, and the frequency is finely checked within the limited range. The data to be checked is divided into blocks according to the frequency check range in advance, and "END CODE" for determining the end of the check is set at the end of the block to be checked.

At the end of the block, "END COD
By setting E ″, the number of frequency data to be checked can be arbitrarily set for each block, so that the ROM efficiency can be improved.

FIG. 9 is a flow chart showing the operation of the CPU 24. The difference from the flowchart of FIG. 2 is that the skip frequency check (step S42) is performed within the SC response waiting time, and the other steps are almost the same as the flowchart of FIG. Is omitted.

FIG. 10 is a flow chart showing the skip frequency check (step S42) of FIG. In this flowchart, REF_ADR indicates a reference address and REF indicates a reference label.

The reference label is R, as shown in FIG.
Three of EF1, REF2, REF3 are defined,
Each reference label is a frequency check range blocked as shown in FIG. 12, and a block 1 (REF1)
Is a block 2 (REF2) for frequencies in the 25 MHz range.
Is a block 3 (REF3) for frequencies in the 26 MHz range.
Has registered frequencies in the 27 MHz range in advance.

Now, in the flow chart of FIG. 10, P
It is determined whether the LL output frequency is within the frequency range of blocks 1, 2, and 3 (steps S50 and S5).
1). If it is within the range of block 1, REF the reference address
1 (step S52), if block 2, the reference address is set to REF2 (step S53), and if block 3, the reference address is set to REF3 (step S5).
4). It is checked in block units whether or not the PLL output frequency is registered in the block corresponding to the reference label (steps S55 to S58), and if registered, the skip flag is set to "1" (step S60).
When "END CODE" is detected, the skip flag is set to "0" (step S59).

After the above skip frequency check, the SC signal is detected in step S44, and if it is determined in step S46 that the skip flag is set to "1", the currently output frequency is the skip frequency. The process moves to the frequency of.

As described above, according to the second embodiment, S
Since the C response waiting time is used to check whether the PLL output frequency is the skip frequency or not, it is possible to effectively use the idle time. Further, since the skip frequency is divided into blocks, it is first checked which block the PLL output frequency is within, and then the details in that block are checked. Therefore, it is necessary to check all registered data. Since there is no such check, the check time can be shortened.

[0045]

As described above, according to the present invention, frequencies that are not required to be received, such as frequencies that one does not want to hear or frequencies caused by spurious reception, are stored in the skip memory.
Since these frequencies can be skipped in the search mode, there is an effect that there is no annoyance and a user's complicated operation is unnecessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a high speed scanning wireless receiver of the present invention.

FIG. 2 is a flowchart showing the operation of the CPU in the first embodiment.

FIG. 3 is a flowchart showing the operation of the CPU in the first embodiment.

FIG. 4 is a diagram showing how memory is registered.

FIG. 5 is a flowchart showing a CPU registration operation.

FIG. 6 is a diagram showing how a skip frequency is deleted.

FIG. 7 is a flowchart showing an operation of deleting a CPU.

FIG. 8 is a diagram showing a state of a memory in which old data is deleted and new data is added.

FIG. 9 is a flowchart showing the operation of the CPU in the second embodiment.

FIG. 10 is a flowchart showing a skip frequency check.

FIG. 11 is a diagram showing a reference label.

FIG. 12 is a diagram showing a frequency check range that is blocked.

[Explanation of symbols]

 12 wireless receiver 14 frequency discriminator 16 squelch circuit 18 low frequency amplifier 22 frequency synthesizer 24 CPU 26 skip memory 28 keyboard

Claims (4)

[Claims] 1. A high frequency scanning radio receiver of a frequency synthesizer system, wherein a squelch circuit for detecting the presence or absence of a signal from an output voltage of a frequency discriminator, a skip memory for registering a skip frequency that does not require reception, and a squelch circuit for squelch circuit. When a signal is generated, the reception frequency at that time is checked whether or not it is registered in the skip memory, and if it is registered, the scanning is continued without stopping, and a processing device that skips the reception frequency, A high-speed scanning wireless receiver comprising: 2. When registering the skip frequency, when the memory becomes full, the old skip frequency is deleted,
The fast scanning radio receiver according to claim 1, wherein a new skip frequency is registered. 3. The skip frequency registered in the first address of the memory is deleted, the content of the address (A + 1) is copied to the address A, and a new skip frequency is registered in the last address. A high-speed scanning wireless receiver according to Item 2. 4. A high-speed scanning wireless receiver of a frequency synthesizer system, a squelch circuit for detecting the presence or absence of a signal from the output voltage of a frequency discriminator, a skip memory for registering skip frequencies not required for reception in frequency block units, Within the response waiting time of the squelch signal generated by the squelch circuit, first determine which block contains the reception frequency, then check the skip frequency registered in the corresponding block, and the squelch circuit outputs the squelch signal. When it occurs, based on the result of the check, if the reception frequency at that time is registered in the skip memory, the processing is continued without stopping the scan and the reception frequency is skipped. High-speed scanning wireless receiver featuring.