JPH07122609A - Method for analyzing detective bump - Google Patents

Method for analyzing detective bump

Info

Publication number
JPH07122609A
JPH07122609A JP26766893A JP26766893A JPH07122609A JP H07122609 A JPH07122609 A JP H07122609A JP 26766893 A JP26766893 A JP 26766893A JP 26766893 A JP26766893 A JP 26766893A JP H07122609 A JPH07122609 A JP H07122609A
Authority
JP
Japan
Prior art keywords
bump
substrate
resin
bumps
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP26766893A
Other languages
Japanese (ja)
Inventor
Satoru Ito
悟 伊藤
Yoshihiro Matsuoka
由博 松岡
Yoshitaka Niwa
喜敬 丹羽
Tomoko Katagiri
友子 片桐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP26766893A priority Critical patent/JPH07122609A/en
Publication of JPH07122609A publication Critical patent/JPH07122609A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To detect insufficient connection at a bump positively while protecting the bump against damage when it is exfoliated from a substrate. CONSTITUTION:In a semiconductor device where a semiconductor chip 1 is connected with a substrate 3 through a bump 2, a resin 8 is cured around the bump. The substrate is then heated to exfoliate the semiconductor chip therefrom and the surface state of the bump is observed. An insufficiently connected bump is then specified based on the adhesion of resin or the abnormal surface state.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はバンプの不良解析方法に
係り, バンプによる接続を行った半導体装置の接続状況
を検査する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump failure analysis method, and more particularly to a method for inspecting the connection status of a semiconductor device connected by bumps.

【0002】[0002]

【従来の技術】近年, 半導体実装技術として, 一つのパ
ッケージ内に複数のチップを搭載する技術が用いられる
ようになってきた。
2. Description of the Related Art In recent years, as a semiconductor mounting technique, a technique of mounting a plurality of chips in one package has been used.

【0003】この技術は図3に示されるように,配線さ
れたマイクロチップサブストレート(MCS) 3 上に, 複数
のチップ 1をバンプ 2を介して搭載し,マイクロチップ
サブストレートをマイクロチップモジュール(MCM) 4 と
呼ばれるパッケージ内に収納し,マイクロチップモジュ
ールに設けられた外部導出リード 5とマイクロチップサ
ブストレートの端子とをワイヤ 7等で接続した構造であ
る。
As shown in FIG. 3, this technique mounts a plurality of chips 1 on a wired microchip substrate (MCS) 3 via bumps 2, and mounts the microchip substrate on a microchip module ( It is housed in a package called MCM) 4 and has a structure in which the external lead 5 provided on the microchip module and the terminal of the microchip substrate are connected by wires 7 or the like.

【0004】このような半導体装置の不良解析を行う際
には,チップをマイクロチップサブストレートから剥離
しなければならない。このための方法として従来は,ヒ
ートブロック上に半導体装置を載せ,パッケージを開封
し,熱的にチップをマイクロチップサブストレートから
剥離していた。あるいは,硝酸や硫酸等の薬液を用いて
剥離を行っていた。
When performing a failure analysis of such a semiconductor device, the chip must be separated from the microchip substrate. As a method for this purpose, conventionally, a semiconductor device was placed on a heat block, the package was opened, and the chip was thermally separated from the microchip substrate. Alternatively, peeling is performed using a chemical solution such as nitric acid or sulfuric acid.

【0005】[0005]

【発明が解決しようとする課題】従来の方法による不良
解析では,パッケージの開封(キャップの剥離)までは
問題なくできるが,チップとマイクロチップサブストレ
ートの剥離において,バンプが熱や薬液によって損傷を
受けるため,バンプでの不良の検出が困難であった。
In the defect analysis by the conventional method, the opening of the package (peeling of the cap) can be performed without any problem, but the bumps are damaged by heat or a chemical solution when the chip and the microchip substrate are peeled. Therefore, it was difficult to detect defects in the bumps.

【0006】本発明はバンプとサブストレートとの剥離
の際に,バンプを損傷しないようにしてバンプでの接続
不良の検出を確実にすることを目的とする。
An object of the present invention is to prevent the bumps from being damaged at the time of peeling the bumps from the substrate and to ensure the detection of the connection failure at the bumps.

【0007】[0007]

【課題を解決するための手段】上記課題の解決は,半導
体チップ 1がバンプ 2を介してサブストレート 3に接続
された半導体装置に対し,該バンプの周囲を樹脂 8で固
化し,次いで,該サブストレートを加熱して該半導体チ
ップを該サブストレートより剥離し,次いで該バンプの
表面状態を観察して樹脂の付着の有無及び表面状態の異
常により接続不良のバンプを特定することを特徴とする
バンプの不良解析方法。
[Means for Solving the Problems] To solve the above problems, a semiconductor device in which a semiconductor chip 1 is connected to a substrate 3 via bumps 2 is solidified around the bumps with a resin 8 and then the bumps are solidified. Characterized in that the substrate is heated to peel off the semiconductor chip from the substrate, and then the surface condition of the bumps is observed to identify bumps with poor connection based on the presence or absence of resin adhesion and abnormal surface condition. Bump defect analysis method.

【0008】[0008]

【作用】本発明ではバンプ周辺の空洞部に低粘度の熱硬
化性樹脂を流し込んで硬化させた後,熱的にチップとサ
ブストレートとを剥がすようにしているため,樹脂に保
護されたバンプは損傷することなく,接続不良部のバン
プ表面には樹脂が付着しているかどうか,あるいは剥離
面の異常等を観察することができる。従って,バンプで
の接続不良の検出が可能となる。
In the present invention, since a low-viscosity thermosetting resin is poured into the cavity around the bump to cure the resin, the chip and the substrate are thermally peeled off. Without damage, it is possible to observe whether the resin is attached to the bump surface of the defective connection portion or whether the peeled surface is abnormal. Therefore, it is possible to detect the connection failure at the bump.

【0009】[0009]

【実施例】図1は本発明の実施例を説明する断面図であ
る。図において, 1はチップ, 2は半田バンプ, 3はマ
イクロチップサブストレート(MCS) , 4はマイクロチッ
プモジュール(MCM), 5 はリード, 6は金属等からなる
キャップ, 7はボンディング・ワイヤ, 8 は注入された
樹脂である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view for explaining an embodiment of the present invention. In the figure, 1 is a chip, 2 is a solder bump, 3 is a microchip substrate (MCS), 4 is a microchip module (MCM), 5 is a lead, 6 is a cap made of metal or the like, 7 is a bonding wire, 8 Is the injected resin.

【0010】図3に示される半導体装置に対して具体的
な不良解析手順の例を次に示す。 (1) キャップ 6に孔を開けて, キャップ 6とマイクロチ
ップモジュール 4とで形成される空間に低粘度の熱硬化
性樹脂 8, 例えばアラルダイトを注入する。樹脂の注入
量はバンプ周辺の空洞部を埋める程度でよい。 (2) 半導体装置を加熱して樹脂を硬化させる。 (3)半導体装置を加熱されたヒートブロック上に載せ,
チップをサブストレートから剥離する。 (4)バンプ表面を金属顕微鏡等により観察する。
An example of a specific failure analysis procedure for the semiconductor device shown in FIG. 3 is shown below. (1) A hole is made in the cap 6, and a low-viscosity thermosetting resin 8, such as araldite, is injected into the space formed by the cap 6 and the microchip module 4. The amount of resin injected may be such that the cavity around the bump is filled. (2) The semiconductor device is heated to cure the resin. (3) Place the semiconductor device on the heated heat block,
Peel the chip from the substrate. (4) Observe the bump surface with a metallographic microscope.

【0011】この際, 或るバンプに樹脂が付着しておれ
ば, このバンプはオープン不良であったことが実証され
る〔図2(A) 参照〕。また,或るバンプの表面に異物が
介在したり, 厚い酸化膜に覆われているいる場合も, こ
のバンプはオープン不良であったことがわかる〔図2
(B) 参照〕。
At this time, if the resin adheres to a certain bump, it is verified that this bump has an open defect [see FIG. 2 (A)]. It can also be seen that when a foreign substance is present on the surface of a bump or the bump is covered with a thick oxide film, this bump has an open defect [Fig.
(B)].

【0012】実施例では樹脂の硬化に熱を用いたが,キ
ャップをチップとは別個に剥がせる構造の半導体装置で
は,樹脂に光を照射して樹脂を硬化させることもでき
る。
Although heat is used to cure the resin in the embodiments, in a semiconductor device having a structure in which the cap can be peeled off separately from the chip, the resin can be irradiated with light to cure the resin.

【0013】[0013]

【発明の効果】本発明によれば,バンプを損傷しないよ
うに, バンプとサブストレートとを剥離することができ
るようになった。この結果, バンプでの接続不良の検出
を確実にすることが可能となり,デバイスの信頼性向上
に寄与することができた。
According to the present invention, the bump and the substrate can be separated from each other without damaging the bump. As a result, it became possible to reliably detect defective connections at bumps, which contributed to improved device reliability.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例を説明する断面図FIG. 1 is a sectional view illustrating an embodiment of the present invention.

【図2】 実施例における不良バンプの断面図FIG. 2 is a sectional view of a defective bump in the example.

【図3】 バンプによる接続を行った半導体装置の断面
FIG. 3 is a cross-sectional view of a semiconductor device connected by bumps.

【符号の説明】[Explanation of symbols]

1 チップ 2 バンプ 3 マイクロチップサブストレート (MCS) 4 マイクロチップモジュール(MCM) 5 リード 6 キャップ 7 ボンディング・ワイヤ 8 樹脂 9 異物 1 chip 2 bump 3 microchip substrate (MCS) 4 microchip module (MCM) 5 lead 6 cap 7 bonding wire 8 resin 9 foreign material

───────────────────────────────────────────────────── フロントページの続き (72)発明者 丹羽 喜敬 愛知県春日井市高蔵寺町2丁目1844番2 富士通ヴィエルエスアイ株式会社内 (72)発明者 片桐 友子 愛知県春日井市高蔵寺町2丁目1844番2 富士通ヴィエルエスアイ株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshitaka Niwa, Yoshitaka Niwa 1844-2, Kozoji-cho, Kasugai-shi, Aichi Fujitsu Vielle SII Co., Ltd. (72) Inventor Tomoko Katagiri 2-1844-2, Kozoji-cho, Kasugai-shi, Aichi Within Fujitsu VIS Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップ(1) がバンプ(2) を介して
サブストレート(3)に接続された半導体装置に対し,該
バンプの周囲を樹脂(8) で固化し,次いで,該サブスト
レートを加熱して該半導体チップを該サブストレートよ
り剥離し,次いで該バンプの表面状態を観察して樹脂の
付着の有無及び表面状態の異常により接続不良のバンプ
を特定することを特徴とするバンプの不良解析方法。
1. A semiconductor device in which a semiconductor chip (1) is connected to a substrate (3) through a bump (2), the periphery of the bump is solidified with a resin (8), and then the substrate is solidified. Of the bump, characterized in that the semiconductor chip is peeled off from the substrate by heating, and then the surface condition of the bump is observed to identify the bump with poor connection based on the presence or absence of resin adhesion and the abnormal surface condition. Failure analysis method.
JP26766893A 1993-10-27 1993-10-27 Method for analyzing detective bump Withdrawn JPH07122609A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26766893A JPH07122609A (en) 1993-10-27 1993-10-27 Method for analyzing detective bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26766893A JPH07122609A (en) 1993-10-27 1993-10-27 Method for analyzing detective bump

Publications (1)

Publication Number Publication Date
JPH07122609A true JPH07122609A (en) 1995-05-12

Family

ID=17447877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26766893A Withdrawn JPH07122609A (en) 1993-10-27 1993-10-27 Method for analyzing detective bump

Country Status (1)

Country Link
JP (1) JPH07122609A (en)

Similar Documents

Publication Publication Date Title
US5424254A (en) Process for recovering bare semiconductor chips from plastic packaged modules by thermal shock
JP2662190B2 (en) Electronic element assembly and rework method
US5682065A (en) Hermetic chip and method of manufacture
JPH04226046A (en) Bonding method of electronic chip
US7573006B2 (en) Apparatus relating to the reconstruction of semiconductor wafers for wafer-level processing
KR100227121B1 (en) A test fixture having an opening for exposing the back side of a semiconductor chip
JPH0582616A (en) Method and apparatus for connecting circuit chip and temporary carrier for burn-in test
US6117352A (en) Removal of a heat spreader from an integrated circuit package to permit testing of the integrated circuit and other elements of the package
JP2000040773A (en) Resin-sealed semiconductor device and manufacture thereof
US20020045294A1 (en) A method for creating printed circuit board substrates having solder mask-free edges
US6395129B1 (en) Process to decapsulate a FBGA package
US6342398B1 (en) Method of backside emission analysis for BGA packaged IC's
US7067332B1 (en) Method for die removal from plastic packages
JP2006196592A (en) Method of inspecting resin-sealed semiconductor device
JPH07122609A (en) Method for analyzing detective bump
US5990543A (en) Reframed chip-on-tape die
JPH03171655A (en) Semiconductor device and manufacture thereof
US6159838A (en) Method of performing rework test on integrated circuit packages
KR100744029B1 (en) Method for decapping packaged semiconductor device chip
Schafft Failure analysis of wire bonds
JP2003151981A (en) Semiconductor device and manufacturing method thereof
US6127194A (en) Package removal for FBGA devices
Selig et al. Corrosion in plastic packages-sensitive initial delamination recognition
Ngo Die Exposure
GB2295722A (en) Packaging integrated circuits

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20010130